Lines Matching +full:ddr +full:- +full:wb +full:- +full:channels
1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/qca,ath79-ddr-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Atheros AR7xxx/AR9xxx DDR controller
10 - Krzysztof Kozlowski <krzk@kernel.org>
13 The DDR controller of the AR7xxx and AR9xxx families provides an interface to
14 flush the FIFO between various devices and the DDR. This is mainly used by
21 - items:
22 - const: qca,ar9132-ddr-controller
23 - const: qca,ar7240-ddr-controller
24 - items:
25 - enum:
26 - qca,ar7100-ddr-controller
27 - qca,ar7240-ddr-controller
29 "#qca,ddr-wb-channel-cells":
40 - compatible
41 - "#qca,ddr-wb-channel-cells"
42 - reg
47 - |
48 ddr_ctrl: memory-controller@18000000 {
49 compatible = "qca,ar9132-ddr-controller",
50 "qca,ar7240-ddr-controller";
53 #qca,ddr-wb-channel-cells = <1>;
56 interrupt-controller {
58 qca,ddr-wb-channel-interrupts = <2>, <3>, <4>, <5>;
59 qca,ddr-wb-channels = <&ddr_ctrl 3>, <&ddr_ctrl 2>,