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Searched +full:d +full:- +full:tlb +full:- +full:size (Results 1 – 25 of 300) sorted by relevance

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/linux/arch/riscv/boot/dts/sifive/
H A D	fu540-c000.dtsi	`1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 /* Copyright (c) 2018-2019 SiFive, Inc */ 4 /dts-v1/; 6 #include <dt-bindings/clock/sifive-fu540-prci.h> 9 #address-cells = <2>; 10 #size-cells = <2>; 11 compatible = "sifive,fu540-c000", "sifive,fu540"; 23 #address-cells = <1>; 24 #size-cells = <0>; 28 i-cache-block-size = <64>; [all …]`
H A D	fu740-c000.dtsi	`1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 4 /dts-v1/; 6 #include <dt-bindings/clock/sifive-fu740-prci.h> 9 #address-cells = <2>; 10 #size-cells = <2>; 11 compatible = "sifive,fu740-c000", "sifive,fu740"; 23 #address-cells = <1>; 24 #size-cells = <0>; 28 i-cache-block-size = <64>; 29 i-cache-sets = <128>; [all …]`
/linux/arch/riscv/boot/dts/microchip/
H A D	mpfs.dtsi	`1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 /* Copyright (c) 2020-2021 Microchip Technology Inc */ 4 /dts-v1/; 5 #include "dt-bindings/clock/microchip,mpfs-clock.h" 8 #address-cells = <2>; 9 #size-cells = <2>; 14 #address-cells = <1>; 15 #size-cells = <0>; 16 timebase-frequency = <1000000>; 21 i-cache-block-size = <64>; [all …]`
/linux/arch/powerpc/boot/dts/
H A D	microwatt.dts	`1 /dts-v1/; 4 #size-cells = <0x02>; 5 #address-cells = <0x02>; 6 model-name = "microwatt"; 7 compatible = "microwatt-soc"; 13 reserved-memory { 14 #size-cells = <0x02>; 15 #address-cells = <0x02>; 26 #clock-cells = <0>; 27 compatible = "fixed-clock"; [all …]`
/linux/Documentation/core-api/
H A D	cachetlb.rst	2 Cache and TLB Flushing Under Linux 7 This document describes the cache/tlb flushing interfaces called 17 thinking SMP cache/tlb flushing must be so inefficient, this is in 23 First, the TLB flushing interfaces, since they are the simplest. The 24 "TLB" is abstracted under Linux as something the cpu uses to cache 25 virtual-->physical address translations obtained from the software 27 possible for stale translations to exist in this "TLB" cache. 44 the TLB. After running, this interface must make sure that 47 there will be no entries in the TLB for 'mm'. 57 address translations from the TLB. After running, this [all …]
/linux/arch/parisc/kernel/
H A D	cache.c	6 * Copyright (C) 1999-2006 Helge Deller <deller@gmx.de> (07-13-1999) 10 * Cache and TLB management 55 void flush_data_cache_local(void ); / flushes local data-cache only / 56 void flush_instruction_cache_local(void); / flushes local code-cache only / 62 by software. We need a spinlock around all TLB flushes to ensure 125 test_bit(PG_dcache_dirty, &folio->flags)) { in __update_cache() 126 while (nr--) in __update_cache() 128 clear_bit(PG_dcache_dirty, &folio->flags); in __update_cache() 130 while (nr--) in __update_cache() 139 seq_printf(m, "I-cache\t\t: %ld KB\n", in show_cache_info() [all …]
/linux/arch/arc/mm/
H A D	tlb.c	1 // SPDX-License-Identifier: GPL-2.0-only 3 * TLB Management (flush/create/diagnostics) for MMUv3 and MMUv4 5 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com) 26 * Utility Routine to erase a J-TLB entry 63 /* Locate the TLB entry for this vaddr + ASID / in tlb_entry_erase() 89 with existing location. This will cause Write CMD to over-write in tlb_entry_insert() 95 /* setup the other half of TLB entry (pfn, rwx..) / in tlb_entry_insert() 101 which doesn't flush uTLBs. I'd rather be safe than sorry. in tlb_entry_insert() 131 * Un-conditionally (without lookup) erase the entire MMU contents 139 int num_tlb = mmu->sets * mmu->ways; in local_flush_tlb_all() [all …]
H A D	tlbex.S	1 /* SPDX-License-Identifier: GPL-2.0-only / 3 TLB Exception Handling for ARC 5 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com) 8 * -MMU v1: moved out legacy code into a separate file 9 * -MMU v3: PD{0,1} bits layout changed: They don't overlap anymore, 13 * -For MMU V2, we need not do heuristics at the time of committing a D-TLB 14 * entry, so that it doesn't knock out its I-TLB entry 15 * -Some more fine tuning: 19 * -Practically rewrote the I/D TLB Miss handlers 26 * -Passing ECR (Exception Cause REG) to do_page_fault( ) for printing [all …]
/linux/arch/riscv/boot/dts/starfive/
H A D	jh7110.dtsi	`1 // SPDX-License-Identifier: GPL-2.0 OR MIT 7 /dts-v1/; 8 #include <dt-bindings/clock/starfive,jh7110-crg.h> 9 #include <dt-bindings/power/starfive,jh7110-pmu.h> 10 #include <dt-bindings/reset/starfive,jh7110-crg.h> 11 #include <dt-bindings/thermal/thermal.h> 15 #address-cells = <2>; 16 #size-cells = <2>; 19 #address-cells = <1>; 20 #size-cells = <0>; [all …]`
/linux/include/asm-generic/
H A D	tlb.h	1 /* SPDX-License-Identifier: GPL-2.0-or-later / 2 / include/asm-generic/tlb.h 4 * Generic TLB shootdown code 32 * Generic MMU-gather implementation. 35 * correct and efficient ordering of freeing pages and TLB invalidation 218 tlb_remove_table(tlb,page) global() argument 279 tlb_delay_rmap(tlb) global() argument 293 tlb_delay_rmap(tlb) global() argument 294 tlb_flush_rmaps(struct mmu_gather * tlb,struct vm_area_struct * vma) tlb_flush_rmaps() argument 362 __tlb_adjust_range(struct mmu_gather * tlb,unsigned long address,unsigned int range_size) __tlb_adjust_range() argument 370 __tlb_reset_range(struct mmu_gather * tlb) __tlb_reset_range() argument 404 tlb_flush(struct mmu_gather * tlb) tlb_flush() argument 418 tlb_flush(struct mmu_gather * tlb) tlb_flush() argument 437 tlb_update_vma_flags(struct mmu_gather * tlb,struct vm_area_struct * vma) tlb_update_vma_flags() argument 455 tlb_flush_mmu_tlbonly(struct mmu_gather * tlb) tlb_flush_mmu_tlbonly() argument 469 tlb_remove_page_size(struct mmu_gather * tlb,struct page * page,int page_size) tlb_remove_page_size() argument 476 __tlb_remove_page(struct mmu_gather * tlb,struct page * page,bool delay_rmap) __tlb_remove_page() argument 486 tlb_remove_page(struct mmu_gather * tlb,struct page * page) tlb_remove_page() argument 491 tlb_remove_ptdesc(struct mmu_gather * tlb,void * pt) tlb_remove_ptdesc() argument 497 tlb_remove_page_ptdesc(struct mmu_gather * tlb,struct ptdesc * pt) tlb_remove_page_ptdesc() argument 502 tlb_change_page_size(struct mmu_gather * tlb,unsigned int page_size) tlb_change_page_size() argument 515 tlb_get_unmap_shift(struct mmu_gather * tlb) tlb_get_unmap_shift() argument 529 tlb_get_unmap_size(struct mmu_gather * tlb) tlb_get_unmap_size() argument 539 tlb_start_vma(struct mmu_gather * tlb,struct vm_area_struct * vma) tlb_start_vma() argument 550 tlb_end_vma(struct mmu_gather * tlb,struct vm_area_struct * vma) tlb_end_vma() argument 574 tlb_flush_pte_range(struct mmu_gather * tlb,unsigned long address,unsigned long size) tlb_flush_pte_range() argument 575 tlb_flush_pte_range(struct mmu_gather * tlb,unsigned long address,unsigned long size) tlb_flush_pte_range() argument 581 tlb_flush_pmd_range(struct mmu_gather * tlb,unsigned long address,unsigned long size) tlb_flush_pmd_range() argument 582 tlb_flush_pmd_range(struct mmu_gather * tlb,unsigned long address,unsigned long size) tlb_flush_pmd_range() argument 588 tlb_flush_pud_range(struct mmu_gather * tlb,unsigned long address,unsigned long size) tlb_flush_pud_range() argument 589 tlb_flush_pud_range(struct mmu_gather * tlb,unsigned long address,unsigned long size) tlb_flush_pud_range() argument 595 tlb_flush_p4d_range(struct mmu_gather * tlb,unsigned long address,unsigned long size) tlb_flush_p4d_range() argument 596 tlb_flush_p4d_range(struct mmu_gather * tlb,unsigned long address,unsigned long size) tlb_flush_p4d_range() argument 603 __tlb_remove_tlb_entry(struct mmu_gather * tlb,pte_t * ptep,unsigned long address) __tlb_remove_tlb_entry() argument 615 tlb_remove_tlb_entry(tlb,ptep,address) global() argument 628 tlb_remove_tlb_entries(struct mmu_gather * tlb,pte_t * ptep,unsigned int nr,unsigned long address) tlb_remove_tlb_entries() argument 641 tlb_remove_huge_tlb_entry(h,tlb,ptep,address) global() argument 660 __tlb_remove_pmd_tlb_entry(tlb,pmdp,address) global() argument 663 tlb_remove_pmd_tlb_entry(tlb,pmdp,address) global() argument 674 __tlb_remove_pud_tlb_entry(tlb,pudp,address) global() argument 677 tlb_remove_pud_tlb_entry(tlb,pudp,address) global() argument 702 pte_free_tlb(tlb,ptep,address) global() argument 711 pmd_free_tlb(tlb,pmdp,address) global() argument 720 pud_free_tlb(tlb,pudp,address) global() argument 729 p4d_free_tlb(tlb,pudp,address) global() argument [all...]
/linux/Documentation/arch/loongarch/
H A D	introduction.rst	1 .. SPDX-License-Identifier: GPL-2.0 7 LoongArch is a new RISC ISA, which is a bit like MIPS or RISC-V. There are 8 currently 3 variants: a reduced 32-bit version (LA32R), a standard 32-bit 9 version (LA32S) and a 64-bit version (LA64). There are 4 privilege levels 22 ---- 24 LoongArch has 32 GPRs ( ``$r0`` ~ ``$r31`` ); each one is 32-bit wide in LA32 25 and 64-bit wide in LA64. ``$r0`` is hard-wired to zero, and the other registers 26 are not architecturally special. (Except ``$r1``, which is hard-wired as the 30 the LoongArch ELF psABI spec, in :ref:`References <loongarch-references>`: 40 ``$r4``-``$r11`` ``$a0``-``$a7`` Argument registers No [all …]
/linux/arch/parisc/include/uapi/asm/
H A D	pdc.h	1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note / 14 #define PDC_BAD_PROC -1 / Called non-existent procedure/ 15 #define PDC_BAD_OPTION -2 / Called with non-existent option / 16 #define PDC_ERROR -3 / Call could not complete without an error / 17 #define PDC_NE_MOD -5 / Module not found / 18 #define PDC_NE_CELL_MOD -7 / Cell module not found / 19 #define PDC_NE_BOOTDEV -9 / Cannot locate a console device or boot device / 20 #define PDC_INVALID_ARG -10 / Called with an invalid argument / 21 #define PDC_BUS_POW_WARN -12 / Call could not complete in allowed power budget / 22 #define PDC_NOT_NARROW -17 / Narrow mode not supported */ [all …]
/linux/arch/sparc/kernel/
H A D	tsb.S	`1 /* SPDX-License-Identifier: GPL-2.0 / 17 / Invoked from TLB miss handler, we are in the 23 * %g3: FAULT_CODE_{D,I}TLB 46 * %g1 -- PAGE_SIZE TSB entry address 47 * %g3 -- FAULT_CODE_{D,I}TLB 48 * %g4 -- missing virtual address 49 * %g6 -- TAG TARGET (vaddr >> 22) 67 cmp %g5, -1 106 * %g1 -- TSB entry address 107 * %g3 -- FAULT_CODE_{D,I}TLB [all …]`
H A D	ktlb.S	1 /* SPDX-License-Identifier: GPL-2.0 / 2 / arch/sparc64/kernel/ktlb.S: Kernel mapping TLB miss handling. 57 /* fallthrough to TLB load / 70 instruction get nop'd out and we get here to branch 71 * to the sun4v tlb load code. The registers are setup 78 * The sun4v TLB load wants the PTE in %g3 so we fix that 148 /* Index through the base page size TSB even for linear 169 /* fallthrough to TLB load / 173 661: stxa %g5, [%g0] ASI_DTLB_DATA_IN ! Reload TLB 182 instruction get nop'd out and we get here to branch [all …]
/linux/tools/perf/Documentation/
H A D	perf-mem.txt	`1 perf-mem(1) 5 ---- 6 perf-mem - Profile memory accesses 9 -------- 14 ----------- 20 and stores are sampled. Use the -t option to limit to loads or stores. 22 Note that on Intel systems the memory latency reported is the use-latency, 27 and kernel support is required. See linkperf:perf-arm-spe[1] for a setup guide. 32 -------------- 33 -f:: [all …]`
/linux/tools/perf/pmu-events/arch/powerpc/power9/
H A D	other.json	50 …"BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from anothe… 65 "BriefDescription": "Read-write data cache collisions" 75 … "BriefDescription": "Data ERAT Miss (Data TLB Access) page size 16G (hpt mode) or 1G (radix mode)" 85 …"BriefDescription": "A radix translation attempt missed in the TLB and all levels of page walk cac… 90 "BriefDescription": "D-cache invalidates sent over the reload bus to the core" 200 "BriefDescription": "Read-write data cache collisions" 280 …-word boundary, which causes it to require an additional slice than than what normally would be re… 300 "BriefDescription": "I-cache Invalidates sent over the realod bus to the core" 395 …-word boundary, which causes it to require an additional slice than than what normally would be re… 430 "BriefDescription": "TM Load (fav or non-fav) ran into conflict (failed)" [all …]
H A D	pipeline.json	10 "BriefDescription": "Number of I-ERAT reloads" 25 …"BriefDescription": "Finish stall because the NTF instruction was a multi-cycle instruction issued… 35 …"BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's L4 on a differ… 40 …"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 without confl… 80 …"BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from anothe… 95 …"BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from anothe… 110 "BriefDescription": "Data ERAT Miss (Data TLB Access) page size 4K" 115 …"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 without dispa… 120 …"BriefDescription": "Marked Data ERAT Miss (Data TLB Access) page size 16G (hpt mode) and 1G (radi… 160 …"BriefDescription": "A Page Table Entry was loaded into the TLB either shared or modified data fro… [all …]
/linux/drivers/gpu/drm/msm/
H A D	msm_iommu.c	1 // SPDX-License-Identifier: GPL-2.0-only 7 #include <linux/adreno-smmu-priv.h> 8 #include <linux/io-pgtable.h> 24 const struct iommu_flush_ops tlb; member 38 size_t size, size_t count) in calc_pgsize() argument 45 /* Page sizes supported by the hardware and small enough for @size / in calc_pgsize() 46 pgsizes = pagetable->pgsize_bitmap & GENMASK(__fls(size), 0); in calc_pgsize() 52 / Make sure we have at least one suitable page size / in calc_pgsize() 55 / Pick the biggest page size remaining / in calc_pgsize() 61 / Find the next biggest support page size, if it exists */ in calc_pgsize() [all …]
/linux/tools/testing/selftests/kvm/
H A D	access_tracking_perf_test.c	1 // SPDX-License-Identifier: GPL-2.0 22 * 1. page_idle only issues clear_young notifiers, which lack a TLB flush. This 33 * the TLB and the number of pages held in pagevecs are a small fraction of the 35 * in nesting, where TLB size is unlimited) this test will print a warning 93 #define PAGEMAP_PFN_MASK ((1ULL << 55) - 1) 129 int vcpu_idx = vcpu_args->vcpu_idx; in mark_vcpu_memory_idle() 130 uint64_t base_gva = vcpu_args->gva; in mark_vcpu_memory_idle() 131 uint64_t pages = vcpu_args->pages; in mark_vcpu_memory_idle() 170 "vCPU %d: No PFN for %" PRIu64 " out of %" PRIu64 " pages.", in mark_vcpu_memory_idle() 176 * LRU list or the translations are still cached in the TLB). 90% is in mark_vcpu_memory_idle() [all …]
/linux/drivers/firmware/efi/
H A D	cper-arm.c	1 // SPDX-License-Identifier: GPL-2.0 70 …"Local management operation (processor initiated a TLB management operation that resulted in an er… 71 …al management operation (processor raised a TLB error caused by another processor or device broadc… 146 printk("%scache level: %d\n", pfx, level); in cper_print_arm_err_info() 149 printk("%sTLB level: %d\n", pfx, level); in cper_print_arm_err_info() 152 printk("%saffinity level at which the bus error occurred: %d\n", in cper_print_arm_err_info() 245 printk("%sMIDR: 0x%016llx\n", pfx, proc->midr); in cper_print_proc_arm() 247 len = proc->section_length - (sizeof(proc) + in cper_print_proc_arm() 248 proc->err_info_num (sizeof(*err_info))); in cper_print_proc_arm() 250 printk("%ssection length: %d\n", pfx, proc->section_length); in cper_print_proc_arm() [all …]
/linux/arch/mips/mm/
H A D	tlbex.c	6 * Synthesize TLB refill handlers at runtime. 10 * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org) 34 #include <asm/cpu-type.h> 54 * TLB load/store/modify handlers. 133 * CVMSEG starts at address -32768 and extends for in scratchpad_offset() 137 return CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE * 128 - (8 * i) - 32768; in scratchpad_offset() 232 * TLB exception handlers. 243 pr_define("_PAGE_PRESENT_SHIFT %d\n", _PAGE_PRESENT_SHIFT); in output_pgtable_bits_defines() 244 pr_define("_PAGE_NO_READ_SHIFT %d\n", _PAGE_NO_READ_SHIFT); in output_pgtable_bits_defines() 245 pr_define("_PAGE_WRITE_SHIFT %d\n", _PAGE_WRITE_SHIFT); in output_pgtable_bits_defines() [all …]
/linux/arch/arm/mach-omap1/
H A D	usb.c	1 // SPDX-License-Identifier: GPL-2.0-or-later 12 #include <linux/dma-map-ops.h> 15 #include <linux/soc/ti/omap1-io.h> 24 /* These routines should handle the standard chip-specific modes 27 * Some board-.c files will need to set up additional mux options, 28 like for suspend handling, vbus sensing, GPIOs, and the D+ pullup. 32 * - 1611B H2 (with usb1 mini-AB) using standard Mini-B or OTG cables 33 * - 5912 OSK OHCI (with usb0 standard-A), standard A-to-B cables 34 * - 5912 OSK UDC, with nonstandard A-to-A cable 35 * - 1510 Innovator UDC with bundled usb0 cable [all …]
/linux/arch/arm/mm/
H A D	Kconfig	1 # SPDX-License-Identifier: GPL-2.0 17 A 32-bit RISC microprocessor based on the ARM7 processor core 36 A 32-bit RISC processor with 8kByte Cache, Write Buffer and 53 A 32-bit RISC processor with 8KB cache or 4KB variants, 69 A 32-bit RISC microprocessor based on the ARM9 processor core 147 instruction sequences for cache and TLB operations. Curiously, 166 Branch Target Buffer, Unified TLB and cache line size 16. 182 ARM940T is a member of the ARM9TDMI family of general- 184 instruction and 4KB data cases, each with a 4-word line 190 # ARM946E-S [all …]
/linux/drivers/gpu/drm/xe/
H A D	xe_gt_tlb_invalidation.c	1 // SPDX-License-Identifier: MIT 25 * TLB inval depends on pending commands in the CT queue and then the real 31 /* this reflects what HW/GuC needs to process TLB inv request / in tlb_timeout_jiffies() 35 long delay = xe_guc_ct_queue_proc_time_jiffies(&gt->uc.guc.ct); in tlb_timeout_jiffies() 42 if (WARN_ON_ONCE(!fence->gt)) in xe_gt_tlb_invalidation_fence_fini() 45 xe_pm_runtime_put(gt_to_xe(fence->gt)); in xe_gt_tlb_invalidation_fence_fini() 46 fence->gt = NULL; / fini() should be called once */ in xe_gt_tlb_invalidation_fence_fini() 52 bool stack = test_bit(FENCE_STACK_BIT, &fence->base.flags); in __invalidation_fence_signal() 56 dma_fence_signal(&fence->base); in __invalidation_fence_signal() 58 dma_fence_put(&fence->base); in __invalidation_fence_signal() [all …]
/linux/arch/sparc/include/asm/
H A D	tsb.h	1 /* SPDX-License-Identifier: GPL-2.0 / 6 power-of-2 sized table of TAG/PTE pairs. The cpu precomputes 11 * TLB miss trap handler software does the actual lookup via something 14 * ldxa [%g0] ASI_{D,I}MMU_TSB_8KB_PTR, %g1 15 * ldxa [%g0] ASI_{D,I}MMU, %g6 20 * bne,pn %xcc, tsb_miss_{d,i}tlb 21 * mov FAULT_CODE_{D,I}TLB, %g3 22 * stxa %g5, [%g0] ASI_{D,I}TLB_DATA_IN 26 * Each 16-byte slot of the TSB is the 8-byte tag and then the 8-byte 27 * PTE. The TAG is of the same layout as the TLB TAG TARGET mmu [all …]

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