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/linux/tools/perf/pmu-events/arch/powerpc/power10/
H A D	pipeline.json	5 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline suffered a TLB miss or… 10 …"BriefDescription": "Cycles in which the next-to-complete (NTC) instruction is held at dispatch fo… 35 "BriefDescription": "Cycles in which an instruction reload is pending to satisfy a demand miss." 45 …"BriefDescription": "Cycles when dispatch was stalled for this thread because the MMU was handling… 50 …"BriefDescription": "Cycles when dispatch was stalled while the instruction was fetched from the l… 55 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline was waiting for a load… 60 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline finished at dispatch a… 75 …"BriefDescription": "Cycles in which the next-to-complete (NTC) instruction is held at dispatch be… 80 …"BriefDescription": "Cycles in which the next-to-complete (NTC) instruction is held at dispatch be… 85 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline was waiting for a load… [all …]
/linux/arch/alpha/include/asm/
H A D	xor.h	`73 xor $0,$1,$0 # 7 cycles from $1 load \n\ 130 xor $0,$1,$1 # 8 cycles from $0 load \n\ 131 xor $3,$4,$4 # 6 cycles from $4 load \n\ 132 xor $6,$7,$7 # 6 cycles from $7 load \n\ 133 xor $21,$22,$22 # 5 cycles from $22 load \n\ 135 xor $1,$2,$2 # 9 cycles from $2 load \n\ 136 xor $24,$25,$25 # 5 cycles from $25 load \n\ 138 xor $4,$5,$5 # 6 cycles from $5 load \n\ 141 xor $7,$20,$20 # 7 cycles from $20 load \n\ 143 xor $22,$23,$23 # 7 cycles from $23 load \n\ [all …]`
/linux/tools/perf/pmu-events/arch/x86/jaketown/
H A D	uncore-power.json	3 "BriefDescription": "pclk Cycles", 7 …CU runs off a fixed 800 MHz clock. This event counts the number of pclk cycles measured while the… 11 "BriefDescription": "Core C State Transition Cycles", 16 …"PublicDescription": "Number of cycles spent performing core C state transitions. There is one ev… 20 "BriefDescription": "Core C State Transition Cycles", 25 …"PublicDescription": "Number of cycles spent performing core C state transitions. There is one ev… 29 "BriefDescription": "Core C State Transition Cycles", 34 …"PublicDescription": "Number of cycles spent performing core C state transitions. There is one ev… 38 "BriefDescription": "Core C State Transition Cycles", 43 …"PublicDescription": "Number of cycles spent performing core C state transitions. There is one ev… [all …]
/linux/tools/perf/pmu-events/arch/x86/haswellx/
H A D	uncore-power.json	3 "BriefDescription": "pclk Cycles", 7 …CU runs off a fixed 800 MHz clock. This event counts the number of pclk cycles measured while the… 11 "BriefDescription": "Core C State Transition Cycles", 16 …"PublicDescription": "Number of cycles spent performing core C state transitions. There is one ev… 20 "BriefDescription": "Core C State Transition Cycles", 25 …"PublicDescription": "Number of cycles spent performing core C state transitions. There is one ev… 29 "BriefDescription": "Core C State Transition Cycles", 34 …"PublicDescription": "Number of cycles spent performing core C state transitions. There is one ev… 38 "BriefDescription": "Core C State Transition Cycles", 43 …"PublicDescription": "Number of cycles spent performing core C state transitions. There is one ev… [all …]
H A D	pipeline.json	318 "BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)", 328 …"BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalte… 332 …"PublicDescription": "Reference cycles when the at least one thread on the physical core is unhalt… 345 "BriefDescription": "Reference cycles when the core is not in halt state.", 348 …"PublicDescription": "This event counts the number of reference cycles when the core is not in a h… 353 "BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)", 357 … "PublicDescription": "Reference cycles when the thread is unhalted. (counts at 100 MHz rate)", 363 …"BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalte… 367 …"PublicDescription": "Reference cycles when the at least one thread on the physical core is unhalt… 372 "BriefDescription": "Core cycles when the thread is not in halt state.", [all …]
/linux/tools/perf/pmu-events/arch/x86/sapphirerapids/
H A D	uncore-power.json	8 "PublicDescription": "Number of PCU PCLK Clock cycles while the event is enabled", 30 "BriefDescription": "Phase Shed 0 Cycles", 36 "PublicDescription": "Phase Shed 0 Cycles : Cycles spent in phase-shedding power state 0", 40 "BriefDescription": "Phase Shed 1 Cycles", 46 "PublicDescription": "Phase Shed 1 Cycles : Cycles spent in phase-shedding power state 1", 50 "BriefDescription": "Phase Shed 2 Cycles", 56 "PublicDescription": "Phase Shed 2 Cycles : Cycles spent in phase-shedding power state 2", 60 "BriefDescription": "Phase Shed 3 Cycles", 66 "PublicDescription": "Phase Shed 3 Cycles : Cycles spent in phase-shedding power state 3", 88 "BriefDescription": "Thermal Strongest Upper Limit Cycles", [all …]
/linux/tools/perf/pmu-events/arch/x86/emeraldrapids/
H A D	uncore-power.json	8 "PublicDescription": "Number of PCU PCLK Clock cycles while the event is enabled", 30 "BriefDescription": "Phase Shed 0 Cycles", 36 "PublicDescription": "Phase Shed 0 Cycles : Cycles spent in phase-shedding power state 0", 40 "BriefDescription": "Phase Shed 1 Cycles", 46 "PublicDescription": "Phase Shed 1 Cycles : Cycles spent in phase-shedding power state 1", 50 "BriefDescription": "Phase Shed 2 Cycles", 56 "PublicDescription": "Phase Shed 2 Cycles : Cycles spent in phase-shedding power state 2", 60 "BriefDescription": "Phase Shed 3 Cycles", 66 "PublicDescription": "Phase Shed 3 Cycles : Cycles spent in phase-shedding power state 3", 88 "BriefDescription": "Thermal Strongest Upper Limit Cycles", [all …]
/linux/tools/perf/pmu-events/arch/x86/broadwellx/
H A D	uncore-power.json	3 "BriefDescription": "pclk Cycles", 7 … PCU runs off a fixed 1 GHz clock. This event counts the number of pclk cycles measured while the… 11 "BriefDescription": "Core C State Transition Cycles", 16 …"PublicDescription": "Number of cycles spent performing core C state transitions. There is one ev… 20 "BriefDescription": "Core C State Transition Cycles", 25 …"PublicDescription": "Number of cycles spent performing core C state transitions. There is one ev… 29 "BriefDescription": "Core C State Transition Cycles", 34 …"PublicDescription": "Number of cycles spent performing core C state transitions. There is one ev… 38 "BriefDescription": "Core C State Transition Cycles", 43 …"PublicDescription": "Number of cycles spent performing core C state transitions. There is one ev… [all …]
H A D	pipeline.json	3 "BriefDescription": "Cycles when divider is busy executing divide operations", 353 "BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)", 363 "BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate).", 379 "BriefDescription": "Reference cycles when the core is not in halt state.", 382 "PublicDescription": "This event counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. This event has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK event. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. Note: On all current platforms this event stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'. This event is clocked by base clock (100 Mhz) on Sandy Bridge. The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'. After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this case.", 387 "BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)", 391 "PublicDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate).", 397 "BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate).", 405 "BriefDescription": "Core cycles when the thread is not in halt state", 408 "PublicDescription": "This event counts the number of core cycles whil [all...]
/linux/tools/perf/pmu-events/arch/x86/broadwellde/
H A D	uncore-power.json	3 "BriefDescription": "pclk Cycles", 7 … PCU runs off a fixed 1 GHz clock. This event counts the number of pclk cycles measured while the… 11 "BriefDescription": "Core C State Transition Cycles", 16 …"PublicDescription": "Number of cycles spent performing core C state transitions. There is one ev… 20 "BriefDescription": "Core C State Transition Cycles", 25 …"PublicDescription": "Number of cycles spent performing core C state transitions. There is one ev… 29 "BriefDescription": "Core C State Transition Cycles", 34 …"PublicDescription": "Number of cycles spent performing core C state transitions. There is one ev… 38 "BriefDescription": "Core C State Transition Cycles", 43 …"PublicDescription": "Number of cycles spent performing core C state transitions. There is one ev… [all …]
H A D	pipeline.json	3 "BriefDescription": "Cycles when divider is busy executing divide operations", 353 "BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)", 363 "BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate).", 379 "BriefDescription": "Reference cycles when the core is not in halt state.", 382 "PublicDescription": "This event counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. This event has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK event. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. Note: On all current platforms this event stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'. This event is clocked by base clock (100 Mhz) on Sandy Bridge. The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'. After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this case.", 387 "BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)", 391 "PublicDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate).", 397 "BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate).", 405 "BriefDescription": "Core cycles when the thread is not in halt state", 408 "PublicDescription": "This event counts the number of core cycles whil [all...]
/linux/tools/perf/pmu-events/arch/x86/snowridgex/
H A D	uncore-power.json	28 "BriefDescription": "Phase Shed 0 Cycles", 34 "PublicDescription": "Phase Shed 0 Cycles : Cycles spent in phase-shedding power state 0", 38 "BriefDescription": "Phase Shed 1 Cycles", 44 "PublicDescription": "Phase Shed 1 Cycles : Cycles spent in phase-shedding power state 1", 48 "BriefDescription": "Phase Shed 2 Cycles", 54 "PublicDescription": "Phase Shed 2 Cycles : Cycles spent in phase-shedding power state 2", 58 "BriefDescription": "Phase Shed 3 Cycles", 64 "PublicDescription": "Phase Shed 3 Cycles : Cycles spent in phase-shedding power state 3", 86 "BriefDescription": "Thermal Strongest Upper Limit Cycles", 92 …"PublicDescription": "Thermal Strongest Upper Limit Cycles : Number of cycles any frequency is red… [all …]
/linux/tools/perf/pmu-events/arch/x86/knightslanding/
H A D	uncore-io.json	3 …"BriefDescription": "Egress (to CMS) Cycles Full. Counts the number of cycles when the M2PCIe Egre… 12 …"BriefDescription": "Egress (to CMS) Cycles Full. Counts the number of cycles when the M2PCIe Egre… 21 …"BriefDescription": "Egress (to CMS) Cycles Full. Counts the number of cycles when the M2PCIe Egre… 30 …"BriefDescription": "Egress (to CMS) Cycles Full. Counts the number of cycles when the M2PCIe Egre… 39 …"BriefDescription": "Egress (to CMS) Cycles Full. Counts the number of cycles when the M2PCIe Egre… 48 …"BriefDescription": "Egress (to CMS) Cycles Full. Counts the number of cycles when the M2PCIe Egre… 57 …"BriefDescription": "Egress (to CMS) Cycles Not Empty. Counts the number of cycles when the M2PCIe… 66 …"BriefDescription": "Egress (to CMS) Cycles Not Empty. Counts the number of cycles when the M2PCIe… 75 …"BriefDescription": "Egress (to CMS) Cycles Not Empty. Counts the number of cycles when the M2PCIe… 84 …"BriefDescription": "Egress (to CMS) Cycles Not Empty. Counts the number of cycles when the M2PCIe… [all …]
/linux/tools/perf/pmu-events/arch/x86/icelakex/
H A D	uncore-power.json	7 … PCU runs off a fixed 1 GHz clock. This event counts the number of pclk cycles measured while the… 29 "BriefDescription": "Phase Shed 0 Cycles", 35 "PublicDescription": "Phase Shed 0 Cycles : Cycles spent in phase-shedding power state 0", 39 "BriefDescription": "Phase Shed 1 Cycles", 45 "PublicDescription": "Phase Shed 1 Cycles : Cycles spent in phase-shedding power state 1", 49 "BriefDescription": "Phase Shed 2 Cycles", 55 "PublicDescription": "Phase Shed 2 Cycles : Cycles spent in phase-shedding power state 2", 59 "BriefDescription": "Phase Shed 3 Cycles", 65 "PublicDescription": "Phase Shed 3 Cycles : Cycles spent in phase-shedding power state 3", 87 "BriefDescription": "Thermal Strongest Upper Limit Cycles", [all …]
/linux/tools/perf/pmu-events/arch/x86/ivytown/
H A D	uncore-power.json	3 "BriefDescription": "pclk Cycles", 7 …CU runs off a fixed 800 MHz clock. This event counts the number of pclk cycles measured while the… 11 "BriefDescription": "Core 0 C State Transition Cycles", 16 …"PublicDescription": "Number of cycles spent performing core C state transitions. There is one ev… 20 "BriefDescription": "Core 10 C State Transition Cycles", 25 …"PublicDescription": "Number of cycles spent performing core C state transitions. There is one ev… 29 "BriefDescription": "Core 11 C State Transition Cycles", 34 …"PublicDescription": "Number of cycles spent performing core C state transitions. There is one ev… 38 "BriefDescription": "Core 12 C State Transition Cycles", 43 …"PublicDescription": "Number of cycles spent performing core C state transitions. There is one ev… [all …]
H A D	pipeline.json	14 "BriefDescription": "Cycles when divider is busy executing divide operations", 18 …"PublicDescription": "Cycles that the divider is active, includes INT and FP. Set 'edge =1, cmask=… 343 "BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)", 353 …"BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalte… 369 "BriefDescription": "Reference cycles when the core is not in halt state.", 376 "BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)", 380 … "PublicDescription": "Reference cycles when the thread is unhalted. (counts at 100 MHz rate)", 386 …"BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalte… 394 "BriefDescription": "Core cycles when the thread is not in halt state.", 402 …"BriefDescription": "Core cycles when at least one thread on the physical core is not in halt stat… [all …]
H A D	frontend.json	21 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles", 25 "PublicDescription": "Cycles DSB to MITE switches caused delay.", 30 …"BriefDescription": "Cycles when Decode Stream Buffer (DSB) fill encounter more than 3 Decode Stre… 48 …"BriefDescription": "Cycles where a code-fetch stalled due to L1 instruction-cache miss or an iTLB… 52 …"PublicDescription": "Cycles where a code-fetch stalled due to L1 instruction-cache miss or an iTL… 66 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops", 71 "PublicDescription": "Counts cycles DSB is delivered four uops. Set Cmask = 4.", 76 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop", 81 "PublicDescription": "Counts cycles DSB is delivered at least one uops. Set Cmask = 1.", 86 "BriefDescription": "Cycles MITE is delivering 4 Uops", [all …]
/linux/tools/perf/pmu-events/arch/x86/amdzen3/
H A D	other.json	5 "BriefDescription": "Cycles where the Micro-Op Queue is empty." 22 …"BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a T… 28 …"BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a T… 34 …"BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a T… 40 …"BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a T… 46 …"BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a t… 52 …"BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a T… 58 …"BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a T… 64 …"BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a T… 70 …"BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a t… [all …]
/linux/tools/perf/pmu-events/arch/x86/ivybridge/
H A D	pipeline.json	14 "BriefDescription": "Cycles when divider is busy executing divide operations", 18 …"PublicDescription": "Cycles that the divider is active, includes INT and FP. Set 'edge =1, cmask=… 343 "BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)", 353 …"BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalte… 369 "BriefDescription": "Reference cycles when the core is not in halt state.", 376 "BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)", 380 … "PublicDescription": "Reference cycles when the thread is unhalted. (counts at 100 MHz rate)", 386 …"BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalte… 394 "BriefDescription": "Core cycles when the thread is not in halt state.", 402 …"BriefDescription": "Core cycles when at least one thread on the physical core is not in halt stat… [all …]
H A D	frontend.json	21 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles", 25 "PublicDescription": "Cycles DSB to MITE switches caused delay.", 30 …"BriefDescription": "Cycles when Decode Stream Buffer (DSB) fill encounter more than 3 Decode Stre… 48 …"BriefDescription": "Cycles where a code-fetch stalled due to L1 instruction-cache miss or an iTLB… 52 …"PublicDescription": "Cycles where a code-fetch stalled due to L1 instruction-cache miss or an iTL… 66 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops", 71 "PublicDescription": "Counts cycles DSB is delivered four uops. Set Cmask = 4.", 76 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop", 81 "PublicDescription": "Counts cycles DSB is delivered at least one uops. Set Cmask = 1.", 86 "BriefDescription": "Cycles MITE is delivering 4 Uops", [all …]
/linux/tools/perf/pmu-events/arch/x86/haswell/
H A D	pipeline.json	318 "BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)", 328 …"BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalte… 332 …"PublicDescription": "Reference cycles when the at least one thread on the physical core is unhalt… 345 "BriefDescription": "Reference cycles when the core is not in halt state.", 348 …"PublicDescription": "This event counts the number of reference cycles when the core is not in a h… 353 "BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)", 357 … "PublicDescription": "Reference cycles when the thread is unhalted. (counts at 100 MHz rate)", 363 …"BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalte… 367 …"PublicDescription": "Reference cycles when the at least one thread on the physical core is unhalt… 372 "BriefDescription": "Core cycles when the thread is not in halt state.", [all …]
/linux/tools/perf/pmu-events/arch/x86/skylake/
H A D	pipeline.json	3 …"BriefDescription": "Cycles when divide unit is busy executing divide or square root operations. A… 182 …"BriefDescription": "Core crystal clock cycles when this thread is unhalted and the other thread i… 190 "BriefDescription": "Core crystal clock cycles when the thread is unhalted.", 199 …"BriefDescription": "Core crystal clock cycles when at least one thread on the physical core is un… 207 …"BriefDescription": "Core crystal clock cycles when this thread is unhalted and the other thread i… 215 "BriefDescription": "Reference cycles when the core is not in halt state.", 218 …"PublicDescription": "Counts the number of reference cycles when the core is not in a halt state. … 223 "BriefDescription": "Core crystal clock cycles when the thread is unhalted.", 232 …"BriefDescription": "Core crystal clock cycles when at least one thread on the physical core is un… 250 "BriefDescription": "Core cycles when the thread is not in halt state", [all …]
/linux/tools/perf/pmu-events/arch/x86/cascadelakex/
H A D	pipeline.json	3 …"BriefDescription": "Cycles when divide unit is busy executing divide or square root operations. A… 192 …"BriefDescription": "Core crystal clock cycles when this thread is unhalted and the other thread i… 200 "BriefDescription": "Core crystal clock cycles when the thread is unhalted.", 209 …"BriefDescription": "Core crystal clock cycles when at least one thread on the physical core is un… 217 …"BriefDescription": "Core crystal clock cycles when this thread is unhalted and the other thread i… 225 "BriefDescription": "Reference cycles when the core is not in halt state.", 228 …"PublicDescription": "Counts the number of reference cycles when the core is not in a halt state. … 233 "BriefDescription": "Core crystal clock cycles when the thread is unhalted.", 242 …"BriefDescription": "Core crystal clock cycles when at least one thread on the physical core is un… 260 "BriefDescription": "Core cycles when the thread is not in halt state", [all …]
/linux/tools/perf/pmu-events/arch/x86/skylakex/
H A D	pipeline.json	3 …"BriefDescription": "Cycles when divide unit is busy executing divide or square root operations. A… 192 …"BriefDescription": "Core crystal clock cycles when this thread is unhalted and the other thread i… 200 "BriefDescription": "Core crystal clock cycles when the thread is unhalted.", 209 …"BriefDescription": "Core crystal clock cycles when at least one thread on the physical core is un… 217 …"BriefDescription": "Core crystal clock cycles when this thread is unhalted and the other thread i… 225 "BriefDescription": "Reference cycles when the core is not in halt state.", 228 …"PublicDescription": "Counts the number of reference cycles when the core is not in a halt state. … 233 "BriefDescription": "Core crystal clock cycles when the thread is unhalted.", 242 …"BriefDescription": "Core crystal clock cycles when at least one thread on the physical core is un… 260 "BriefDescription": "Core cycles when the thread is not in halt state", [all …]
/linux/tools/perf/pmu-events/arch/x86/broadwell/
H A D	pipeline.json	3 "BriefDescription": "Cycles when divider is busy executing divide operations", 353 "BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)", 363 "BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate).", 379 "BriefDescription": "Reference cycles when the core is not in halt state.", 382 "PublicDescription": "This event counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. This event has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK event. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. Note: On all current platforms this event stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'. This event is clocked by base clock (100 Mhz) on Sandy Bridge. The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'. After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this case.", 387 "BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)", 391 "PublicDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate).", 397 "BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate).", 405 "BriefDescription": "Core cycles when the thread is not in halt state", 408 "PublicDescription": "This event counts the number of core cycles whil [all...]

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