1[ 2 { 3 "BriefDescription": "PCU PCLK Clockticks", 4 "Counter": "0,1,2,3", 5 "EventCode": "0x01", 6 "EventName": "UNC_P_CLOCKTICKS", 7 "PerPkg": "1", 8 "PublicDescription": "Number of PCU PCLK Clock cycles while the event is enabled", 9 "Unit": "PCU" 10 }, 11 { 12 "BriefDescription": "UNC_P_CORE_TRANSITION_CYCLES", 13 "Counter": "0,1,2,3", 14 "EventCode": "0x60", 15 "EventName": "UNC_P_CORE_TRANSITION_CYCLES", 16 "Experimental": "1", 17 "PerPkg": "1", 18 "Unit": "PCU" 19 }, 20 { 21 "BriefDescription": "UNC_P_DEMOTIONS", 22 "Counter": "0,1,2,3", 23 "EventCode": "0x30", 24 "EventName": "UNC_P_DEMOTIONS", 25 "Experimental": "1", 26 "PerPkg": "1", 27 "Unit": "PCU" 28 }, 29 { 30 "BriefDescription": "Phase Shed 0 Cycles", 31 "Counter": "0,1,2,3", 32 "EventCode": "0x75", 33 "EventName": "UNC_P_FIVR_PS_PS0_CYCLES", 34 "Experimental": "1", 35 "PerPkg": "1", 36 "PublicDescription": "Phase Shed 0 Cycles : Cycles spent in phase-shedding power state 0", 37 "Unit": "PCU" 38 }, 39 { 40 "BriefDescription": "Phase Shed 1 Cycles", 41 "Counter": "0,1,2,3", 42 "EventCode": "0x76", 43 "EventName": "UNC_P_FIVR_PS_PS1_CYCLES", 44 "Experimental": "1", 45 "PerPkg": "1", 46 "PublicDescription": "Phase Shed 1 Cycles : Cycles spent in phase-shedding power state 1", 47 "Unit": "PCU" 48 }, 49 { 50 "BriefDescription": "Phase Shed 2 Cycles", 51 "Counter": "0,1,2,3", 52 "EventCode": "0x77", 53 "EventName": "UNC_P_FIVR_PS_PS2_CYCLES", 54 "Experimental": "1", 55 "PerPkg": "1", 56 "PublicDescription": "Phase Shed 2 Cycles : Cycles spent in phase-shedding power state 2", 57 "Unit": "PCU" 58 }, 59 { 60 "BriefDescription": "Phase Shed 3 Cycles", 61 "Counter": "0,1,2,3", 62 "EventCode": "0x78", 63 "EventName": "UNC_P_FIVR_PS_PS3_CYCLES", 64 "Experimental": "1", 65 "PerPkg": "1", 66 "PublicDescription": "Phase Shed 3 Cycles : Cycles spent in phase-shedding power state 3", 67 "Unit": "PCU" 68 }, 69 { 70 "BriefDescription": "AVX256 Frequency Clipping", 71 "Counter": "0,1,2,3", 72 "EventCode": "0x49", 73 "EventName": "UNC_P_FREQ_CLIP_AVX256", 74 "Experimental": "1", 75 "PerPkg": "1", 76 "Unit": "PCU" 77 }, 78 { 79 "BriefDescription": "AVX512 Frequency Clipping", 80 "Counter": "0,1,2,3", 81 "EventCode": "0x4a", 82 "EventName": "UNC_P_FREQ_CLIP_AVX512", 83 "Experimental": "1", 84 "PerPkg": "1", 85 "Unit": "PCU" 86 }, 87 { 88 "BriefDescription": "Thermal Strongest Upper Limit Cycles", 89 "Counter": "0,1,2,3", 90 "EventCode": "0x04", 91 "EventName": "UNC_P_FREQ_MAX_LIMIT_THERMAL_CYCLES", 92 "Experimental": "1", 93 "PerPkg": "1", 94 "PublicDescription": "Thermal Strongest Upper Limit Cycles : Number of cycles any frequency is reduced due to a thermal limit. Count only if throttling is occurring.", 95 "Unit": "PCU" 96 }, 97 { 98 "BriefDescription": "Power Strongest Upper Limit Cycles", 99 "Counter": "0,1,2,3", 100 "EventCode": "0x05", 101 "EventName": "UNC_P_FREQ_MAX_POWER_CYCLES", 102 "Experimental": "1", 103 "PerPkg": "1", 104 "PublicDescription": "Power Strongest Upper Limit Cycles : Counts the number of cycles when power is the upper limit on frequency.", 105 "Unit": "PCU" 106 }, 107 { 108 "BriefDescription": "IO P Limit Strongest Lower Limit Cycles", 109 "Counter": "0,1,2,3", 110 "EventCode": "0x73", 111 "EventName": "UNC_P_FREQ_MIN_IO_P_CYCLES", 112 "Experimental": "1", 113 "PerPkg": "1", 114 "PublicDescription": "IO P Limit Strongest Lower Limit Cycles : Counts the number of cycles when IO P Limit is preventing us from dropping the frequency lower. This algorithm monitors the needs to the IO subsystem on both local and remote sockets and will maintain a frequency high enough to maintain good IO BW. This is necessary for when all the IA cores on a socket are idle but a user still would like to maintain high IO Bandwidth.", 115 "Unit": "PCU" 116 }, 117 { 118 "BriefDescription": "Cycles spent changing Frequency", 119 "Counter": "0,1,2,3", 120 "EventCode": "0x74", 121 "EventName": "UNC_P_FREQ_TRANS_CYCLES", 122 "Experimental": "1", 123 "PerPkg": "1", 124 "PublicDescription": "Cycles spent changing Frequency : Counts the number of cycles when the system is changing frequency. This can not be filtered by thread ID. One can also use it with the occupancy counter that monitors number of threads in C0 to estimate the performance impact that frequency transitions had on the system.", 125 "Unit": "PCU" 126 }, 127 { 128 "BriefDescription": "Memory Phase Shedding Cycles", 129 "Counter": "0,1,2,3", 130 "EventCode": "0x2f", 131 "EventName": "UNC_P_MEMORY_PHASE_SHEDDING_CYCLES", 132 "Experimental": "1", 133 "PerPkg": "1", 134 "PublicDescription": "Memory Phase Shedding Cycles : Counts the number of cycles that the PCU has triggered memory phase shedding. This is a mode that can be run in the iMC physicals that saves power at the expense of additional latency.", 135 "Unit": "PCU" 136 }, 137 { 138 "BriefDescription": "Package C State Residency - C0", 139 "Counter": "0,1,2,3", 140 "EventCode": "0x2a", 141 "EventName": "UNC_P_PKG_RESIDENCY_C0_CYCLES", 142 "Experimental": "1", 143 "PerPkg": "1", 144 "PublicDescription": "Package C State Residency - C0 : Counts the number of cycles when the package was in C0. This event can be used in conjunction with edge detect to count C0 entrances (or exits using invert). Residency events do not include transition times.", 145 "Unit": "PCU" 146 }, 147 { 148 "BriefDescription": "Package C State Residency - C2E", 149 "Counter": "0,1,2,3", 150 "EventCode": "0x2b", 151 "EventName": "UNC_P_PKG_RESIDENCY_C2E_CYCLES", 152 "Experimental": "1", 153 "PerPkg": "1", 154 "PublicDescription": "Package C State Residency - C2E : Counts the number of cycles when the package was in C2E. This event can be used in conjunction with edge detect to count C2E entrances (or exits using invert). Residency events do not include transition times.", 155 "Unit": "PCU" 156 }, 157 { 158 "BriefDescription": "Package C State Residency - C6", 159 "Counter": "0,1,2,3", 160 "EventCode": "0x2d", 161 "EventName": "UNC_P_PKG_RESIDENCY_C6_CYCLES", 162 "Experimental": "1", 163 "PerPkg": "1", 164 "PublicDescription": "Package C State Residency - C6 : Counts the number of cycles when the package was in C6. This event can be used in conjunction with edge detect to count C6 entrances (or exits using invert). Residency events do not include transition times.", 165 "Unit": "PCU" 166 }, 167 { 168 "BriefDescription": "UNC_P_PMAX_THROTTLED_CYCLES", 169 "Counter": "0", 170 "EventCode": "0x06", 171 "EventName": "UNC_P_PMAX_THROTTLED_CYCLES", 172 "Experimental": "1", 173 "PerPkg": "1", 174 "Unit": "PCU" 175 }, 176 { 177 "BriefDescription": "Number of cores in C0", 178 "Counter": "0,1,2,3", 179 "EventCode": "0x35", 180 "EventName": "UNC_P_POWER_STATE_OCCUPANCY_CORES_C0", 181 "Experimental": "1", 182 "PerPkg": "1", 183 "PublicDescription": "Number of cores in C0 : This is an occupancy event that tracks the number of cores that are in the chosen C-State. It can be used by itself to get the average number of cores in that C-state with thresholding to generate histograms, or with other PCU events and occupancy triggering to capture other details.", 184 "Unit": "PCU" 185 }, 186 { 187 "BriefDescription": "Number of cores in C3", 188 "Counter": "0,1,2,3", 189 "EventCode": "0x36", 190 "EventName": "UNC_P_POWER_STATE_OCCUPANCY_CORES_C3", 191 "Experimental": "1", 192 "PerPkg": "1", 193 "PublicDescription": "Number of cores in C3 : This is an occupancy event that tracks the number of cores that are in the chosen C-State. It can be used by itself to get the average number of cores in that C-state with thresholding to generate histograms, or with other PCU events and occupancy triggering to capture other details.", 194 "Unit": "PCU" 195 }, 196 { 197 "BriefDescription": "Number of cores in C6", 198 "Counter": "0,1,2,3", 199 "EventCode": "0x37", 200 "EventName": "UNC_P_POWER_STATE_OCCUPANCY_CORES_C6", 201 "Experimental": "1", 202 "PerPkg": "1", 203 "PublicDescription": "Number of cores in C6 : This is an occupancy event that tracks the number of cores that are in the chosen C-State. It can be used by itself to get the average number of cores in that C-state with thresholding to generate histograms, or with other PCU events and occupancy triggering to capture other details.", 204 "Unit": "PCU" 205 }, 206 { 207 "BriefDescription": "External Prochot", 208 "Counter": "0,1,2,3", 209 "EventCode": "0x0a", 210 "EventName": "UNC_P_PROCHOT_EXTERNAL_CYCLES", 211 "Experimental": "1", 212 "PerPkg": "1", 213 "PublicDescription": "External Prochot : Counts the number of cycles that we are in external PROCHOT mode. This mode is triggered when a sensor off the die determines that something off-die (like DRAM) is too hot and must throttle to avoid damaging the chip.", 214 "Unit": "PCU" 215 }, 216 { 217 "BriefDescription": "Internal Prochot", 218 "Counter": "0,1,2,3", 219 "EventCode": "0x09", 220 "EventName": "UNC_P_PROCHOT_INTERNAL_CYCLES", 221 "Experimental": "1", 222 "PerPkg": "1", 223 "PublicDescription": "Internal Prochot : Counts the number of cycles that we are in Internal PROCHOT mode. This mode is triggered when a sensor on the die determines that we are too hot and must throttle to avoid damaging the chip.", 224 "Unit": "PCU" 225 }, 226 { 227 "BriefDescription": "Total Core C State Transition Cycles", 228 "Counter": "0,1,2,3", 229 "EventCode": "0x72", 230 "EventName": "UNC_P_TOTAL_TRANSITION_CYCLES", 231 "Experimental": "1", 232 "PerPkg": "1", 233 "PublicDescription": "Total Core C State Transition Cycles : Number of cycles spent performing core C state transitions across all cores.", 234 "Unit": "PCU" 235 }, 236 { 237 "BriefDescription": "VR Hot", 238 "Counter": "0,1,2,3", 239 "EventCode": "0x42", 240 "EventName": "UNC_P_VR_HOT_CYCLES", 241 "Experimental": "1", 242 "PerPkg": "1", 243 "PublicDescription": "VR Hot : Number of cycles that a CPU SVID VR is hot. Does not cover DRAM VRs", 244 "Unit": "PCU" 245 } 246] 247