1d910f0baSAndi Kleen[ 2d910f0baSAndi Kleen { 370d90a6aSIan Rogers "BriefDescription": "Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.", 4*3235704cSIan Rogers "Counter": "0,1,2,3", 570d90a6aSIan Rogers "EventCode": "0xE6", 670d90a6aSIan Rogers "EventName": "BACLEARS.ANY", 770d90a6aSIan Rogers "PublicDescription": "Number of front end re-steers due to BPU misprediction.", 870d90a6aSIan Rogers "SampleAfterValue": "100003", 970d90a6aSIan Rogers "UMask": "0x1f" 10d910f0baSAndi Kleen }, 11d910f0baSAndi Kleen { 1270d90a6aSIan Rogers "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches", 13*3235704cSIan Rogers "Counter": "0,1,2,3", 1470d90a6aSIan Rogers "EventCode": "0xAB", 1570d90a6aSIan Rogers "EventName": "DSB2MITE_SWITCHES.COUNT", 1670d90a6aSIan Rogers "PublicDescription": "Number of DSB to MITE switches.", 17d910f0baSAndi Kleen "SampleAfterValue": "2000003", 1870d90a6aSIan Rogers "UMask": "0x1" 19d910f0baSAndi Kleen }, 20d910f0baSAndi Kleen { 2170d90a6aSIan Rogers "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles", 22*3235704cSIan Rogers "Counter": "0,1,2,3", 2370d90a6aSIan Rogers "EventCode": "0xAB", 2470d90a6aSIan Rogers "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES", 2570d90a6aSIan Rogers "PublicDescription": "Cycles DSB to MITE switches caused delay.", 26d910f0baSAndi Kleen "SampleAfterValue": "2000003", 2770d90a6aSIan Rogers "UMask": "0x2" 28d910f0baSAndi Kleen }, 29d910f0baSAndi Kleen { 3070d90a6aSIan Rogers "BriefDescription": "Cycles when Decode Stream Buffer (DSB) fill encounter more than 3 Decode Stream Buffer (DSB) lines", 31*3235704cSIan Rogers "Counter": "0,1,2,3", 3270d90a6aSIan Rogers "EventCode": "0xAC", 3370d90a6aSIan Rogers "EventName": "DSB_FILL.EXCEED_DSB_LINES", 3470d90a6aSIan Rogers "PublicDescription": "DSB Fill encountered > 3 DSB lines.", 35194b6fa4SAndi Kleen "SampleAfterValue": "2000003", 3670d90a6aSIan Rogers "UMask": "0x8" 37194b6fa4SAndi Kleen }, 38194b6fa4SAndi Kleen { 39d910f0baSAndi Kleen "BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches", 40*3235704cSIan Rogers "Counter": "0,1,2,3", 41d910f0baSAndi Kleen "EventCode": "0x80", 4270d90a6aSIan Rogers "EventName": "ICACHE.HIT", 4370d90a6aSIan Rogers "PublicDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches.", 44d910f0baSAndi Kleen "SampleAfterValue": "2000003", 4570d90a6aSIan Rogers "UMask": "0x1" 4670d90a6aSIan Rogers }, 4770d90a6aSIan Rogers { 48d910f0baSAndi Kleen "BriefDescription": "Cycles where a code-fetch stalled due to L1 instruction-cache miss or an iTLB miss", 49*3235704cSIan Rogers "Counter": "0,1,2,3", 5070d90a6aSIan Rogers "EventCode": "0x80", 5170d90a6aSIan Rogers "EventName": "ICACHE.IFETCH_STALL", 5270d90a6aSIan Rogers "PublicDescription": "Cycles where a code-fetch stalled due to L1 instruction-cache miss or an iTLB miss.", 53d910f0baSAndi Kleen "SampleAfterValue": "2000003", 5470d90a6aSIan Rogers "UMask": "0x4" 55d910f0baSAndi Kleen }, 56d910f0baSAndi Kleen { 5770d90a6aSIan Rogers "BriefDescription": "Instruction cache, streaming buffer and victim cache misses", 58*3235704cSIan Rogers "Counter": "0,1,2,3", 5970d90a6aSIan Rogers "EventCode": "0x80", 6070d90a6aSIan Rogers "EventName": "ICACHE.MISSES", 6170d90a6aSIan Rogers "PublicDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Misses. Includes UC accesses.", 6270d90a6aSIan Rogers "SampleAfterValue": "200003", 6370d90a6aSIan Rogers "UMask": "0x2" 6470d90a6aSIan Rogers }, 6570d90a6aSIan Rogers { 6670d90a6aSIan Rogers "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops", 67*3235704cSIan Rogers "Counter": "0,1,2,3", 6870d90a6aSIan Rogers "CounterMask": "4", 6970d90a6aSIan Rogers "EventCode": "0x79", 7070d90a6aSIan Rogers "EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS", 7170d90a6aSIan Rogers "PublicDescription": "Counts cycles DSB is delivered four uops. Set Cmask = 4.", 7270d90a6aSIan Rogers "SampleAfterValue": "2000003", 7370d90a6aSIan Rogers "UMask": "0x18" 7470d90a6aSIan Rogers }, 7570d90a6aSIan Rogers { 7670d90a6aSIan Rogers "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop", 77*3235704cSIan Rogers "Counter": "0,1,2,3", 7870d90a6aSIan Rogers "CounterMask": "1", 7970d90a6aSIan Rogers "EventCode": "0x79", 8070d90a6aSIan Rogers "EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS", 8170d90a6aSIan Rogers "PublicDescription": "Counts cycles DSB is delivered at least one uops. Set Cmask = 1.", 8270d90a6aSIan Rogers "SampleAfterValue": "2000003", 8370d90a6aSIan Rogers "UMask": "0x18" 8470d90a6aSIan Rogers }, 8570d90a6aSIan Rogers { 8670d90a6aSIan Rogers "BriefDescription": "Cycles MITE is delivering 4 Uops", 87*3235704cSIan Rogers "Counter": "0,1,2,3", 8870d90a6aSIan Rogers "CounterMask": "4", 8970d90a6aSIan Rogers "EventCode": "0x79", 9070d90a6aSIan Rogers "EventName": "IDQ.ALL_MITE_CYCLES_4_UOPS", 9170d90a6aSIan Rogers "PublicDescription": "Counts cycles MITE is delivered four uops. Set Cmask = 4.", 9270d90a6aSIan Rogers "SampleAfterValue": "2000003", 9370d90a6aSIan Rogers "UMask": "0x24" 9470d90a6aSIan Rogers }, 9570d90a6aSIan Rogers { 9670d90a6aSIan Rogers "BriefDescription": "Cycles MITE is delivering any Uop", 97*3235704cSIan Rogers "Counter": "0,1,2,3", 9870d90a6aSIan Rogers "CounterMask": "1", 9970d90a6aSIan Rogers "EventCode": "0x79", 10070d90a6aSIan Rogers "EventName": "IDQ.ALL_MITE_CYCLES_ANY_UOPS", 10170d90a6aSIan Rogers "PublicDescription": "Counts cycles MITE is delivered at least one uops. Set Cmask = 1.", 10270d90a6aSIan Rogers "SampleAfterValue": "2000003", 10370d90a6aSIan Rogers "UMask": "0x24" 10470d90a6aSIan Rogers }, 10570d90a6aSIan Rogers { 10670d90a6aSIan Rogers "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path", 107*3235704cSIan Rogers "Counter": "0,1,2,3", 10870d90a6aSIan Rogers "CounterMask": "1", 10970d90a6aSIan Rogers "EventCode": "0x79", 11070d90a6aSIan Rogers "EventName": "IDQ.DSB_CYCLES", 11170d90a6aSIan Rogers "PublicDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path.", 11270d90a6aSIan Rogers "SampleAfterValue": "2000003", 11370d90a6aSIan Rogers "UMask": "0x8" 11470d90a6aSIan Rogers }, 11570d90a6aSIan Rogers { 11670d90a6aSIan Rogers "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path", 117*3235704cSIan Rogers "Counter": "0,1,2,3", 11870d90a6aSIan Rogers "EventCode": "0x79", 11970d90a6aSIan Rogers "EventName": "IDQ.DSB_UOPS", 12070d90a6aSIan Rogers "PublicDescription": "Increment each cycle. # of uops delivered to IDQ from DSB path. Set Cmask = 1 to count cycles.", 12170d90a6aSIan Rogers "SampleAfterValue": "2000003", 12270d90a6aSIan Rogers "UMask": "0x8" 12370d90a6aSIan Rogers }, 12470d90a6aSIan Rogers { 12570d90a6aSIan Rogers "BriefDescription": "Instruction Decode Queue (IDQ) empty cycles", 126*3235704cSIan Rogers "Counter": "0,1,2,3", 12770d90a6aSIan Rogers "EventCode": "0x79", 12870d90a6aSIan Rogers "EventName": "IDQ.EMPTY", 12970d90a6aSIan Rogers "PublicDescription": "Counts cycles the IDQ is empty.", 13070d90a6aSIan Rogers "SampleAfterValue": "2000003", 13170d90a6aSIan Rogers "UMask": "0x2" 13270d90a6aSIan Rogers }, 13370d90a6aSIan Rogers { 13470d90a6aSIan Rogers "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path", 135*3235704cSIan Rogers "Counter": "0,1,2,3", 13670d90a6aSIan Rogers "EventCode": "0x79", 13770d90a6aSIan Rogers "EventName": "IDQ.MITE_ALL_UOPS", 13870d90a6aSIan Rogers "PublicDescription": "Number of uops delivered to IDQ from any path.", 13970d90a6aSIan Rogers "SampleAfterValue": "2000003", 14070d90a6aSIan Rogers "UMask": "0x3c" 14170d90a6aSIan Rogers }, 14270d90a6aSIan Rogers { 14370d90a6aSIan Rogers "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path", 144*3235704cSIan Rogers "Counter": "0,1,2,3", 14570d90a6aSIan Rogers "CounterMask": "1", 14670d90a6aSIan Rogers "EventCode": "0x79", 14770d90a6aSIan Rogers "EventName": "IDQ.MITE_CYCLES", 14870d90a6aSIan Rogers "PublicDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path.", 14970d90a6aSIan Rogers "SampleAfterValue": "2000003", 15070d90a6aSIan Rogers "UMask": "0x4" 15170d90a6aSIan Rogers }, 15270d90a6aSIan Rogers { 15370d90a6aSIan Rogers "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path", 154*3235704cSIan Rogers "Counter": "0,1,2,3", 15570d90a6aSIan Rogers "EventCode": "0x79", 15670d90a6aSIan Rogers "EventName": "IDQ.MITE_UOPS", 15770d90a6aSIan Rogers "PublicDescription": "Increment each cycle # of uops delivered to IDQ from MITE path. Set Cmask = 1 to count cycles.", 15870d90a6aSIan Rogers "SampleAfterValue": "2000003", 15970d90a6aSIan Rogers "UMask": "0x4" 16070d90a6aSIan Rogers }, 16170d90a6aSIan Rogers { 162d2aaf040SIan Rogers "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy", 163*3235704cSIan Rogers "Counter": "0,1,2,3", 16470d90a6aSIan Rogers "CounterMask": "1", 16570d90a6aSIan Rogers "EventCode": "0x79", 16670d90a6aSIan Rogers "EventName": "IDQ.MS_CYCLES", 167d2aaf040SIan Rogers "PublicDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy.", 16870d90a6aSIan Rogers "SampleAfterValue": "2000003", 16970d90a6aSIan Rogers "UMask": "0x30" 17070d90a6aSIan Rogers }, 17170d90a6aSIan Rogers { 172d2aaf040SIan Rogers "BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy", 173*3235704cSIan Rogers "Counter": "0,1,2,3", 17470d90a6aSIan Rogers "CounterMask": "1", 17570d90a6aSIan Rogers "EventCode": "0x79", 17670d90a6aSIan Rogers "EventName": "IDQ.MS_DSB_CYCLES", 177d2aaf040SIan Rogers "PublicDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy.", 17870d90a6aSIan Rogers "SampleAfterValue": "2000003", 17970d90a6aSIan Rogers "UMask": "0x10" 18070d90a6aSIan Rogers }, 18170d90a6aSIan Rogers { 182d2aaf040SIan Rogers "BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequencer (MS) is busy", 183*3235704cSIan Rogers "Counter": "0,1,2,3", 18470d90a6aSIan Rogers "CounterMask": "1", 18570d90a6aSIan Rogers "EdgeDetect": "1", 18670d90a6aSIan Rogers "EventCode": "0x79", 18770d90a6aSIan Rogers "EventName": "IDQ.MS_DSB_OCCUR", 188d2aaf040SIan Rogers "PublicDescription": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequencer (MS) is busy.", 18970d90a6aSIan Rogers "SampleAfterValue": "2000003", 19070d90a6aSIan Rogers "UMask": "0x10" 19170d90a6aSIan Rogers }, 19270d90a6aSIan Rogers { 193d2aaf040SIan Rogers "BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy", 194*3235704cSIan Rogers "Counter": "0,1,2,3", 19570d90a6aSIan Rogers "EventCode": "0x79", 19670d90a6aSIan Rogers "EventName": "IDQ.MS_DSB_UOPS", 19770d90a6aSIan Rogers "PublicDescription": "Increment each cycle # of uops delivered to IDQ when MS_busy by DSB. Set Cmask = 1 to count cycles. Add Edge=1 to count # of delivery.", 19870d90a6aSIan Rogers "SampleAfterValue": "2000003", 19970d90a6aSIan Rogers "UMask": "0x10" 20070d90a6aSIan Rogers }, 20170d90a6aSIan Rogers { 202d2aaf040SIan Rogers "BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy", 203*3235704cSIan Rogers "Counter": "0,1,2,3", 20470d90a6aSIan Rogers "EventCode": "0x79", 20570d90a6aSIan Rogers "EventName": "IDQ.MS_MITE_UOPS", 20670d90a6aSIan Rogers "PublicDescription": "Increment each cycle # of uops delivered to IDQ when MS_busy by MITE. Set Cmask = 1 to count cycles.", 20770d90a6aSIan Rogers "SampleAfterValue": "2000003", 20870d90a6aSIan Rogers "UMask": "0x20" 20970d90a6aSIan Rogers }, 21070d90a6aSIan Rogers { 21170d90a6aSIan Rogers "BriefDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer", 212*3235704cSIan Rogers "Counter": "0,1,2,3", 21370d90a6aSIan Rogers "CounterMask": "1", 21470d90a6aSIan Rogers "EdgeDetect": "1", 21570d90a6aSIan Rogers "EventCode": "0x79", 21670d90a6aSIan Rogers "EventName": "IDQ.MS_SWITCHES", 21770d90a6aSIan Rogers "PublicDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.", 21870d90a6aSIan Rogers "SampleAfterValue": "2000003", 21970d90a6aSIan Rogers "UMask": "0x30" 22070d90a6aSIan Rogers }, 22170d90a6aSIan Rogers { 222d2aaf040SIan Rogers "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy", 223*3235704cSIan Rogers "Counter": "0,1,2,3", 22470d90a6aSIan Rogers "EventCode": "0x79", 22570d90a6aSIan Rogers "EventName": "IDQ.MS_UOPS", 22670d90a6aSIan Rogers "PublicDescription": "Increment each cycle # of uops delivered to IDQ from MS by either DSB or MITE. Set Cmask = 1 to count cycles.", 22770d90a6aSIan Rogers "SampleAfterValue": "2000003", 22870d90a6aSIan Rogers "UMask": "0x30" 22970d90a6aSIan Rogers }, 23070d90a6aSIan Rogers { 23170d90a6aSIan Rogers "BriefDescription": "Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled", 232*3235704cSIan Rogers "Counter": "0,1,2,3", 23370d90a6aSIan Rogers "EventCode": "0x9C", 23470d90a6aSIan Rogers "EventName": "IDQ_UOPS_NOT_DELIVERED.CORE", 23570d90a6aSIan Rogers "PublicDescription": "Count issue pipeline slots where no uop was delivered from the front end to the back end when there is no back-end stall.", 23670d90a6aSIan Rogers "SampleAfterValue": "2000003", 23770d90a6aSIan Rogers "UMask": "0x1" 23870d90a6aSIan Rogers }, 23970d90a6aSIan Rogers { 24070d90a6aSIan Rogers "BriefDescription": "Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled.", 241*3235704cSIan Rogers "Counter": "0,1,2,3", 24270d90a6aSIan Rogers "CounterMask": "4", 24370d90a6aSIan Rogers "EventCode": "0x9C", 244d910f0baSAndi Kleen "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE", 245d910f0baSAndi Kleen "SampleAfterValue": "2000003", 24670d90a6aSIan Rogers "UMask": "0x1" 247d910f0baSAndi Kleen }, 248d910f0baSAndi Kleen { 24970d90a6aSIan Rogers "BriefDescription": "Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.", 250*3235704cSIan Rogers "Counter": "0,1,2,3", 25170d90a6aSIan Rogers "CounterMask": "1", 25270d90a6aSIan Rogers "EventCode": "0x9C", 25370d90a6aSIan Rogers "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK", 25470d90a6aSIan Rogers "Invert": "1", 25570d90a6aSIan Rogers "SampleAfterValue": "2000003", 25670d90a6aSIan Rogers "UMask": "0x1" 25770d90a6aSIan Rogers }, 25870d90a6aSIan Rogers { 25970d90a6aSIan Rogers "BriefDescription": "Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled.", 260*3235704cSIan Rogers "Counter": "0,1,2,3", 26170d90a6aSIan Rogers "CounterMask": "3", 26270d90a6aSIan Rogers "EventCode": "0x9C", 263d910f0baSAndi Kleen "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE", 264d910f0baSAndi Kleen "SampleAfterValue": "2000003", 26570d90a6aSIan Rogers "UMask": "0x1" 266d910f0baSAndi Kleen }, 267d910f0baSAndi Kleen { 26870d90a6aSIan Rogers "BriefDescription": "Cycles with less than 2 uops delivered by the front end.", 269*3235704cSIan Rogers "Counter": "0,1,2,3", 27070d90a6aSIan Rogers "CounterMask": "2", 27170d90a6aSIan Rogers "EventCode": "0x9C", 272d910f0baSAndi Kleen "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE", 273d910f0baSAndi Kleen "SampleAfterValue": "2000003", 27470d90a6aSIan Rogers "UMask": "0x1" 275d910f0baSAndi Kleen }, 276d910f0baSAndi Kleen { 27770d90a6aSIan Rogers "BriefDescription": "Cycles with less than 3 uops delivered by the front end.", 278*3235704cSIan Rogers "Counter": "0,1,2,3", 27970d90a6aSIan Rogers "CounterMask": "1", 28070d90a6aSIan Rogers "EventCode": "0x9C", 281d910f0baSAndi Kleen "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE", 282d910f0baSAndi Kleen "SampleAfterValue": "2000003", 28370d90a6aSIan Rogers "UMask": "0x1" 284d910f0baSAndi Kleen } 285d910f0baSAndi Kleen] 286