| /linux/arch/alpha/lib/ |
| H A D | ev6-csum_ipv6_magic.S | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * arch/alpha/lib/ev6-csum_ipv6_magic.S
4 * 21264 version contributed by Rick Gorton <rick.gorton@alpha-processor.com>
15 * ftp.digital.com/pub/Digital/info/semiconductor/literature/dsc-library.html
17 * E - either cluster
18 * U - upper subcluster; U0 - subcluster U0; U1 - subcluster U1
19 * L - lower subcluster; L0 - subcluster L0; L1 - subcluster L1
32 * Then turn it back into a sign extended 32-bit item
35 * Swap <len> (an unsigned int) using Mike Burrows' 7-instruction sequence
36 * (we can't hide the 3-cycle latency of the unpkbw in the 6-instruction sequence)
[all …]
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| H A D | ev6-memchr.S | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * arch/alpha/lib/ev6-memchr.S
5 * 21264 version contributed by Rick Gorton <rick.gorton@alpha-processor.com>
9 * - memory accessed as aligned quadwords only
10 * - uses cmpbge to compare 8 bytes in parallel
11 * - does binary search to find 0 byte in last
18 * - only minimum number of quadwords may be accessed
19 * - the third argument is an unsigned long
24 * ftp.digital.com/pub/Digital/info/semiconductor/literature/dsc-library.html
26 * E - either cluster
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| H A D | memset.S | 1 /* SPDX-License-Identifier: GPL-2.0 */
10 * This routine is "moral-ware": you are free to use it any way you wish, and
35 bis $17,$1,$17 /* E0 (p-c latency, next cycle) */
36 sll $17,16,$1 /* E1 (p-c latency, next cycle) */
38 bis $17,$1,$17 /* E0 (p-c latency, next cycle) */
39 sll $17,32,$1 /* E1 (p-c latency, next cycle) */
40 bis $17,$1,$17 /* E0 (p-c latency, next cycle) */
45 addq $18,$16,$6 /* E0 */
47 xor $16,$6,$1 /* E0 */
51 beq $1,within_one_quad /* .. E1 (note EV5 zero-latency forwarding) */
[all …]
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| H A D | ev6-copy_page.S | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * arch/alpha/lib/ev6-copy_page.S
13 -----------------------------
24 that the processor can fetch at most 4 aligned instructions per cycle.
28 9 cycles but I was not able to get it to run that fast -- the initial
34 -------------------------------------
45 --------------------------------------
51 forced me to add another cycle to the inner-most kernel - up to 11
53 further by unrolling the loop and doing multiple prefetches per cycle.
68 /* Prefetch 5 read cachelines; write-hint 10 cache lines. */
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| /linux/Documentation/hwmon/ |
| H A D | dme1737.rst | 18 Addresses scanned: none, address read from Super-I/O config space
34 Addresses scanned: none, address read from Super-I/O config space
43 -----------------
52 Include non-standard LPC addresses 0x162e and 0x164e
55 - VIA EPIA SN18000
59 -----------
63 and SCH5127 Super-I/O chips. These chips feature monitoring of 3 temp sensors
64 temp[1-3] (2 remote diodes and 1 internal), 8 voltages in[0-7] (7 external and
65 1 internal) and up to 6 fan speeds fan[1-6]. Additionally, the chips implement
66 up to 5 PWM outputs pwm[1-3,5-6] for controlling fan speeds both manually and
[all …]
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| H A D | max31790.rst | 10 Addresses scanned: -
18 -----------
24 through the I2C interface. The outputs drive "4-wire" fans directly,
28 Tachometer inputs monitor fan tachometer logic outputs for precise (+/-1%)
35 -------------
38 fan[1-12]_input RO fan tachometer speed in RPM
39 fan[1-12]_fault RO fan experienced fault
40 fan[1-6]_target RW desired fan speed in RPM
41 fan[1-6]_enable RW enable or disable the tachometer input
42 pwm[1-6]_enable RW regulator mode, 0=disabled (duty cycle=0%), 1=manual mode, 2=rpm mode
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| /linux/tools/perf/pmu-events/arch/x86/sierraforest/ |
| H A D | pipeline.json | 4 "Counter": "0,1,2,3,4,5,6,7",
13 "Counter": "0,1,2,3,4,5,6,7",
21 "Counter": "0,1,2,3,4,5,6,7",
29 "Counter": "0,1,2,3,4,5,6,7",
37 "Counter": "0,1,2,3,4,5,6,7",
45 "Counter": "0,1,2,3,4,5,6,7",
53 "Counter": "0,1,2,3,4,5,6,7",
61 "Counter": "0,1,2,3,4,5,6,7",
70 "Counter": "0,1,2,3,4,5,6,7",
78 "Counter": "0,1,2,3,4,5,6,7",
[all …]
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| H A D | virtual-memory.json | 4 "Counter": "0,1,2,3,4,5,6,7",
12 "Counter": "0,1,2,3,4,5,6,7",
20 "Counter": "0,1,2,3,4,5,6,7",
29 "Counter": "0,1,2,3,4,5,6,7",
37 …Counts the number of page walks outstanding for Loads (demand or SW prefetch) in PMH every cycle.",
38 "Counter": "0,1,2,3,4,5,6,7",
41 …n PMH every cycle. A PMH page walk is outstanding from page walk start till PMH becomes idle agai…
47 "Counter": "0,1,2,3,4,5,6,7",
55 "Counter": "0,1,2,3,4,5,6,7",
63 "Counter": "0,1,2,3,4,5,6,7",
[all …]
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| /linux/tools/perf/pmu-events/arch/x86/grandridge/ |
| H A D | pipeline.json | 4 "Counter": "0,1,2,3,4,5,6,7",
13 "Counter": "0,1,2,3,4,5,6,7",
21 "Counter": "0,1,2,3,4,5,6,7",
29 "Counter": "0,1,2,3,4,5,6,7",
37 "Counter": "0,1,2,3,4,5,6,7",
45 "Counter": "0,1,2,3,4,5,6,7",
53 "Counter": "0,1,2,3,4,5,6,7",
61 "Counter": "0,1,2,3,4,5,6,7",
70 "Counter": "0,1,2,3,4,5,6,7",
78 "Counter": "0,1,2,3,4,5,6,7",
[all …]
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| H A D | virtual-memory.json | 4 "Counter": "0,1,2,3,4,5,6,7",
12 "Counter": "0,1,2,3,4,5,6,7",
20 "Counter": "0,1,2,3,4,5,6,7",
29 "Counter": "0,1,2,3,4,5,6,7",
37 …Counts the number of page walks outstanding for Loads (demand or SW prefetch) in PMH every cycle.",
38 "Counter": "0,1,2,3,4,5,6,7",
41 …n PMH every cycle. A PMH page walk is outstanding from page walk start till PMH becomes idle agai…
47 "Counter": "0,1,2,3,4,5,6,7",
55 "Counter": "0,1,2,3,4,5,6,7",
63 "Counter": "0,1,2,3,4,5,6,7",
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| /linux/include/linux/mfd/ |
| H A D | rz-mtu3.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
12 /* 8-bit shared register offsets macros */
16 /* 16-bit shared register offset macros */
19 #define RZ_MTU3_TCDRA 0x014 /* Timer cycle data register A */
20 #define RZ_MTU3_TCDRB 0x814 /* Timer cycle data register B */
21 #define RZ_MTU3_TCBRA 0x022 /* Timer cycle buffer register A */
22 #define RZ_MTU3_TCBRB 0x822 /* Timer cycle buffer register B */
31 /* 8-bit register offset macros of MTU3 channels except MTU5 */
44 #define RZ_MTU3_TIOR 6 /* Timer I/O control register */
45 #define RZ_MTU3_TIORH 6 /* Timer I/O control register H */
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| /linux/tools/perf/pmu-events/arch/x86/meteorlake/ |
| H A D | virtual-memory.json | 4 "Counter": "0,1,2,3,4,5,6,7",
34 "Counter": "0,1,2,3,4,5,6,7",
63 "Counter": "0,1,2,3,4,5,6,7",
83 "Counter": "0,1,2,3,4,5,6,7",
102 …Counts the number of page walks outstanding for Loads (demand or SW prefetch) in PMH every cycle.",
103 "Counter": "0,1,2,3,4,5,6,7",
106 …n PMH every cycle. A PMH page walk is outstanding from page walk start till PMH becomes idle agai…
112 … "BriefDescription": "Number of page walks outstanding for a demand load in the PMH each cycle.",
116 …the number of page walks outstanding for a demand load in the PMH (Page Miss Handler) each cycle.",
123 "Counter": "0,1,2,3,4,5,6,7",
[all …]
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| H A D | pipeline.json | 4 "Counter": "0,1,2,3,4,5,6,7",
14 "Counter": "0,1,2,3,4,5,6,7",
18 …y executing divide or square root operations. Accounts for integer and floating-point operations.",
25 "Counter": "0,1,2,3,4,5,6,7",
35 "Counter": "0,1,2,3,4,5,6,7",
45 "Counter": "0,1,2,3,4,5,6,7",
54 "Counter": "0,1,2,3,4,5,6,7",
64 "Counter": "0,1,2,3,4,5,6,7",
73 "Counter": "0,1,2,3,4,5,6,7",
84 "Counter": "0,1,2,3,4,5,6,7",
[all …]
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| H A D | frontend.json | 4 "Counter": "0,1,2,3,4,5,6,7",
17 …"PublicDescription": "Number of times the front-end is resteered when it finds a branch instructio…
27 …e number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length …
42 "BriefDescription": "DSB-to-MITE switch true penalty cycles.",
46 …"PublicDescription": "Decode Stream Buffer (DSB) is a Uop-cache that holds translations of previou…
53 "Counter": "0,1,2,3,4,5,6,7",
66 "Counter": "0,1,2,3,4,5,6,7",
72 …Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.",
79 "Counter": "0,1,2,3,4,5,6,7",
85 …ode stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to …
[all …]
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| /linux/drivers/ata/ |
| H A D | libata-pata-timings.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright 2003-2004 Red Hat, Inc. All rights reserved.
6 * Copyright 2003-2004 Jeff Garzik
15 * drivers/ide/ide-timing.h and was originally written by Vojtech Pavlik
18 * PIO 0-4, MWDMA 0-2 and UDMA 0-6 timings (in nanoseconds).
19 * These were taken from ATA/ATAPI-6 standard, rev 0a, except
22 * For PIO 5/6 MWDMA 3/4 see the CFA specification 3.0.
57 #define ENOUGH(v, unit) (((v)-1)/(unit)+1)
63 q->setup = EZ(t->setup, T); in ata_timing_quantize()
64 q->act8b = EZ(t->act8b, T); in ata_timing_quantize()
[all …]
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| H A D | pata_icside.c | 1 // SPDX-License-Identifier: GPL-2.0-only
35 .stepping = 6,
41 .stepping = 6,
47 .stepping = 6,
80 #define ICS_TYPE_NOTYPE ((unsigned int)-1)
82 /* ---------------- Version 5 PCB Support Functions --------------------- */
88 struct pata_icside_state *state = ec->irq_data; in pata_icside_irqenable_arcin_v5()
90 writeb(0, state->irq_port + ICS_ARCIN_V5_INTROFFSET); in pata_icside_irqenable_arcin_v5()
98 struct pata_icside_state *state = ec->irq_data; in pata_icside_irqdisable_arcin_v5()
100 readb(state->irq_port + ICS_ARCIN_V5_INTROFFSET); in pata_icside_irqdisable_arcin_v5()
[all …]
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| /linux/tools/perf/pmu-events/arch/x86/alderlake/ |
| H A D | pipeline.json | 4 "Counter": "0,1,2,3,4,5,6,7",
15 "Counter": "0,1,2,3,4,5,6,7",
19 …y executing divide or square root operations. Accounts for integer and floating-point operations.",
26 "Counter": "0,1,2,3,4,5,6,7",
37 "Counter": "0,1,2,3,4,5,6,7",
47 "Counter": "0,1,2,3,4,5,6,7",
58 "Counter": "0,1,2,3,4,5,6,7",
78 "Counter": "0,1,2,3,4,5,6,7",
109 "Counter": "0,1,2,3,4,5,6,7",
120 "Counter": "0,1,2,3,4,5,6,7",
[all …]
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| H A D | frontend.json | 17 …"PublicDescription": "Number of times the front-end is resteered when it finds a branch instructio…
27 …e number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length …
42 "BriefDescription": "DSB-to-MITE switch true penalty cycles.",
46 …"PublicDescription": "Decode Stream Buffer (DSB) is a Uop-cache that holds translations of previou…
53 "Counter": "0,1,2,3,4,5,6,7",
59 …Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.",
66 "Counter": "0,1,2,3,4,5,6,7",
72 …ode stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to …
79 "Counter": "0,1,2,3,4,5,6,7",
92 "Counter": "0,1,2,3,4,5,6,7",
[all …]
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| /linux/drivers/pwm/ |
| H A D | pwm-sl28cpld.c | 1 // SPDX-License-Identifier: GPL-2.0-only
8 * enough to be briefly explained. It consists of one 8-bit counter. The PWM
15 * +-----------+--------+--------------+-----------+---------------+
17 * +-----------+--------+--------------+-----------+---------------+
18 * | 0 | cnt[7] | cnt[6:0] | 250 Hz | 4000000 ns |
19 * | 1 | cnt[6] | cnt[5:0] | 500 Hz | 2000000 ns |
22 * +-----------+--------+--------------+-----------+---------------+
25 * - The hardware cannot generate a 100% duty cycle if the prescaler is 0.
26 * - The hardware cannot atomically set the prescaler and the counter value,
28 * - The counter is not reset if you switch the prescaler which leads
[all …]
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| /linux/tools/perf/pmu-events/arch/x86/sapphirerapids/ |
| H A D | frontend.json | 7 …"PublicDescription": "Number of times the front-end is resteered when it finds a branch instructio…
16 …e number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length …
29 "BriefDescription": "DSB-to-MITE switch true penalty cycles.",
33 …"PublicDescription": "Decode Stream Buffer (DSB) is a Uop-cache that holds translations of previou…
39 "Counter": "0,1,2,3,4,5,6,7",
45 …Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.",
51 "Counter": "0,1,2,3,4,5,6,7",
57 …ode stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to …
63 "Counter": "0,1,2,3,4,5,6,7",
75 "Counter": "0,1,2,3,4,5,6,7",
[all …]
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| /linux/tools/perf/pmu-events/arch/x86/emeraldrapids/ |
| H A D | frontend.json | 7 …"PublicDescription": "Number of times the front-end is resteered when it finds a branch instructio…
16 …e number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length …
29 "BriefDescription": "DSB-to-MITE switch true penalty cycles.",
33 …"PublicDescription": "Decode Stream Buffer (DSB) is a Uop-cache that holds translations of previou…
39 "Counter": "0,1,2,3,4,5,6,7",
45 …Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.",
51 "Counter": "0,1,2,3,4,5,6,7",
57 …ode stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to …
63 "Counter": "0,1,2,3,4,5,6,7",
75 "Counter": "0,1,2,3,4,5,6,7",
[all …]
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| /linux/tools/perf/pmu-events/arch/x86/graniterapids/ |
| H A D | frontend.json | 7 …"PublicDescription": "Number of times the front-end is resteered when it finds a branch instructio…
16 …e number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length …
29 "BriefDescription": "DSB-to-MITE switch true penalty cycles.",
33 …"PublicDescription": "Decode Stream Buffer (DSB) is a Uop-cache that holds translations of previou…
39 "Counter": "0,1,2,3,4,5,6,7",
51 "Counter": "0,1,2,3,4,5,6,7",
57 …Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.",
63 "Counter": "0,1,2,3,4,5,6,7",
69 …ode stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to …
75 "Counter": "0,1,2,3,4,5,6,7",
[all …]
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| /linux/drivers/mfd/ |
| H A D | atmel-smc.c | 1 // SPDX-License-Identifier: GPL-2.0-only
8 * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
11 #include <linux/mfd/syscon/atmel-smc.h>
15 * atmel_smc_cs_conf_init - initialize a SMC CS conf
27 * atmel_smc_cs_encode_ncycles - encode a number of MCK clk cycles in the
36 * (section "SMC Setup/Pulse/Cycle/Timings Register"). This is a generic
40 * If the @ncycles value is too big to be encoded, -ERANGE is returned and
49 unsigned int lsbmask = GENMASK(msbpos - 1, 0); in atmel_smc_cs_encode_ncycles()
50 unsigned int msbmask = GENMASK(msbwidth - 1, 0); in atmel_smc_cs_encode_ncycles()
65 * We still return -ERANGE in case the caller cares. in atmel_smc_cs_encode_ncycles()
[all …]
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| /linux/sound/firewire/ |
| H A D | amdtp-stream.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Audio and Music Data Transmission Protocol (IEC 61883-6) streams
4 * with Common Isochronous Packet (IEC 61883-1) headers
12 #include <linux/firewire-constants.h>
17 #include "amdtp-stream.h"
27 #include "amdtp-stream-trace.h"
83 * amdtp_stream_init - initialize an AMDTP stream structure
87 * @flags: the details of the streaming protocol consist of cip_flags enumeration-constants.
99 return -EINVAL; in amdtp_stream_init()
101 s->protocol = kzalloc(protocol_size, GFP_KERNEL); in amdtp_stream_init()
[all …]
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| /linux/arch/alpha/kernel/ |
| H A D | core_cia.c | 1 // SPDX-License-Identifier: GPL-2.0
34 * NOTE: Herein lie back-to-back mb instructions. They are magic.
57 * 3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0
58 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
60 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
69 * 3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0
70 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
72 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
81 * The function number selects which function of a multi-function device
93 u8 bus = bus_dev->number; in mk_conf_addr()
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