Lines Matching +full:cycle +full:- +full:6
7 …"PublicDescription": "Number of times the front-end is resteered when it finds a branch instructio…
16 …e number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length …
29 "BriefDescription": "DSB-to-MITE switch true penalty cycles.",
33 …"PublicDescription": "Decode Stream Buffer (DSB) is a Uop-cache that holds translations of previou…
39 "Counter": "0,1,2,3,4,5,6,7",
51 "Counter": "0,1,2,3,4,5,6,7",
57 …Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.",
63 "Counter": "0,1,2,3,4,5,6,7",
69 …ode stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to …
75 "Counter": "0,1,2,3,4,5,6,7",
87 "Counter": "0,1,2,3,4,5,6,7",
99 "Counter": "0,1,2,3,4,5,6,7",
110 "BriefDescription": "Retired instructions after front-end starvation of at least 1 cycle",
111 "Counter": "0,1,2,3,4,5,6,7",
117 …er an interval where the front-end delivered no uops for a period of at least 1 cycle which was no…
122 …after an interval where the front-end delivered no uops for a period of 128 cycles which was not i…
123 "Counter": "0,1,2,3,4,5,6,7",
129 …after an interval where the front-end delivered no uops for a period of 128 cycles which was not i…
134 … after an interval where the front-end delivered no uops for a period of 16 cycles which was not i…
135 "Counter": "0,1,2,3,4,5,6,7",
141 …tions that are delivered to the back-end after a front-end stall of at least 16 cycles. During thi…
146 "BriefDescription": "Retired instructions after front-end starvation of at least 2 cycles",
147 "Counter": "0,1,2,3,4,5,6,7",
153 …er an interval where the front-end delivered no uops for a period of at least 2 cycles which was n…
158 …after an interval where the front-end delivered no uops for a period of 256 cycles which was not i…
159 "Counter": "0,1,2,3,4,5,6,7",
165 …after an interval where the front-end delivered no uops for a period of 256 cycles which was not i…
170 …er an interval where the front-end had at least 1 bubble-slot for a period of 2 cycles which was n…
171 "Counter": "0,1,2,3,4,5,6,7",
177 …delivered to the back-end after the front-end had at least 1 bubble-slot for a period of 2 cycles.…
182 … after an interval where the front-end delivered no uops for a period of 32 cycles which was not i…
183 "Counter": "0,1,2,3,4,5,6,7",
189 …tions that are delivered to the back-end after a front-end stall of at least 32 cycles. During thi…
194 … after an interval where the front-end delivered no uops for a period of 4 cycles which was not in…
195 "Counter": "0,1,2,3,4,5,6,7",
201 … after an interval where the front-end delivered no uops for a period of 4 cycles which was not in…
206 …after an interval where the front-end delivered no uops for a period of 512 cycles which was not i…
207 "Counter": "0,1,2,3,4,5,6,7",
213 …after an interval where the front-end delivered no uops for a period of 512 cycles which was not i…
218 … after an interval where the front-end delivered no uops for a period of 64 cycles which was not i…
219 "Counter": "0,1,2,3,4,5,6,7",
225 … after an interval where the front-end delivered no uops for a period of 64 cycles which was not i…
230 … after an interval where the front-end delivered no uops for a period of 8 cycles which was not in…
231 "Counter": "0,1,2,3,4,5,6,7",
237 …tions that are delivered to the back-end after a front-end stall of at least 8 cycles. During this…
242 "BriefDescription": "I-Cache miss too close to Code Prefetch Instruction",
243 "Counter": "0,1,2,3,4,5,6,7",
249 …tion": "Number of Instruction Cache demand miss in shadow of an on-going i-fetch cache-line trigge…
255 "Counter": "0,1,2,3,4,5,6,7",
267 "Counter": "0,1,2,3,4,5,6,7",
278 "Counter": "0,1,2,3,4,5,6,7",
290 "Counter": "0,1,2,3,4,5,6,7",
340 "CounterMask": "6",
369 "CounterMask": "6",
416 … when no operation was delivered to the back-end pipeline due to instruction fetch limitations whe…
417 "Counter": "0,1,2,3,4,5,6,7",
420 …-end pipeline due to instruction fetch limitations when the back-end could have accepted more oper…
426 "Counter": "0,1,2,3,4,5,6,7",
427 "CounterMask": "6",
430 …ueue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts fo…
435 …ion": "Cycles when optimal number of uops was delivered to the back-end when the back-end is not s…
436 "Counter": "0,1,2,3,4,5,6,7",
441 …ueue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts fo…
447 "Counter": "0,1,2,3,4,5,6,7",
450 …ueue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts fo…
456 "Counter": "0,1,2,3,4,5,6,7",
457 "CounterMask": "6",
460 …ueue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts fo…
465 …ion": "Cycles when optimal number of uops was delivered to the back-end when the back-end is not s…
466 "Counter": "0,1,2,3,4,5,6,7",
471 …ueue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts fo…