Lines Matching +full:cycle +full:- +full:6

1 /* SPDX-License-Identifier: GPL-2.0 */
3  * arch/alpha/lib/ev6-memchr.S
5  * 21264 version contributed by Rick Gorton <rick.gorton@alpha-processor.com>
9  *    - memory accessed as aligned quadwords only
10  *    - uses cmpbge to compare 8 bytes in parallel
11  *    - does binary search to find 0 byte in last
18  *    - only minimum number of quadwords may be accessed
19  *    - the third argument is an unsigned long
24  *	ftp.digital.com/pub/Digital/info/semiconductor/literature/dsc-library.html
26  *	E	- either cluster
27  *	U	- upper subcluster; U0 - subcluster U0; U1 - subcluster U1
28  *	L	- lower subcluster; L0 - subcluster L0; L1 - subcluster L1
42 	# Hack -- if someone passes in (size_t)-1, hoping to just
45 	# that we will never have a 56-bit address space, cropping
55         lda     $3, -1($31)	# E : U L L U
65 	ldq_u	$6, -1($5)	# L : L U U L : eight or less bytes to search Latency=3
67 	extqh	$6, $16, $6	# U : 2 cycle stall for $6
70 	or	$7, $6, $1	# E : L U L U $1 = quadword starting at $16
74 	#	$18 = 6
77 	negq	$18, $6		# E :
79 	srl	$3, $6, $6	# U : $6 = mask of $18 bits set
84 	and	$2, $6, $2	# E :
107         cmoveq  $1, $3, $0	# E : Latency 2, extra map cycle
110         addq    $0, 2, $3	# E : U L U L : 2 cycle stall on $0
112         cmoveq  $1, $3, $0	# E : Latency 2, extra map cycle
115         addq    $0, 1, $3	# E : U L U L : 2 cycle stall on $0
117         cmoveq  $1, $3, $0	# E : Latency 2, extra map cycle
147 	subq	$18, $0, $4	# E : $4 <- nr quads to be processed
169 	addq	$0, 8, $6	# E :
172 	cmpult	$6, $18, $6	# E :
176 	bne	$6, $unrolled_loop # U :
181 $final:	subq	$5, $0, $18	# E : $18 <- number of bytes left to do