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/freebsd/lib/libpmc/pmu-events/arch/x86/amdzen1/
H A D	floating-point.json	5 "BriefDescription": "Total number multi-pipe uOps assigned to all pipes.", 6 …-pipe uOps dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the F… 12 "BriefDescription": "Total number multi-pipe uOps assigned to pipe 3.", 13 …-pipe uOps dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the F… 19 "BriefDescription": "Total number multi-pipe uOps assigned to pipe 2.", 20 …-pipe uOps dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the F… 26 "BriefDescription": "Total number multi-pipe uOps assigned to pipe 1.", 27 …-pipe uOps dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the F… 33 "BriefDescription": "Total number multi-pipe uOps assigned to pipe 0.", 34 …-pipe uOps dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the F… [all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/ivybridge/
H A D	floating-point.json	16 "CounterHTOff": "0,1,2,3,4,5,6,7", 26 "CounterHTOff": "0,1,2,3,4,5,6,7", 36 "CounterHTOff": "0,1,2,3,4,5,6,7", 46 "CounterHTOff": "0,1,2,3,4,5,6,7", 54 …"BriefDescription": "Number of SSE* or AVX-128 FP Computational packed double-precision uops issue… 56 "CounterHTOff": "0,1,2,3,4,5,6,7", 59 …PublicDescription": "Number of SSE* or AVX-128 FP Computational packed double-precision uops issue… 64 …"BriefDescription": "Number of SSE* or AVX-128 FP Computational packed single-precision uops issue… 66 "CounterHTOff": "0,1,2,3,4,5,6,7", 69 …PublicDescription": "Number of SSE* or AVX-128 FP Computational packed single-precision uops issue… [all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/ivytown/
H A D	floating-point.json	16 "CounterHTOff": "0,1,2,3,4,5,6,7", 26 "CounterHTOff": "0,1,2,3,4,5,6,7", 36 "CounterHTOff": "0,1,2,3,4,5,6,7", 46 "CounterHTOff": "0,1,2,3,4,5,6,7", 54 …"BriefDescription": "Number of SSE* or AVX-128 FP Computational packed double-precision uops issue… 56 "CounterHTOff": "0,1,2,3,4,5,6,7", 59 …PublicDescription": "Number of SSE* or AVX-128 FP Computational packed double-precision uops issue… 64 …"BriefDescription": "Number of SSE* or AVX-128 FP Computational packed single-precision uops issue… 66 "CounterHTOff": "0,1,2,3,4,5,6,7", 69 …PublicDescription": "Number of SSE* or AVX-128 FP Computational packed single-precision uops issue… [all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/amdzen3/
H A D	floating-point.json	6 …4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for … 13 …4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for … 20 …4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for … 27 …4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for … 34 …4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for … 40 …n": "All FLOPS. This is a retire-based event. The number of retired SSE/AVX FLOPS. The number of e… 46 …-Accumulate FLOPs. Each MAC operation is counted as 2 FLOPS. This is a retire-based event. The num… 52 …-based event. The number of retired SSE/AVX FLOPs. The number of events logged per cycle can vary … 58 …-based event. The number of retired SSE/AVX FLOPs. The number of events logged per cycle can vary … 64 …-based event. The number of retired SSE/AVX FLOPs. The number of events logged per cycle can vary … [all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/jaketown/
H A D	floating-point.json	15 "CounterHTOff": "0,1,2,3,4,5,6,7", 24 "CounterHTOff": "0,1,2,3,4,5,6,7", 33 "CounterHTOff": "0,1,2,3,4,5,6,7", 42 "CounterHTOff": "0,1,2,3,4,5,6,7", 49 …"BriefDescription": "Number of SSE* or AVX-128 FP Computational packed double-precision uops issue… 51 "CounterHTOff": "0,1,2,3,4,5,6,7", 58 …"BriefDescription": "Number of SSE* or AVX-128 FP Computational packed single-precision uops issue… 60 "CounterHTOff": "0,1,2,3,4,5,6,7", 67 …"BriefDescription": "Number of SSE* or AVX-128 FP Computational scalar double-precision uops issue… 69 "CounterHTOff": "0,1,2,3,4,5,6,7", [all …]
H A D	jkt-metrics.json	4 "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)", 7 …-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into mi… 11 …"MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CL… 14 …-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into mi… 18 …"MetricExpr": "( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * INT_MISC.RECOVERY_CYCLES ) / (4… 21 …s for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For… 25 …"MetricExpr": "( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY … 28 …s for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For… 33 …- ( (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) + (( UOPS_ISSUED.ANY - UOPS_RETI… 36 …-of-order scheduler dispatches ready uops into their respective execution units; and once complete… [all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/sandybridge/
H A D	floating-point.json	15 "CounterHTOff": "0,1,2,3,4,5,6,7", 24 "CounterHTOff": "0,1,2,3,4,5,6,7", 33 "CounterHTOff": "0,1,2,3,4,5,6,7", 42 "CounterHTOff": "0,1,2,3,4,5,6,7", 49 …"BriefDescription": "Number of SSE* or AVX-128 FP Computational packed double-precision uops issue… 51 "CounterHTOff": "0,1,2,3,4,5,6,7", 58 …"BriefDescription": "Number of SSE* or AVX-128 FP Computational packed single-precision uops issue… 60 "CounterHTOff": "0,1,2,3,4,5,6,7", 67 …"BriefDescription": "Number of SSE* or AVX-128 FP Computational scalar double-precision uops issue… 69 "CounterHTOff": "0,1,2,3,4,5,6,7", [all …]
H A D	snb-metrics.json	4 "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)", 7 …-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into mi… 11 …"MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CL… 14 …-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into mi… 18 …"MetricExpr": "( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * INT_MISC.RECOVERY_CYCLES ) / (4… 21 …s for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For… 25 …"MetricExpr": "( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY … 28 …s for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For… 33 …- ( (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) + (( UOPS_ISSUED.ANY - UOPS_RETI… 36 …-of-order scheduler dispatches ready uops into their respective execution units; and once complete… [all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/amdzen2/
H A D	floating-point.json	6 …4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for … 13 …4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for … 20 …4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for … 27 …4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for … 34 …4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for … 40 …n": "All FLOPS. This is a retire-based event. The number of retired SSE/AVX FLOPS. The number of e… 46 …ly-add FLOPS. Multiply-add counts as 2 FLOPS. This is a retire-based event. The number of retired … 53 …are root FLOPS. This is a retire-based event. The number of retired SSE/AVX FLOPS. The number of e… 59 …Multiply FLOPS. This is a retire-based event. The number of retired SSE/AVX FLOPS. The number of e… 65 …subtract FLOPS. This is a retire-based event. The number of retired SSE/AVX FLOPS. The number of e… [all …]
/freebsd/contrib/lua/src/
H A D	lgc.h	22 can be visited again before finishing the collection cycle. (Open 35 #define GCSswpfinobj 4 43 (GCSswpallgc <= (g)->gcstate && (g)->gcstate <= GCSswpend) 50 still-black objects. The invariant is restored when sweep ends and 54 #define keepinvariant(g) ((g)->gcstate <= GCSatomic) 76 #define WHITE1BIT 4 /* object is white (type 1) */ 87 #define iswhite(x) testbits((x)->marked, WHITEBITS) 88 #define isblack(x) testbit((x)->marked, BLACKBIT) 90 (!testbits((x)->marked, WHITEBITS \| bitmask(BLACKBIT))) 92 #define tofinalize(x) testbit((x)->marked, FINALIZEDBIT) [all …]
/freebsd/share/doc/psd/18.gprof/
H A D	present.me	`69 0.20 1.20 4/10 \ \ \s-1CALLER1\s+1 [7] 70 0.30 1.80 6/10 \ \ \s-1CALLER2\s+1 [1] 71 [2] 41.5 0.50 3.00 10+4 \s-1EXAMPLE\s+1 [2] 72 1.50 1.00 20/40 \ \ \s-1SUB1\s+1 <cycle1> [4] 73 0.00 0.50 1/5 \ \ \s-1SUB2\s+1 [9] 74 0.00 0.00 0/5 \ \ \s-1SUB3\s+1 [11] 77 Profile entry for \s-1EXAMPLE\s+1. 78 Figure 4. 82 but we are limited by the two-dimensional nature of our output 116 The cycle as a whole is shown as though it were a single routine, [all …]`
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A D	P9InstrResources.td	1 //===- P9InstrResources.td - P9 Instruction Resource Defs -- tablegen --==// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 16 // - Each CPU is made up of two superslices. 17 // - Each superslice is made up of two slices. Therefore, there are 4 slices 19 // - Up to 6 instructions can be dispatched to each CPU. Three per superslice. 20 // - Each CPU has: 21 // - One CY (Crypto) unit P9_CY_* 22 // - One DFU (Decimal Floating Point and Quad Precision) unit P9_DFU_* 23 // - Two PM (Permute) units. One on each superslice. P9_PM_* [all …]
/freebsd/sys/contrib/device-tree/Bindings/net/
H A D	gpmc-eth.txt	4 General-Purpose Memory Controller can be used to connect Pseudo-SRAM devices 12 Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt 18 Child nodes need to specify the GPMC bus address width using the "bank-width" 20 specify the I/O registers address width. Even when the GPMC has a maximum 16-bit 21 address width, it supports devices with 32-bit word registers. 23 OMAP2+ board, "bank-width = <2>;" and "reg-io-width = <4>;". 26 - bank-width: Address width of the device in bytes. GPMC supports 8-bit 27 and 16-bit devices and so must be either 1 or 2 bytes. 28 - compatible: Compatible string property for the ethernet child device. 29 - gpmc,cs-on-ns: Chip-select assertion time [all …]
/freebsd/lib/libpmc/
H A D	pmc.haswell.3	`45 .Bl -tag -width "Li PMC_CLASS_IAP" 47 Fixed-function counters that count only one hardware event per counter. 59 .%B "Intel(R) 64 and IA-32 Architectures Software Developer's Manual" 61 .%N "Order Number: 325462-045US" 70 .Bl -column "PMC_CAP_INTERRUPT" "Support" 87 .Bl -tag -width indent 89 Configure the Off-core Response bits. 90 .Bl -tag -width indent 128 M-state initial lookup stat in L3. 130 E-state. [all …]`
H A D	pmc.haswellxeon.3	`46 .Bl -tag -width "Li PMC_CLASS_IAP" 48 Fixed-function counters that count only one hardware event per counter. 60 .%B "Intel(R) 64 and IA-32 Architectures Software Developer's Manual" 62 .%N "Order Number: 325462-052US" 71 .Bl -column "PMC_CAP_INTERRUPT" "Support" 88 .Bl -tag -width indent 90 Configure the Off-core Response bits. 91 .Bl -tag -width indent 129 M-state initial lookup stat in L3. 131 E-state. [all …]`
/freebsd/lib/libpmc/pmu-events/arch/x86/goldmontplus/
H A D	virtual-memory.json	15 "BriefDescription": "Page walk completed due to a demand load to a 2M or 4M page", 22 …hose address translations missed in all TLB levels and were mapped to 2M or 4M pages. The page wa… 27 "BriefDescription": "Page walk completed due to a demand load to a 4K page", 34 …hes) whose address translations missed in all TLB levels and were mapped to 4K pages. The page wa… 39 "BriefDescription": "Page walks outstanding due to a demand load every cycle.", 46 …"PublicDescription": "Counts once per cycle for each page walk occurring due to a load (demand dat… 63 "BriefDescription": "Page walk completed due to a demand data store to a 2M or 4M page", 70 …tores whose address translations missed in the TLB and were mapped to 2M or 4M pages. The page wa… 75 "BriefDescription": "Page walk completed due to a demand data store to a 4K page", 82 …data stores whose address translations missed in the TLB and were mapped to 4K pages. The page wa… [all …]
/freebsd/contrib/llvm-project/llvm/tools/llvm-mca/Views/
H A D	TimelineView.h	1 //===--------------------- TimelineView.h ------------------------ C++ --===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 10 /// This file implements a timeline view for the llvm-mca tool. 25 /// [0,4] . D==eeeER. .. vaddss %xmm3, %xmm2, %xmm4 28 /// [1,0] . DeE------R .. vmovshdup %xmm0, %xmm1 29 /// [1,1] . DeE------R .. vpermilpd $1, %xmm0, %xmm2 30 /// [1,2] . DeE-----R .. vpermilps $231, %xmm0, %xmm5 31 /// [1,3] . D=eeeE--R .. vaddss %xmm1, %xmm0, %xmm3 32 /// [1,4] . D===eeeER .. vaddss %xmm3, %xmm2, %xmm4 [all …]
/freebsd/share/doc/papers/kerntune/
H A D	2.t	78 but we are limited by the two-dimensional nature of our output 104 0.20 1.20 4/10 \ \ \s-1CALLER1\s+1 [7] 105 0.30 1.80 6/10 \ \ \s-1CALLER2\s+1 [1] 106 [2] 41.5 0.50 3.00 10+4 \s-1EXAMPLE\s+1 [2] 107 1.50 1.00 20/40 \ \ \s-1SUB1\s+1 <cycle1> [4] 108 0.00 0.50 1/5 \ \ \s-1SUB2\s+1 [9] 109 0.00 0.00 0/5 \ \ \s-1SUB3\s+1 [11] 112 Figure 1. Profile entry for \s-1EXAMPLE\s+1. 136 The cycle as a whole is shown as though it were a single routine, 137 except that members of the cycle are listed in place of the children. [all …]
/freebsd/sys/contrib/device-tree/Bindings/spi/
H A D	renesas,sh-msiof.yaml	`1 # SPDX-License-Identifier: GPL-2.0 3 --- 4 $id: http://devicetree.org/schemas/spi/renesas,sh-msiof.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Geert Uytterhoeven <geert+renesas@glider.be> 13 - $ref: spi-controller.yaml# 18 - items: 19 - const: renesas,msiof-sh73a0 # SH-Mobile AG5 20 - const: renesas,sh-mobile-msiof # generic SH-Mobile compatible 22 - items: [all …]`
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A D	AArch64SchedOryon.td	1 //=- AArch64SchedOryon.td - Qualcomm Oryon CPU 001 ---- tablegen --=// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 12 //===----------------------------------------------------------------------===// 14 //===----------------------------------------------------------------------===// 20 let LoadLatency = 4; 37 // LSU has 4 ports p6 ~ p9(ls0 ~ ls3), p10/p11(std0, std1) has to work with ls0~ls3 38 // VXU has 4 ports p12 ~ p15 65 // Port 4: ALU. 139 // Multiply/Multiply-ADD instructions on ports I4/I5. [all …]
/freebsd/sys/contrib/device-tree/Bindings/input/
H A D	azoteq,iqs7222.yaml	`1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 5 $schema: http://devicetree.org/meta-schema [all...]`
/freebsd/lib/libpmc/pmu-events/arch/s390/cf_z10/
H A D	basic.json	6 "PublicDescription": "Cycle Count" 18 "PublicDescription": "Level-1 I-Cache Directory Write Count" 24 "PublicDescription": "Level-1 I-Cache Penalty Cycle Count" 27 "EventCode": "4", 30 "PublicDescription": "Level-1 D-Cache Directory Write Count" 36 "PublicDescription": "Level-1 D-Cache Penalty Cycle Count" 41 "BriefDescription": "Problem-State CPU Cycles", 42 "PublicDescription": "Problem-State Cycle Count" 47 "BriefDescription": "Problem-State Instructions", 48 "PublicDescription": "Problem-State Instruction Count" [all …]
/freebsd/lib/libpmc/pmu-events/arch/s390/cf_z13/
H A D	basic.json	6 "PublicDescription": "Cycle Count" 18 "PublicDescription": "Level-1 I-Cache Directory Write Count" 24 "PublicDescription": "Level-1 I-Cache Penalty Cycle Count" 27 "EventCode": "4", 30 "PublicDescription": "Level-1 D-Cache Directory Write Count" 36 "PublicDescription": "Level-1 D-Cache Penalty Cycle Count" 41 "BriefDescription": "Problem-State CPU Cycles", 42 "PublicDescription": "Problem-State Cycle Count" 47 "BriefDescription": "Problem-State Instructions", 48 "PublicDescription": "Problem-State Instruction Count" [all …]
/freebsd/lib/libpmc/pmu-events/arch/s390/cf_z196/
H A D	basic.json	6 "PublicDescription": "Cycle Count" 18 "PublicDescription": "Level-1 I-Cache Directory Write Count" 24 "PublicDescription": "Level-1 I-Cache Penalty Cycle Count" 27 "EventCode": "4", 30 "PublicDescription": "Level-1 D-Cache Directory Write Count" 36 "PublicDescription": "Level-1 D-Cache Penalty Cycle Count" 41 "BriefDescription": "Problem-State CPU Cycles", 42 "PublicDescription": "Problem-State Cycle Count" 47 "BriefDescription": "Problem-State Instructions", 48 "PublicDescription": "Problem-State Instruction Count" [all …]
/freebsd/lib/libpmc/pmu-events/arch/s390/cf_zec12/
H A D	basic.json	6 "PublicDescription": "Cycle Count" 18 "PublicDescription": "Level-1 I-Cache Directory Write Count" 24 "PublicDescription": "Level-1 I-Cache Penalty Cycle Count" 27 "EventCode": "4", 30 "PublicDescription": "Level-1 D-Cache Directory Write Count" 36 "PublicDescription": "Level-1 D-Cache Penalty Cycle Count" 41 "BriefDescription": "Problem-State CPU Cycles", 42 "PublicDescription": "Problem-State Cycle Count" 47 "BriefDescription": "Problem-State Instructions", 48 "PublicDescription": "Problem-State Instruction Count" [all …]

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