Lines Matching +full:cycle +full:- +full:4

46 .Bl -tag -width "Li PMC_CLASS_IAP"
48 Fixed-function counters that count only one hardware event per counter.
60 .%B "Intel(R) 64 and IA-32 Architectures Software Developer's Manual"
62 .%N "Order Number: 325462-052US"
71 .Bl -column "PMC_CAP_INTERRUPT" "Support"
88 .Bl -tag -width indent
90 Configure the Off-core Response bits.
91 .Bl -tag -width indent
129 M-state initial lookup stat in L3.
131 E-state.
133 S-state.
135 F-state.
139 No details on snoop-related information.
149 Hit denotes a cache-line was valid before snoop effect.
160 A snoop was needed and it HitM-ed in local or remote cache.
161 HitM denotes a cache-line was in modified state before effect as a results of snoop.
167 Target was non-DRAM system address.
172 events measured in a cycle is greater than or equal to
175 Configure the PMC to count the number of de-asserted to asserted
184 events per cycle is less than the value specified by the
202 .Bl -tag -width indent
209 Speculative cache-line split load uops dispatched to
213 Speculative cache-line split Store-address uops
226 that caused 4K page walks in any TLB levels.
230 that caused 2M/4M page walks in any TLB levels.
237 Cycle PMH is busy with a walk.
240 Load misses that missed DTLB but hit STLB (4K).
250 DTLB demand load misses with low part of linear-to-
259 ncrements each cycle the # of Uops issued by the
265 Number of flags-merge uops allocated.
334 .Pq Event 2EH , Umask 4FH
355 every cycle.
360 page size (4K/2M/4M/1G).
364 more TLB levels of 4K page structure.
368 more TLB levels of 2M/4M page structure.
372 levels of any page size (4K/2M/4M/1G).
378 Store misses that missed DTLB but hit STLB (4K).
388 DTLB store misses with low part of linear-to-physical
391 .Pq Event 4CH , Umask 01H
392 Non-SW-prefetch load dispatches that hit fill buffer
395 .Pq Event 4CH , Umask 02H
396 Non-SW-prefetch load dispatches that hit fill buffer
457 Increment each cycle # of uops delivered to IDQ from
462 Increment each cycle. # of uops delivered to IDQ
467 Increment each cycle # of uops delivered to IDQ
473 ncrement each cycle # of uops delivered to IDQ
478 Increment each cycle # of uops delivered to IDQ from
488 Set Cmask =4.
496 Set Cmask =4.
511 Completed page walks due to misses in ITLB 4K page
515 Completed page walks due to misses in ITLB 2M/4M
522 Cycle PMH is busy with a walk.
525 ITLB misses that hit STLB (4K).
596 Count number of non-delivered uops to RAT per
616 Cycles which a Uop is dispatched on port 4 in this
643 Cycles stalled due to re-order buffer full.
647 Set Cmask=2 to count cycle.
651 Set Cmask=2 to count cycle.
658 Set Cmask=8 to count cycle.
662 4k/2M/4M pages.
678 Counts total number of uops to be executed per-core
679 each cycle.
714 DTLB flush attempts of the thread-specific entries.
727 Number of transitions from AVX-256 to legacy SSE
731 Number of transitions from SSE to AVX-256 when
739 Counts the number of micro-ops retired, Use
745 cycle.
752 Number of self-modifying-code machine clears
858 and cross-core snoop missed in on-pkg core cache.
862 cross-core snoop hits in on-pkg core cache.
877 Number of front end re-steers due to BPU
945 .Xr hwpmc 4