Lines Matching +full:cycle +full:- +full:4
1 //=- AArch64SchedOryon.td - Qualcomm Oryon CPU 001 ---*- tablegen -*-=//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
20 let LoadLatency = 4;
37 // LSU has 4 ports p6 ~ p9(ls0 ~ ls3), p10/p11(std0, std1) has to work with ls0~ls3
38 // VXU has 4 ports p12 ~ p15
65 // Port 4: ALU.
139 // Multiply/Multiply-ADD instructions on ports I4/I5.
165 // Arithmetic and CRYP-AED ASIMD/FP instructions on ports FP0/FP1/FP2/FP3.
181 // CRYP-SHA instructions on ports FP1.
288 // b. Link Register Update on pipes 0 and 1 taking 1 cycle
289 // c. Indirect branch on pipe 0 taking 1 cycle
301 // 1 cycle on I012345
304 // 1 cycle on I0123
307 // 1 cycle on 2 of I012345
311 // 2 cycle on 2 of I0123 with ReleaseAtCycles
318 // 2 cycle on 2 of I012345
325 // 3 cycle on 2 of I45
332 // 3 cycle on I45
337 // 7 cycle on I2 32-bit integer division
343 // 9 cycle on I2 64-bit integer division
351 // 4 cycle on LS(P6789)
353 let Latency = 4;
356 // 4 cycle for Post/Pre inc/dec access, also covers all pair loads Post/Pre
358 let Latency = 4;
361 // 5 (4+1) for VXU SIMD access/could also include FP
379 let NumMicroOps = 4;
402 // 6 cycle for Post/Pre inc/dec access
419 let NumMicroOps = 4;
442 // 1 cycle for all generic stores
454 let NumMicroOps = 4;
473 // 1 cycle for neon write: float + ASIMD with Post/Pre Inc/Dec access
488 let NumMicroOps = 4;
512 // On VXU doc, p37 -- latencies and throughput
515 let Latency = 4;
525 // Latency is 3, FCVT is also 3 cycle
552 let Latency = 4;
576 // 2 cycle on FP1
581 // 3 cycle on FP1
586 // 4 cycle , 0.5 throughput on FP1
588 let Latency = 4;
589 let ReleaseAtCycles = [4];
592 // 5 cycle , 1 throughput on FP1
597 // 8 cycle , 2 throughput on FP0123
640 let Latency = 4;
646 let Latency = 4;
653 let Latency = 4;
661 let NumMicroOps = 4;
665 //===----------------------------------------------------------------------===//
667 //===----------------------------------------------------------------------===//
669 //---
671 //---
681 //1,1,4 alias CMP, CMN on page 75
689 //1,1,4
698 //1,1,4
703 //---
705 //---
713 //1,1,4
717 //---
719 //---
728 // 3 uOp, 1 cycle for branch, 7 cycle for Authentication,
729 // 1 cycle for updating link register
739 //---
741 //1,1,4 TST is an alias of ANDS
761 //---
763 //---
771 //---
772 // Move-Data Bit-field and Sign_Extension Instructions
773 //---
785 //---
787 //---
794 //---
796 //---
798 //1,1,4
802 //---
804 //---
811 //---
813 //---
821 //---
823 //---
832 //---
839 //---
841 //---
860 //===----------------------------------------------------------------------===//
862 //===----------------------------------------------------------------------===//
864 // 4 cycle Load-to-use from L1D$
865 // Neon load with 5 cycle
866 // 6 cycle to STA ?
867 // STD cycle ?
873 // Load pair, immed pre-index, normal
874 // Load pair, immed pre-index, signed words
875 // Load pair, immed post-index, normal
876 // Load pair, immed post-index, signed words
1004 // Store register, immed post-index
1007 // Store register, immed pre-index
1010 // Store pair, immed post-index, W-form
1011 // Store pair, immed post-indx, X-form
1012 // Store pair, immed pre-index, W-form
1013 // Store pair, immed pre-index, X-form
1093 // ASIMD Load instructions, 4 cycle access + 2 cycle NEON access
1094 // ASIMD load, 1 element, multiple, 1 reg, D-form 1uOps
1095 // ASIMD load, 1 element, multiple, 1 reg, Q-form 1uOps
1097 (instregex "^LD1Onev(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
1100 (instregex "^LD1Onev(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
1102 // ASIMD load, 1 element, multiple, 2 reg, D-form 3 uOps
1103 // ASIMD load, 1 element, multiple, 2 reg, Q-form 2 uOps
1105 (instregex "^LD1Twov(8b|4h|2s|1d)$")>;
1108 (instregex "^LD1Twov(16b|8h|4s|2d)$")>;
1111 (instregex "^LD1Twov(8b|4h|2s|1d)_POST$")>;
1114 (instregex "^LD1Twov(16b|8h|4s|2d)_POST$")>;
1116 // ASIMD load, 1 element, multiple, 3 reg, D-form 4 uOps
1117 // ASIMD load, 1 element, multiple, 3 reg, Q-form 3 uOps
1119 (instregex "^LD1Threev(8b|4h|2s|1d)$")>;
1122 (instregex "^LD1Threev(16b|8h|4s|2d)$")>;
1125 (instregex "^LD1Threev(8b|4h|2s|1d)_POST$")>;
1128 (instregex "^LD1Threev(16b|8h|4s|2d)_POST$")>;
1130 // ASIMD load, 1 element, multiple, 4 reg, D-form 6 uOps
1131 // ASIMD load, 1 element, multiple, 4 reg, Q-form 4 uOps
1133 (instregex "^LD1Fourv(8b|4h|2s|1d)$")>;
1135 (instregex "^LD1Fourv(16b|8h|4s|2d)$")>;
1138 (instregex "^LD1Fourv(8b|4h|2s|1d)_POST$")>;
1140 (instregex "^LD1Fourv(16b|8h|4s|2d)_POST$")>;
1148 // ASIMD load, 1 element, all lanes, D-form, B/H/S 2uOps
1149 // ASIMD load, 1 element, all lanes, D-form, D 2uOps
1150 // ASIMD load, 1 element, all lanes, Q-form 2uOps
1152 (instregex "^LD1Rv(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
1154 (instregex "^LD1Rv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
1156 // ASIMD load, 2 element, multiple, D-form, B/H/S 3 uOps
1157 // ASIMD load, 2 element, multiple, Q-form, D 4 uOps
1159 (instregex "^LD2Twov(8b|4h|2s)$")>;
1161 (instregex "^LD2Twov(16b|8h|4s|2d)$")>;
1163 (instregex "^LD2Twov(8b|4h|2s)_POST$")>;
1165 (instregex "^LD2Twov(16b|8h|4s|2d)_POST$")>;
1174 // ASIMD load, 2 element, all lanes, D-form, B/H/S 3 uOps
1175 // ASIMD load, 2 element, all lanes, D-form, D 3 uOps
1176 // ASIMD load, 2 element, all lanes, Q-form 3 uOps
1178 (instregex "^LD2Rv(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
1180 (instregex "^LD2Rv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
1182 // ASIMD load, 3 element, multiple, D-form, B/H/S 5 uOps
1183 // ASIMD load, 3 element, multiple, Q-form, B/H/S 6 uOps
1184 // ASIMD load, 3 element, multiple, Q-form, D 6 uOps
1186 (instregex "^LD3Threev(8b|4h|2s)$")>;
1188 (instregex "^LD3Threev(16b|8h|4s|2d)$")>;
1190 (instregex "^LD3Threev(8b|4h|2s)_POST$")>;
1192 (instregex "^LD3Threev(16b|8h|4s|2d)_POST$")>;
1194 // ASIMD load, 3 element, one lone, B/H 4 uOps
1195 // ASIMD load, 3 element, one lane, S 4 uOps
1204 // ASIMD load, 3 element, all lanes, D-form, B/H/S 4 uOps
1205 // ASIMD load, 3 element, all lanes, D-form, D 5 uOps
1206 // ASIMD load, 3 element, all lanes, Q-form, B/H/S 4 uOps
1207 // ASIMD load, 3 element, all lanes, Q-form, D 5 uOps
1209 (instregex "^LD3Rv(8b|4h|2s|16b|8h|4s)$")>;
1213 (instregex "^LD3Rv(8b|4h|2s|16b|8h|4s)_POST$")>;
1217 // ASIMD load, 4 element, multiple, D-form, B/H/S 6 uOps
1218 // ASIMD load, 4 element, multiple, Q-form, B/H/S 10 uOps
1219 // ASIMD load, 4 element, multiple, Q-form, D 8 uOps
1221 (instregex "^LD4Fourv(8b|4h|2s)$")>;
1223 (instregex "^LD4Fourv(16b|8h|4s)$")>;
1227 (instregex "^LD4Fourv(8b|4h|2s)_POST$")>;
1229 (instregex "^LD4Fourv(16b|8h|4s)_POST$")>;
1233 // ASIMD load, 4 element, one lane, B/H 5 uOps
1234 // ASIMD load, 4 element, one lane, S 5 uOps
1235 // ASIMD load, 4 element, one lane, D 6 uOps
1243 // ASIMD load, 4 element, all lanes, D-form, B/H/S 5 uOps
1244 // ASIMD load, 4 element, all lanes, D-form, D 6 uOps
1245 // ASIMD load, 4 element, all lanes, Q-form, B/H/S 5 uOps
1246 // ASIMD load, 4 element, all lanes, Q-form, D 6 uOps
1248 (instregex "^LD4Rv(8b|4h|2s|16b|8h|4s)$")>;
1252 (instregex "^LD4Rv(8b|4h|2s|16b|8h|4s)_POST$")>;
1257 // ASIMD store, 1 element, multiple, 1 reg, D-form 1 uOps
1258 // ASIMD store, 1 element, multiple, 1 reg, Q-form 1 uops
1260 (instregex "^ST1Onev(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
1262 (instregex "^ST1Onev(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
1264 // ASIMD store, 1 element, multiple, 2 reg, D-form 2 uOps
1265 // ASIMD store, 1 element, multiple, 2 reg, Q-form 2 uOps
1267 (instregex "^ST1Twov(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
1269 (instregex "^ST1Twov(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
1271 // ASIMD store, 1 element, multiple, 3 reg, D-form 3 uOps
1272 // ASIMD store, 1 element, multiple, 3 reg, Q-form 3 uOps
1274 (instregex "^ST1Threev(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
1276 (instregex "^ST1Threev(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
1278 // ASIMD store, 1 element, multiple, 4 reg, D-form 4 uOps
1279 // ASIMD store, 1 element, multiple, 4 reg, Q-form 4 uOps
1281 (instregex "^ST1Fourv(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
1283 (instregex "^ST1Fourv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
1292 // ASIMD store, 2 element, multiple, D-form, B/H/S 2 uOps
1293 // ASIMD store, 2 element, multiple, Q-form, B/H/S 4 uOps
1294 // ASIMD store, 2 element, multiple, Q-form, D 4 uOps
1296 (instregex "^ST2Twov(8b|4h|2s)$")>;
1298 (instregex "^ST2Twov(16b|8h|4s|2d)$")>;
1300 (instregex "^ST2Twov(8b|4h|2s)_POST$")>;
1302 (instregex "^ST2Twov(16b|8h|4s|2d)_POST$")>;
1311 // ASIMD store, 3 element, multiple, D-form, B/H/S 4 uOps
1312 // ASIMD store, 3 element, multiple, Q-form, B/H/S 6 uOps
1313 // ASIMD store, 3 element, multiple, Q-form, D 6 uOps
1315 (instregex "^ST3Threev(8b|4h|2s)$")>;
1317 (instregex "^ST3Threev(16b|8h|4s|2d)$")>;
1319 (instregex "^ST3Threev(8b|4h|2s)_POST$")>;
1321 (instregex "^ST3Threev(16b|8h|4s|2d)_POST$")>;
1325 // ASIMD store, 3 element, one lane, D 4 uOps
1334 // ASIMD store, 4 element, multiple, D-form, B/H/S 5 uOps
1335 // ASIMD store, 4 element, multiple, Q-form, B/H/S 10 uOps
1336 // ASIMD store, 4 element, multiple, Q-form, D 8 uOps
1338 (instregex "^ST4Fourv(8b|4h|2s)$")>;
1340 (instregex "^ST4Fourv(16b|8h|4s)$")>;
1344 (instregex "^ST4Fourv(8b|4h|2s)_POST$")>;
1346 (instregex "^ST4Fourv(16b|8h|4s)_POST$")>;
1350 // ASIMD store, 4 element, one lane, B/H 3 uOps
1351 // ASIMD store, 4 element, one lane, S 3 uOps
1352 // ASIMD store, 4 element, one lane, D 4 uOps
1361 //===----------------------------------------------------------------------===//
1363 //===----------------------------------------------------------------------===//
1394 // floating multiply-add
1397 // floating unary, cycle/throughput? xls row14
1551 // SIMD floating-point and integer conversion instructions
1579 // TBL 1-reg/2-reg; TBX 1-reg, 1uOp, throughput=4 latency=2
1584 // TBL 3-reg/4-reg, 3uops, throughtput=4/3=1.33 latency=4
1590 // TBX 2-reg 2 uOps, throughput=2 latency=4
1593 // TBX 3-reg/4-reg, 4uOps, throughput=1, latency=6
1608 // 3,4 on IMLA, CRYP
1612 // 2,4 on CRYP
1633 // 4,0.25 on CRYP
1640 // 4,2 on IMLA
1643 // 4,0.5 on IMLA
1646 // 4,0.5 on IMLA
1649 // 3,4
1655 // 3,4