Lines Matching +full:cycle +full:- +full:4

45 .Bl -tag -width "Li PMC_CLASS_IAP"
47 Fixed-function counters that count only one hardware event per counter.
59 .%B "Intel(R) 64 and IA-32 Architectures Software Developer's Manual"
61 .%N "Order Number: 325462-045US"
70 .Bl -column "PMC_CAP_INTERRUPT" "Support"
87 .Bl -tag -width indent
89 Configure the Off-core Response bits.
90 .Bl -tag -width indent
128 M-state initial lookup stat in L3.
130 E-state.
132 S-state.
134 F-state.
138 No details on snoop-related information.
148 Hit denotes a cache-line was valid before snoop effect.
159 A snoop was needed and it HitM-ed in local or remote cache.
160 HitM denotes a cache-line was in modified state before effect as a results of snoop.
166 Target was non-DRAM system address.
171 events measured in a cycle is greater than or equal to
174 Configure the PMC to count the number of de-asserted to asserted
183 events per cycle is less than the value specified by the
201 .Bl -tag -width indent
208 Speculative cache-line split load uops dispatched to
212 Speculative cache-line split Store-address uops
225 that caused 4K page walks in any TLB levels.
229 that caused 2M/4M page walks in any TLB levels.
236 Cycle PMH is busy with a walk.
239 Load misses that missed DTLB but hit STLB (4K).
249 DTLB demand load misses with low part of linear-to-
258 ncrements each cycle the # of Uops issued by the
264 Number of flags-merge uops allocated.
333 .Pq Event 2EH , Umask 4FH
351 Increments the number of outstanding L1D misses every cycle.
356 page size (4K/2M/4M/1G).
360 more TLB levels of 4K page structure.
364 more TLB levels of 2M/4M page structure.
368 levels of any page size (4K/2M/4M/1G).
374 Store misses that missed DTLB but hit STLB (4K).
384 DTLB store misses with low part of linear-to-physical
387 .Pq Event 4CH , Umask 01H
388 Non-SW-prefetch load dispatches that hit fill buffer
391 .Pq Event 4CH , Umask 02H
392 Non-SW-prefetch load dispatches that hit fill buffer
449 Increment each cycle # of uops delivered to IDQ from MITE path.
453 Increment each cycle. # of uops delivered to IDQ
458 Increment each cycle # of uops delivered to IDQ when MS_busy by DSB.
463 ncrement each cycle # of uops delivered to IDQ when MS_busy by MITE.
467 Increment each cycle # of uops delivered to IDQ from MS by either DSB or MITE.
476 Set Cmask=4.
484 Set Cmask =4.
498 Completed page walks due to misses in ITLB 4K page
502 Completed page walks due to misses in ITLB 2M/4M
509 Cycle PMH is busy with a walk.
512 ITLB misses that hit STLB (4K).
583 Count number of non-delivered uops to RAT per
603 Cycles which a Uop is dispatched on port 4 in this
630 Cycles stalled due to re-order buffer full.
634 Set Cmask=2 to count cycle.
638 Set Cmask=2 to count cycle.
645 Set Cmask=8 to count cycle.
649 4k/2M/4M pages.
666 Counts total number of uops to be executed per-core
667 each cycle.
702 DTLB flush attempts of the thread-specific entries.
715 Number of transitions from AVX-256 to legacy SSE
719 Number of transitions from SSE to AVX-256 when
727 Counts the number of micro-ops retired, Use
733 cycle.
740 Number of self-modifying-code machine clears
845 and cross-core snoop missed in on-pkg core cache.
849 cross-core snoop hits in on-pkg core cache.
864 Number of front end re-steers due to BPU
931 .Xr hwpmc 4
938 .An -nosplit