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/linux/arch/alpha/lib/
H A Dev6-csum_ipv6_magic.S1 /* SPDX-License-Identifier: GPL-2.0 */
3 * arch/alpha/lib/ev6-csum_ipv6_magic.S
4 * 21264 version contributed by Rick Gorton <rick.gorton@alpha-processor.com>
15 * ftp.digital.com/pub/Digital/info/semiconductor/literature/dsc-library.html
17 * E - either cluster
18 * U - upper subcluster; U0 - subcluster U0; U1 - subcluster U1
19 * L - lower subcluster; L0 - subcluster L0; L1 - subcluster L1
32 * Then turn it back into a sign extended 32-bit item
35 * Swap <len> (an unsigned int) using Mike Burrows' 7-instruction sequence
36 * (we can't hide the 3-cycle latency of the unpkbw in the 6-instruction sequence)
[all …]
H A Dmemset.S1 /* SPDX-License-Identifier: GPL-2.0 */
10 * This routine is "moral-ware": you are free to use it any way you wish, and
35 bis $17,$1,$17 /* E0 (p-c latency, next cycle) */
36 sll $17,16,$1 /* E1 (p-c latency, next cycle) */
38 bis $17,$1,$17 /* E0 (p-c latency, next cycle) */
39 sll $17,32,$1 /* E1 (p-c latency, next cycle) */
40 bis $17,$1,$17 /* E0 (p-c latency, next cycle) */
51 beq $1,within_one_quad /* .. E1 (note EV5 zero-latency forwarding) */
52 and $16,7,$3 /* E0 */
53 beq $3,aligned /* .. E1 (note EV5 zero-latency forwarding) */
[all …]
H A Dev6-memchr.S1 /* SPDX-License-Identifier: GPL-2.0 */
3 * arch/alpha/lib/ev6-memchr.S
5 * 21264 version contributed by Rick Gorton <rick.gorton@alpha-processor.com>
9 * - memory accessed as aligned quadwords only
10 * - uses cmpbge to compare 8 bytes in parallel
11 * - does binary search to find 0 byte in last
18 * - only minimum number of quadwords may be accessed
19 * - the third argument is an unsigned long
24 * ftp.digital.com/pub/Digital/info/semiconductor/literature/dsc-library.html
26 * E - either cluster
[all …]
/linux/Documentation/hwmon/
H A Ddme1737.rst18 Addresses scanned: none, address read from Super-I/O config space
34 Addresses scanned: none, address read from Super-I/O config space
43 -----------------
52 Include non-standard LPC addresses 0x162e and 0x164e
55 - VIA EPIA SN18000
59 -----------
63 and SCH5127 Super-I/O chips. These chips feature monitoring of 3 temp sensors
64 temp[1-3] (2 remote diodes and 1 internal), 8 voltages in[0-7] (7 external and
65 1 internal) and up to 6 fan speeds fan[1-6]. Additionally, the chips implement
66 up to 5 PWM outputs pwm[1-3,5-6] for controlling fan speeds both manually and
[all …]
H A Dvt1211.rst10 Addresses scanned: none, address read from Super-I/O config space
24 -----------------
29 configuration for channels 1-5.
30 Legal values are in the range of 0-31. Bit 0 maps to
47 -----------
49 The VIA VT1211 Super-I/O chip includes complete hardware monitoring
52 implements 5 universal input channels (UCH1-5) that can be individually
60 connected to the PWM outputs of the VT1211 :-().
69 Reading 3 temp2 Internal thermal diode
80 ------------------
[all …]
/linux/tools/perf/pmu-events/arch/x86/ivybridge/
H A Dfloating-point.json4 "Counter": "0,1,2,3",
14 "Counter": "0,1,2,3",
23 "Counter": "0,1,2,3",
32 "Counter": "0,1,2,3",
41 "Counter": "0,1,2,3",
49 …"BriefDescription": "Number of SSE* or AVX-128 FP Computational packed double-precision uops issue…
50 "Counter": "0,1,2,3",
53 …PublicDescription": "Number of SSE* or AVX-128 FP Computational packed double-precision uops issue…
58 …"BriefDescription": "Number of SSE* or AVX-128 FP Computational packed single-precision uops issue…
59 "Counter": "0,1,2,3",
[all …]
/linux/tools/perf/pmu-events/arch/x86/ivytown/
H A Dfloating-point.json4 "Counter": "0,1,2,3",
14 "Counter": "0,1,2,3",
23 "Counter": "0,1,2,3",
32 "Counter": "0,1,2,3",
41 "Counter": "0,1,2,3",
49 …"BriefDescription": "Number of SSE* or AVX-128 FP Computational packed double-precision uops issue…
50 "Counter": "0,1,2,3",
53 …PublicDescription": "Number of SSE* or AVX-128 FP Computational packed double-precision uops issue…
58 …"BriefDescription": "Number of SSE* or AVX-128 FP Computational packed single-precision uops issue…
59 "Counter": "0,1,2,3",
[all …]
/linux/tools/perf/pmu-events/arch/x86/elkhartlake/
H A Dpipeline.json4 "Counter": "0,1,2,3",
13 "Counter": "0,1,2,3",
22 "Counter": "0,1,2,3",
31 "Counter": "0,1,2,3",
40 "Counter": "0,1,2,3",
49 "Counter": "0,1,2,3",
58 "Counter": "0,1,2,3",
67 "Counter": "0,1,2,3",
76 "Counter": "0,1,2,3",
85 "Counter": "0,1,2,3",
[all …]
/linux/tools/perf/pmu-events/arch/x86/snowridgex/
H A Dpipeline.json4 "Counter": "0,1,2,3",
13 "Counter": "0,1,2,3",
22 "Counter": "0,1,2,3",
31 "Counter": "0,1,2,3",
40 "Counter": "0,1,2,3",
49 "Counter": "0,1,2,3",
58 "Counter": "0,1,2,3",
67 "Counter": "0,1,2,3",
76 "Counter": "0,1,2,3",
85 "Counter": "0,1,2,3",
[all …]
H A Duncore-cache.json4 "Counter": "0,1,2,3",
9 … : For Transgress 0 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
15 "Counter": "0,1,2,3",
20 … : For Transgress 1 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
26 "Counter": "0,1,2,3",
31 … : For Transgress 2 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
36 "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 3",
37 "Counter": "0,1,2,3",
42 … Agent0 AD Credits Acquired : For Transgress 3 : Number of CMS Agent 0 AD credits acquired in a gi…
48 "Counter": "0,1,2,3",
[all …]
/linux/tools/perf/pmu-events/arch/x86/alderlaken/
H A Dpipeline.json4 "Counter": "0,1,2,3,4,5",
13 "Counter": "0,1,2,3,4,5",
23 "Counter": "0,1,2,3,4,5",
32 "Counter": "0,1,2,3,4,5",
41 "Counter": "0,1,2,3,4,5",
50 "Counter": "0,1,2,3,4,5",
59 "Counter": "0,1,2,3,4,5",
68 "Counter": "0,1,2,3,4,5",
78 "Counter": "0,1,2,3,4,5",
88 "Counter": "0,1,2,3,4,5",
[all …]
/linux/tools/perf/pmu-events/arch/x86/jaketown/
H A Dfloating-point.json4 "Counter": "0,1,2,3",
13 "Counter": "0,1,2,3",
21 "Counter": "0,1,2,3",
29 "Counter": "0,1,2,3",
37 "Counter": "0,1,2,3",
44 …"BriefDescription": "Number of SSE* or AVX-128 FP Computational packed double-precision uops issue…
45 "Counter": "0,1,2,3",
52 …"BriefDescription": "Number of SSE* or AVX-128 FP Computational packed single-precision uops issue…
53 "Counter": "0,1,2,3",
60 …"BriefDescription": "Number of SSE* or AVX-128 FP Computational scalar double-precision uops issue…
[all …]
/linux/tools/perf/pmu-events/arch/x86/sandybridge/
H A Dfloating-point.json4 "Counter": "0,1,2,3",
13 "Counter": "0,1,2,3",
21 "Counter": "0,1,2,3",
29 "Counter": "0,1,2,3",
37 "Counter": "0,1,2,3",
44 …"BriefDescription": "Number of SSE* or AVX-128 FP Computational packed double-precision uops issue…
45 "Counter": "0,1,2,3",
52 …"BriefDescription": "Number of SSE* or AVX-128 FP Computational packed single-precision uops issue…
53 "Counter": "0,1,2,3",
60 …"BriefDescription": "Number of SSE* or AVX-128 FP Computational scalar double-precision uops issue…
[all …]
/linux/tools/perf/pmu-events/arch/x86/sierraforest/
H A Dpipeline.json4 "Counter": "0,1,2,3,4,5,6,7",
13 "Counter": "0,1,2,3,4,5,6,7",
21 "Counter": "0,1,2,3,4,5,6,7",
29 "Counter": "0,1,2,3,4,5,6,7",
37 "Counter": "0,1,2,3,4,5,6,7",
45 "Counter": "0,1,2,3,4,5,6,7",
53 "Counter": "0,1,2,3,4,5,6,7",
61 "Counter": "0,1,2,3,4,5,6,7",
70 "Counter": "0,1,2,3,4,5,6,7",
78 "Counter": "0,1,2,3,4,5,6,7",
[all …]
H A Dvirtual-memory.json4 "Counter": "0,1,2,3,4,5,6,7",
12 "Counter": "0,1,2,3,4,5,6,7",
20 "Counter": "0,1,2,3,4,5,6,7",
29 "Counter": "0,1,2,3,4,5,6,7",
37 …Counts the number of page walks outstanding for Loads (demand or SW prefetch) in PMH every cycle.",
38 "Counter": "0,1,2,3,4,5,6,7",
41 …n PMH every cycle. A PMH page walk is outstanding from page walk start till PMH becomes idle agai…
47 "Counter": "0,1,2,3,4,5,6,7",
55 "Counter": "0,1,2,3,4,5,6,7",
63 "Counter": "0,1,2,3,4,5,6,7",
[all …]
/linux/tools/perf/pmu-events/arch/x86/grandridge/
H A Dpipeline.json4 "Counter": "0,1,2,3,4,5,6,7",
13 "Counter": "0,1,2,3,4,5,6,7",
21 "Counter": "0,1,2,3,4,5,6,7",
29 "Counter": "0,1,2,3,4,5,6,7",
37 "Counter": "0,1,2,3,4,5,6,7",
45 "Counter": "0,1,2,3,4,5,6,7",
53 "Counter": "0,1,2,3,4,5,6,7",
61 "Counter": "0,1,2,3,4,5,6,7",
70 "Counter": "0,1,2,3,4,5,6,7",
78 "Counter": "0,1,2,3,4,5,6,7",
[all …]
H A Dvirtual-memory.json4 "Counter": "0,1,2,3,4,5,6,7",
12 "Counter": "0,1,2,3,4,5,6,7",
20 "Counter": "0,1,2,3,4,5,6,7",
29 "Counter": "0,1,2,3,4,5,6,7",
37 …Counts the number of page walks outstanding for Loads (demand or SW prefetch) in PMH every cycle.",
38 "Counter": "0,1,2,3,4,5,6,7",
41 …n PMH every cycle. A PMH page walk is outstanding from page walk start till PMH becomes idle agai…
47 "Counter": "0,1,2,3,4,5,6,7",
55 "Counter": "0,1,2,3,4,5,6,7",
63 "Counter": "0,1,2,3,4,5,6,7",
[all …]
/linux/tools/perf/pmu-events/arch/x86/amdzen1/
H A Dfloating-point.json5 "BriefDescription": "Total number multi-pipe uOps assigned to all pipes.",
6 …-pipe uOps dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the F…
12 "BriefDescription": "Total number multi-pipe uOps assigned to pipe 3.",
13 …-pipe uOps dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the F…
19 "BriefDescription": "Total number multi-pipe uOps assigned to pipe 2.",
20 …-pipe uOps dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the F…
26 "BriefDescription": "Total number multi-pipe uOps assigned to pipe 1.",
27 …-pipe uOps dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the F…
33 "BriefDescription": "Total number multi-pipe uOps assigned to pipe 0.",
34 …-pipe uOps dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the F…
[all …]
/linux/include/linux/mfd/
H A Drz-mtu3.h1 /* SPDX-License-Identifier: GPL-2.0 */
12 /* 8-bit shared register offsets macros */
16 /* 16-bit shared register offset macros */
19 #define RZ_MTU3_TCDRA 0x014 /* Timer cycle data register A */
20 #define RZ_MTU3_TCDRB 0x814 /* Timer cycle data register B */
21 #define RZ_MTU3_TCBRA 0x022 /* Timer cycle buffer register A */
22 #define RZ_MTU3_TCBRB 0x822 /* Timer cycle buffer register B */
27 * MTU5 contains 3 timer counter registers and is totaly different
31 /* 8-bit register offset macros of MTU3 channels except MTU5 */
35 #define RZ_MTU3_TCR 3 /* Timer control register */
[all …]
/linux/tools/perf/pmu-events/arch/x86/goldmontplus/
H A Dvirtual-memory.json4 "Counter": "0,1,2,3",
13 "Counter": "0,1,2,3",
22 "Counter": "0,1,2,3",
30 "BriefDescription": "Page walks outstanding due to a demand load every cycle.",
31 "Counter": "0,1,2,3",
34 …"PublicDescription": "Counts once per cycle for each page walk occurring due to a load (demand dat…
40 "Counter": "0,1,2,3",
49 "Counter": "0,1,2,3",
58 "Counter": "0,1,2,3",
66 "BriefDescription": "Page walks outstanding due to a demand data store every cycle.",
[all …]
H A Dcache.json4 "Counter": "0,1,2,3",
12 "Counter": "0,1,2,3",
20 "BriefDescription": "Cycles code-fetch stalled due to an outstanding ICache miss.",
21 "Counter": "0,1,2,3",
30 "Counter": "0,1,2,3",
33 …from the intra-die interconnect (IDI) fabric. The XQ may reject transactions from the L2Q (non-cac…
38 "Counter": "0,1,2,3",
47 "Counter": "0,1,2,3",
56 "Counter": "0,1,2,3",
67 "Counter": "0,1,2,3",
[all …]
/linux/tools/perf/pmu-events/arch/x86/meteorlake/
H A Dvirtual-memory.json4 "Counter": "0,1,2,3,4,5,6,7",
13 "Counter": "0,1,2,3",
23 "Counter": "0,1,2,3",
34 "Counter": "0,1,2,3,4,5,6,7",
43 "Counter": "0,1,2,3",
53 "Counter": "0,1,2,3",
63 "Counter": "0,1,2,3,4,5,6,7",
73 "Counter": "0,1,2,3",
83 "Counter": "0,1,2,3,4,5,6,7",
93 "Counter": "0,1,2,3",
[all …]
/linux/tools/perf/pmu-events/arch/x86/amdzen3/
H A Dfloating-point.json6 … Each increment represents a one- cycle dispatch event. This event is a speculative event. Since t…
12 "BriefDescription": "Total number uOps assigned to pipe 3.",
13 …-cycle dispatch event. This event is a speculative event. Since this event includes non-numeric op…
20 … Each increment represents a one- cycle dispatch event. This event is a speculative event. Since t…
27 … Each increment represents a one- cycle dispatch event. This event is a speculative event. Since t…
34 … Each increment represents a one- cycle dispatch event. This event is a speculative event. Since t…
40 …n": "All FLOPS. This is a retire-based event. The number of retired SSE/AVX FLOPS. The number of e…
46 …-Accumulate FLOPs. Each MAC operation is counted as 2 FLOPS. This is a retire-based event. The num…
52 …-based event. The number of retired SSE/AVX FLOPs. The number of events logged per cycle can vary …
58 …-based event. The number of retired SSE/AVX FLOPs. The number of events logged per cycle can vary …
[all …]
/linux/Documentation/admin-guide/perf/
H A Dalibaba_pmu.rst2 Alibaba's T-Head SoC Uncore Performance Monitoring Unit (PMU)
5 The Yitian 710, custom-built by Alibaba Group's chip development business,
6 T-Head, implements uncore PMU for performance and functional debugging to
9 DDR Sub-System Driveway (DRW) PMU Driver
14 channel is split into two independent sub-channels. The DDR Sub-System Driveway
15 implements separate PMUs for each sub-channel to monitor various performance
20 sub-channels of the same channel in die 0. And the PMU device of die 1 is
23 Each sub-channel has 36 PMU counters in total, which is classified into
26 - Group 0: PMU Cycle Counter. This group has one pair of counters
27 pmu_cycle_cnt_low and pmu_cycle_cnt_high, that is used as the cycle count
[all …]
/linux/Documentation/devicetree/bindings/spi/
H A Drenesas,sh-msiof.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/spi/renesas,sh-msiof.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Geert Uytterhoeven <geert+renesas@glider.be>
13 - $ref: spi-controller.yaml#
18 - items:
19 - const: renesas,msiof-sh73a0 # SH-Mobile AG5
20 - const: renesas,sh-mobile-msiof # generic SH-Mobile compatible
22 - items:
[all …]

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