Lines Matching +full:cycle +full:- +full:3

1 /* SPDX-License-Identifier: GPL-2.0 */
3  * arch/alpha/lib/ev6-csum_ipv6_magic.S
4  * 21264 version contributed by Rick Gorton <rick.gorton@alpha-processor.com>
15  *	ftp.digital.com/pub/Digital/info/semiconductor/literature/dsc-library.html
17  *	E	- either cluster
18  *	U	- upper subcluster; U0 - subcluster U0; U1 - subcluster U1
19  *	L	- lower subcluster; L0 - subcluster L0; L1 - subcluster L1
32  * Then turn it back into a sign extended 32-bit item
35  * Swap <len> (an unsigned int) using Mike Burrows' 7-instruction sequence
36  * (we can't hide the 3-cycle latency of the unpkbw in the 6-instruction sequence)
41  * add carry bits + ushort --> ushort
42  * add carry bits + ushort --> ushort (in case the carry results in an overflow)
47  * add the 3 low ushorts together, generating a uint
53  * may cause additional delay in rare cases (load-load replay traps).
64 	ldq_u	$0,0($16)	# L : Latency: 3
66 	ldq_u	$1,8($16)	# L : Latency: 3
70 	ldq_u	$5,15($16)	# L : Latency: 3
72 	ldq_u	$2,0($17)	# L : U L U L : Latency: 3
76 	ldq_u	$3,8($17)	# L : Latency: 3
80 	ldq_u	$23,15($17)	# L : Latency: 3
81 	inswl	$18,3,$18	# U : 000000CCDD000000
92 	extqh	$3,$6,$22	# U : L U L U :
95 	extql	$3,$6,$3	# U :
102 	or	$3,$23,$3	# E : U L U L : 2nd dst word complete
115 	addq	$20,$3,$20	# E :
116 	cmpult	$20,$3,$3	# E : (1 cycle stall on $20)
117 	addq	$20,$18,$20	# E : U L U L (1 cycle stall on $20)
120 	addq	$20,$19,$20	# E : (1 cycle stall on $20)
122 	addq	$2,$3,$2	# E :
125 	addq	$18,$19,$18	# E : (1 cycle stall on $19)
128 		/* (1 cycle stall on $18, 2 cycles on $20) */
131 	zapnot	$0,15,$1	# U : Start folding output (1 cycle stall on $0)
133 	srl	$0,32,$0	# U : U L U L : (1 cycle stall on $0)
136 	extwl	$1,2,$2		# U : ushort[1] (1 cycle stall on $1)
137 	zapnot	$1,3,$0		# U : ushort[0] (1 cycle stall on $1)
138 	extwl	$1,4,$1		# U : ushort[2] (1 cycle stall on $1)
141 	addq	$0,$1,$3	# E : Finished generating uint
142 		/* (1 cycle stall on $0) */
143 	extwl	$3,2,$1		# U : ushort[1] (1 cycle stall on $3)
146 	addq	$1,$3,$0	# E : Final carry
147 	not	$0,$4		# E : complement (1 cycle stall on $0)
148 	zapnot	$4,3,$0		# U : clear upper garbage bits
149 		/* (1 cycle stall on $4) */