Lines Matching +full:cycle +full:- +full:3

1 /* SPDX-License-Identifier: GPL-2.0 */
3  * arch/alpha/lib/ev6-memchr.S
5  * 21264 version contributed by Rick Gorton <rick.gorton@alpha-processor.com>
9  *    - memory accessed as aligned quadwords only
10  *    - uses cmpbge to compare 8 bytes in parallel
11  *    - does binary search to find 0 byte in last
18  *    - only minimum number of quadwords may be accessed
19  *    - the third argument is an unsigned long
24  *	ftp.digital.com/pub/Digital/info/semiconductor/literature/dsc-library.html
26  *	E	- either cluster
27  *	U	- upper subcluster; U0 - subcluster U0; U1 - subcluster U1
28  *	L	- lower subcluster; L0 - subcluster L0; L1 - subcluster L1
42 	# Hack -- if someone passes in (size_t)-1, hoping to just
45 	# that we will never have a 56-bit address space, cropping
49         ldq_u   $1, 0($16)	# L : load first quadword Latency=3
55         lda     $3, -1($31)	# E : U L L U
65 	ldq_u	$6, -1($5)	# L : L U U L : eight or less bytes to search Latency=3
67 	extqh	$6, $16, $6	# U : 2 cycle stall for $6
79 	srl	$3, $6, $6	# U : $6 = mask of $18 bits set
93 	cttz	$2, $3		# U0 :
94 	addq	$0, $3, $0	# E : All done
102         negq    $2, $3		# E :
103         and     $2, $3, $2	# E :
105         addq    $0, 4, $3	# E :
107         cmoveq  $1, $3, $0	# E : Latency 2, extra map cycle
110         addq    $0, 2, $3	# E : U L U L : 2 cycle stall on $0
112         cmoveq  $1, $3, $0	# E : Latency 2, extra map cycle
115         addq    $0, 1, $3	# E : U L U L : 2 cycle stall on $0
117         cmoveq  $1, $3, $0	# E : Latency 2, extra map cycle
128         insqh   $3, $16, $2	# U : $2 = 0000ffffffffffff ($16<0:2> ff)
147 	subq	$18, $0, $4	# E : $4 <- nr quads to be processed
181 $final:	subq	$5, $0, $18	# E : $18 <- number of bytes left to do