Home
last modified time | relevance | path

Searched +full:csr +full:- +full:offset (Results 1 – 25 of 222) sorted by relevance

123456789

/linux/drivers/usb/musb/
H A Dmusbhsdma.c1 // SPDX-License-Identifier: GPL-2.0
3 * MUSB OTG driver - support for Mentor's DMA controller
6 * Copyright (C) 2005-2007 by Texas Instruments
35 /* control register (16-bit): */
78 struct musb *musb = controller->private_data; in dma_controller_stop()
82 if (controller->used_channels != 0) { in dma_controller_stop()
83 dev_err(musb->controller, in dma_controller_stop()
87 if (controller->used_channels & (1 << bit)) { in dma_controller_stop()
88 channel = &controller->channel[bit].channel; in dma_controller_stop()
91 if (!controller->used_channels) in dma_controller_stop()
[all …]
/linux/arch/arm64/boot/dts/apm/
H A Dapm-storm.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * dts file for AppliedMicro (APM) X-Gene Storm SOC
9 compatible = "apm,xgene-storm";
10 interrupt-parent = <&gic>;
11 #address-cells = <2>;
12 #size-cells = <2>;
15 #address-cells = <2>;
16 #size-cells = <0>;
22 enable-method = "spin-table";
23 cpu-release-addr = <0x1 0x0000fff8>;
[all …]
/linux/arch/alpha/kernel/
H A Dcore_titan.c1 // SPDX-License-Identifier: GPL-2.0
44 * BIOS32-style PCI interface:
60 mk_tig_addr(int offset) in mk_tig_addr() argument
62 return (volatile unsigned long *)(TITAN_TIG_SPACE + (offset << 6)); in mk_tig_addr()
66 titan_read_tig(int offset, u8 value) in titan_read_tig() argument
68 volatile unsigned long *tig_addr = mk_tig_addr(offset); in titan_read_tig()
73 titan_write_tig(int offset, u8 value) in titan_write_tig() argument
75 volatile unsigned long *tig_addr = mk_tig_addr(offset); in titan_write_tig()
89 * Note also that type 1 is determined by non-zero bus number.
95 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
[all …]
H A Dsys_marvel.c1 // SPDX-License-Identifier: GPL-2.0
52 * -----+-----+--------+--- in io7_device_interrupt()
57 * 0x0800 - 0x0ff0 - 0x0800 + (LSI id << 4) in io7_device_interrupt()
58 * 0x1000 - 0x2ff0 - 0x1000 + (MSI_DAT<8:0> << 4) in io7_device_interrupt()
61 irq = ((vector & 0xffff) - 0x800) >> 4; in io7_device_interrupt()
63 irq += 16; /* offset for legacy */ in io7_device_interrupt()
81 "%s for nonexistent io7 -- vec %x, pid %d\n", in io7_get_irq_ctl()
87 irq -= 16; /* subtract legacy bias */ in io7_get_irq_ctl()
91 "%s for invalid irq -- pid %d adjusted irq %x\n", in io7_get_irq_ctl()
96 ctl = &io7->csrs->PO7_LSI_CTL[irq & 0xff].csr; /* assume LSI */ in io7_get_irq_ctl()
[all …]
H A Dcore_marvel.c1 // SPDX-License-Identifier: GPL-2.0
56 read_ev7_csr(int pe, unsigned long offset) in read_ev7_csr() argument
58 ev7_csr *ev7csr = EV7_CSR_KERN(pe, offset); in read_ev7_csr()
62 q = ev7csr->csr; in read_ev7_csr()
69 write_ev7_csr(int pe, unsigned long offset, unsigned long q) in write_ev7_csr() argument
71 ev7_csr *ev7csr = EV7_CSR_KERN(pe, offset); in write_ev7_csr()
74 ev7csr->csr = q; in write_ev7_csr()
96 return (prev ? prev->next : io7_head); in marvel_next_io7()
104 for (io7 = io7_head; io7 && io7->pe != pe; io7 = io7->next) in marvel_find_io7()
123 io7->pe = pe; in alloc_io7()
[all …]
H A Dcore_tsunami.c1 // SPDX-License-Identifier: GPL-2.0
39 * NOTE: Herein lie back-to-back mb instructions. They are magic.
45 * BIOS32-style PCI interface:
66 * Note also that type 1 is determined by non-zero bus number.
72 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
74 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
83 * The function number selects which function of a multi-function device
86 * The register selects a DWORD (32 bit) register offset. Hence it
95 struct pci_controller *hose = pbus->sysdata; in mk_conf_addr()
97 u8 bus = pbus->number; in mk_conf_addr()
[all …]
/linux/arch/x86/include/asm/numachip/
H A Dnumachip_csr.h6 * Numascale NumaConnect-Specific Header file
24 /* 32K CSR space, b15 indicates geo/non-geo */
30 * Local CSR space starts in global CSR space with "nodeid" = 0xfff0, however
36 #define NUMACHIP_LCSR_SIZE (NUMACHIP_LCSR_LIM - NUMACHIP_LCSR_BASE + 1)
39 static inline void *lcsr_address(unsigned long offset) in lcsr_address() argument
42 CSR_NODE_BITS(0xfff0) | (offset & CSR_OFFSET_MASK)); in lcsr_address()
45 static inline unsigned int read_lcsr(unsigned long offset) in read_lcsr() argument
47 return swab32(readl(lcsr_address(offset))); in read_lcsr()
50 static inline void write_lcsr(unsigned long offset, unsigned int val) in write_lcsr() argument
52 writel(swab32(val), lcsr_address(offset)); in write_lcsr()
[all …]
/linux/drivers/net/ethernet/netronome/nfp/nfpcore/
H A Dnfp6000_pcie.c1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 /* Copyright (C) 2015-2018 Netronome Systems, Inc. */
14 * using target, token and offset/size matching. The generic CPP bus
98 #define NFP_PCIE_P2C_FIXED_SIZE(bar) (1 << (bar)->bitsize)
99 #define NFP_PCIE_P2C_BULK_SIZE(bar) (1 << (bar)->bitsize)
100 #define NFP_PCIE_P2C_GENERAL_TARGET_OFFSET(bar, x) ((x) << ((bar)->bitsize - 2))
101 #define NFP_PCIE_P2C_GENERAL_TOKEN_OFFSET(bar, x) ((x) << ((bar)->bitsize - 4))
102 #define NFP_PCIE_P2C_GENERAL_SIZE(bar) (1 << ((bar)->bitsize - 4))
116 * struct nfp_bar - describes BAR configuration and usage
118 * @barcfg: cached contents of BAR config CSR
[all …]
/linux/drivers/net/wireless/ralink/rt2x00/
H A Drt2x00mmio.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
22 const unsigned int offset) in rt2x00mmio_register_read() argument
24 return readl(rt2x00dev->csr.base + offset); in rt2x00mmio_register_read()
28 const unsigned int offset, in rt2x00mmio_register_multiread() argument
31 memcpy_fromio(value, rt2x00dev->csr.base + offset, length); in rt2x00mmio_register_multiread()
35 const unsigned int offset, in rt2x00mmio_register_write() argument
38 writel(value, rt2x00dev->csr.base + offset); in rt2x00mmio_register_write()
42 const unsigned int offset, in rt2x00mmio_register_multiwrite() argument
46 __iowrite32_copy(rt2x00dev->csr.base + offset, value, length >> 2); in rt2x00mmio_register_multiwrite()
[all …]
H A Drt2x00pci.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
13 #include <linux/dma-mapping.h>
27 kfree(rt2x00dev->rf); in rt2x00pci_free_reg()
28 rt2x00dev->rf = NULL; in rt2x00pci_free_reg()
30 kfree(rt2x00dev->eeprom); in rt2x00pci_free_reg()
31 rt2x00dev->eeprom = NULL; in rt2x00pci_free_reg()
33 if (rt2x00dev->csr.base) { in rt2x00pci_free_reg()
34 iounmap(rt2x00dev->csr.base); in rt2x00pci_free_reg()
35 rt2x00dev->csr.base = NULL; in rt2x00pci_free_reg()
[all …]
/linux/arch/arm/mach-omap1/
H A Domap-dma.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/arch/arm/plat-omap/dma.c
5 * Copyright (C) 2003 - 2008 Nokia Corporation
10 * OMAP2/3 support Copyright (C) 2004-2007 Texas Instruments, Inc.
12 * Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc.
15 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
19 * Copyright (C) 2010 Texas Instruments Incorporated - https://www.ti.com/
21 * - G, Manjunath Kondaiah <manjugk@ti.com>
35 #include <linux/omap-dma.h>
37 #include <linux/soc/ti/omap1-io.h>
[all …]
/linux/drivers/crypto/intel/qat/qat_common/
H A Dadf_gen2_pfvf.c1 // SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0-only)
56 /* Enable VF2PF Messaging Ints - VFs 0 through 15 per vf_mask[15:0] */ in adf_gen2_enable_vf2pf_interrupts()
95 * To work around it, disable all and re-enable only the sources that in adf_gen2_disable_pending_vf2pf_interrupts()
96 * are not in vf_mask and were not already disabled. Re-enabling will in adf_gen2_disable_pending_vf2pf_interrupts()
112 static u32 gen2_csr_get_int_bit(enum gen2_csr_pos offset) in gen2_csr_get_int_bit() argument
114 return ADF_PFVF_INT << offset; in gen2_csr_get_int_bit()
117 static u32 gen2_csr_msg_to_position(u32 csr_msg, enum gen2_csr_pos offset) in gen2_csr_msg_to_position() argument
119 return (csr_msg & 0xFFFF) << offset; in gen2_csr_msg_to_position()
122 static u32 gen2_csr_msg_from_position(u32 csr_val, enum gen2_csr_pos offset) in gen2_csr_msg_from_position() argument
124 return (csr_val >> offset) & 0xFFFF; in gen2_csr_msg_from_position()
[all …]
/linux/drivers/dma/stm32/
H A Dstm32-dma3.c1 // SPDX-License-Identifier: GPL-2.0-only
11 #include <linux/dma-mapping.h>
24 #include "../virt-dma.h"
56 /* MISR DMA non-secure/secure masked interrupt status register */
140 CTR1_PAM_0S_LT, /* if DDW > SDW, padded with 0s else left-truncated */
141 CTR1_PAM_SE_RT, /* if DDW > SDW, sign extended else right-truncated */
163 /* CxLLR DMA channel x linked-list address register */
192 AXI64, /* 1x AXI: 64-bit port 0 */
193 AHB32, /* 1x AHB: 32-bit port 0 */
194 AHB32_AHB32, /* 2x AHB: 32-bit port 0 and 32-bit port 1 */
[all …]
/linux/arch/mips/dec/
H A Dkn01-berr.c1 // SPDX-License-Identifier: GPL-2.0-or-later
36 * Bits 7:0 of the Control Register are write-only -- the
41 * There is no default value -- it has to be initialized.
49 volatile u16 *csr = (void *)CKSEG1ADDR(KN01_SLOT_BASE + KN01_CSR); in dec_kn01_be_ack() local
54 *csr = cached_kn01_csr | KN01_CSR_MEMERR; /* Clear bus IRQ. */ in dec_kn01_be_ack()
74 int data = regs->cp0_cause & 4; in dec_kn01_be_backend()
75 unsigned int __user *pc = (unsigned int __user *)regs->cp0_epc + in dec_kn01_be_backend()
76 ((regs->cp0_cause & CAUSEF_BD) != 0); in dec_kn01_be_backend()
78 unsigned long entrylo, offset; in dec_kn01_be_backend() local
101 vaddr = regs->regs[insn.i_format.rs] + in dec_kn01_be_backend()
[all …]
/linux/arch/alpha/include/asm/
H A Dcore_t2.h1 /* SPDX-License-Identifier: GPL-2.0 */
14 * memory controller and PCI access for the SABLE-based systems.
27 /* GAMMA-SABLE is a SABLE with EV5-based CPUs */
87 /* T2 CSRs are in the non-cachable primary IO space from 3.8000.0000 to
90 * +--------------+ 3 8000 0000
92 * +--------------+ 3 8100 0000
94 * +--------------+ 3 8200 0000
96 * +--------------+ 3 8300 0000
98 * +--------------+ 3 8400 0000
100 * +--------------+ 3 8700 0000
[all …]
/linux/drivers/tty/serial/
H A Drsci.c1 // SPDX-License-Identifier: GPL-2.0
28 #define CSR 0x48 macro
58 #define CCR1_SHARPS BIT(20) /* Half -duplex Communication Select */
76 /* CSR (Common Status Register) */
90 #define SCxSR_ERRORS(port) (to_sci_port(port)->params->error_mask)
91 #define SCxSR_ERROR_CLEAR(port) (to_sci_port(port)->params->error_clear)
124 static u32 rsci_serial_in(struct uart_port *p, int offset) in rsci_serial_in() argument
126 return readl(p->membase + offset); in rsci_serial_in()
129 static void rsci_serial_out(struct uart_port *p, int offset, int value) in rsci_serial_out() argument
131 writel(value, p->membase + offset); in rsci_serial_out()
[all …]
/linux/drivers/net/ethernet/meta/fbnic/
H A Dfbnic_csr.h1 /* SPDX-License-Identifier: GPL-2.0 */
43 /* Length, Type, Offset Masks and Shifts */
125 (FBNIC_BD_DESC_ADDR_MASK & ~(FBNIC_BD_DESC_ADDR_MASK - 1))
152 #define FBNIC_RCD_AL_BUFF_FRAG_MASK (FBNIC_BD_FRAG_COUNT - 1)
211 #define FBNIC_CSR_START_INTR 0x00000 /* CSR section delimiter */
236 #define FBNIC_CSR_END_INTR 0x0005f /* CSR section delimiter */
239 #define FBNIC_CSR_START_INTR_CQ 0x00400 /* CSR section delimiter */
256 #define FBNIC_CSR_END_INTR_CQ 0x007fe /* CSR section delimiter */
259 #define FBNIC_CSR_START_QM_TX 0x00800 /* CSR section delimiter */
309 #define FBNIC_CSR_END_QM_TX 0x00873 /* CSR section delimiter */
[all …]
/linux/drivers/misc/eeprom/
H A Didt_89hpesx.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2016 T-Platforms. All Rights Reserved.
5 * IDT PCIe-switch NTB Linux driver
8 * Serge Semin <fancer.lancer@gmail.com>, <Sergey.Semin@t-platforms.ru>
11 * NOTE of the IDT 89HPESx SMBus-slave interface driver
13 * IDT PCIe-switches. IDT provides a simple SMBus interface to perform IO-
16 * binary sysfs-file in the device directory:
17 * /sys/bus/i2c/devices/<bus>-<devaddr>/eeprom
18 * In case if read-only flag is specified in the dts-node of device desription,
19 * User-space applications won't be able to write to the EEPROM sysfs-node.
[all …]
/linux/drivers/hid/intel-ish-hid/ipc/
H A Dipc.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (c) 2014-2016, Intel Corporation.
8 #include <linux/devm-helpers.h>
14 #include "hw-ish.h"
22 * ish_reg_read() - Read register
24 * @offset: Register offset
26 * Read 32 bit register at a given offset
31 unsigned long offset) in ish_reg_read() argument
35 return readl(hw->mem_addr + offset); in ish_reg_read()
39 * ish_reg_write() - Write register
[all …]
/linux/drivers/staging/vme_user/
H A Dvme_tsi148.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
50 * Layout of a DMAC Linked-List Descriptor
53 * correctly laid out - It must also be aligned on 64-bit boundaries.
70 * The descriptor needs to be aligned on a 64-bit boundary, we increase
83 * PCFS - PCI Configuration Space Registers
84 * LCSR - Local Control and Status Registers
85 * GCSR - Global Control and Status Registers
86 * CR/CSR - Subset of Configuration ROM /
209 * offset 0x200
226 * offset 0x220
[all …]
/linux/sound/soc/intel/atom/sst/
H A Dsst_loader.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * sst_dsp.c - Intel SST Driver for audio engine
5 * Copyright (C) 2008-14 Intel Corp
29 #include "../sst-mfld-platform.h"
34 /* __iowrite32_copy uses 32-bit count values so divide by 4 for in memcpy32_toio()
42 /* __ioread32_copy uses 32-bit count values so divide by 4 for in memcpy32_fromio()
49 * intel_sst_reset_dsp_mrfld - Resetting SST DSP
56 union config_status_reg_mrfld csr; in intel_sst_reset_dsp_mrfld() local
58 dev_dbg(sst_drv_ctx->dev, "sst: Resetting the DSP in mrfld\n"); in intel_sst_reset_dsp_mrfld()
59 csr.full = sst_shim_read64(sst_drv_ctx->shim, SST_CSR); in intel_sst_reset_dsp_mrfld()
[all …]
/linux/drivers/pci/controller/
H A Dpci-xgene.c1 // SPDX-License-Identifier: GPL-2.0+
3 * APM X-Gene PCIe Driver
20 #include <linux/pci-acpi.h>
21 #include <linux/pci-ecam.h>
73 return readl(port->csr_base + reg); in xgene_pcie_readl()
78 writel(val, port->csr_base + reg); in xgene_pcie_writel()
91 return (struct xgene_pcie *)(bus->sysdata); in pcie_bus_to_port()
93 cfg = bus->sysdata; in pcie_bus_to_port()
94 return (struct xgene_pcie *)(cfg->priv); in pcie_bus_to_port()
105 if (bus->number >= (bus->primary + 1)) in xgene_pcie_get_cfg_base()
[all …]
/linux/arch/mips/kernel/
H A Dsignal.c7 * Copyright (C) 1994 - 2000 Ralf Baechle
37 #include <asm/cpu-features.h>
43 #include "signal-common.h"
73 struct mips_abi *abi = current->thread.abi; in copy_fp_to_sigcontext()
74 uint64_t __user *fpregs = sc + abi->off_sc_fpregs; in copy_fp_to_sigcontext()
75 uint32_t __user *csr = sc + abi->off_sc_fpc_csr; in copy_fp_to_sigcontext() local
82 __put_user(get_fpr64(&current->thread.fpu.fpr[i], 0), in copy_fp_to_sigcontext()
85 err |= __put_user(current->thread.fpu.fcr31, csr); in copy_fp_to_sigcontext()
92 struct mips_abi *abi = current->thread.abi; in copy_fp_from_sigcontext()
93 uint64_t __user *fpregs = sc + abi->off_sc_fpregs; in copy_fp_from_sigcontext()
[all …]
/linux/drivers/net/ethernet/marvell/octeontx2/af/
H A Dlmac_common.h1 /* SPDX-License-Identifier: GPL-2.0 */
14 * struct lmac - per lmac locks and properties
58 * bar offset for example
70 /* lmac offset is different is RPM */
79 /* Unlike CN10K which shares same CSR offset with CGX
80 * CNF10KB has different csr offset
167 void cgx_write(struct cgx *cgx, u64 lmac, u64 offset, u64 val);
168 u64 cgx_read(struct cgx *cgx, u64 lmac, u64 offset);
/linux/include/linux/
H A Drio_regs.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
60 #define RIO_SRC_OPS_STREAM_WRITE 0x00002000 /* [I] Str-write op */
69 #define RIO_SRC_OPS_PORT_WRITE 0x00000004 /* [I] Port-write op */
74 #define RIO_DST_OPS_STREAM_WRITE 0x00002000 /* [I] Str-write op */
83 #define RIO_DST_OPS_PORT_WRITE 0x00000004 /* [I] Port-write op */
87 #define RIO_OPS_STREAM_WRITE 0x00002000 /* [I] Str-write op */
96 #define RIO_OPS_PORT_WRITE 0x00000004 /* [I] Port-write op */
98 /* 0x20-0x30 *//* Reserved */
103 #define RIO_MBOX_CSR 0x40 /* [II, <= 1.2] Mailbox CSR */
129 #define RIO_WRITE_PORT_CSR 0x44 /* [I, <= 1.2] Write Port CSR */
[all …]

123456789