Lines Matching +full:csr +full:- +full:offset
1 // SPDX-License-Identifier: GPL-2.0
55 * Need SMP-safe access to interrupt CSRs
83 dim0 = &cchip->dim0.csr; in titan_update_irq_hw()
84 dim1 = &cchip->dim1.csr; in titan_update_irq_hw()
85 dim2 = &cchip->dim2.csr; in titan_update_irq_hw()
86 dim3 = &cchip->dim3.csr; in titan_update_irq_hw()
103 dimB = &cchip->dim0.csr; in titan_update_irq_hw()
104 if (bcpu == 1) dimB = &cchip->dim1.csr; in titan_update_irq_hw()
105 else if (bcpu == 2) dimB = &cchip->dim2.csr; in titan_update_irq_hw()
106 else if (bcpu == 3) dimB = &cchip->dim3.csr; in titan_update_irq_hw()
117 unsigned int irq = d->irq; in titan_enable_irq()
119 titan_cached_irq_mask |= 1UL << (irq - 16); in titan_enable_irq()
127 unsigned int irq = d->irq; in titan_disable_irq()
129 titan_cached_irq_mask &= ~(1UL << (irq - 16)); in titan_disable_irq()
152 unsigned int irq = d->irq; in titan_set_irq_affinity()
154 titan_cpu_set_irq_affinity(irq - 16, *affinity); in titan_set_irq_affinity()
172 irq = (vector - 0x800) >> 4; in titan_srm_device_interrupt()
200 * event counting -- just return. in titan_intr_nop()
248 /* convert to SRM vector... priority is <63> -> <0> */ in titan_dispatch_irqs()
249 vector = 63 - __kernel_ctlz(mask); in titan_dispatch_irqs()
320 /* Offset by 16 to make room for ISA interrupts 0 - 15. */ in titan_map_irq()