1 // SPDX-License-Identifier: GPL-2.0-or-later
36  * Bits 7:0 of the Control Register are write-only -- the
41  * There is no default value -- it has to be initialized.
49 	volatile u16 *csr = (void *)CKSEG1ADDR(KN01_SLOT_BASE + KN01_CSR);  in dec_kn01_be_ack()  local
54 	*csr = cached_kn01_csr | KN01_CSR_MEMERR;	/* Clear bus IRQ. */  in dec_kn01_be_ack()
74 	int data = regs->cp0_cause & 4;  in dec_kn01_be_backend()
75 	unsigned int __user *pc = (unsigned int __user *)regs->cp0_epc +  in dec_kn01_be_backend()
76 				  ((regs->cp0_cause & CAUSEF_BD) != 0);  in dec_kn01_be_backend()
78 	unsigned long entrylo, offset;  in dec_kn01_be_backend()  local
101 			vaddr = regs->regs[insn.i_format.rs] +  in dec_kn01_be_backend()
110 			entryhi = asid & (PAGE_SIZE - 1);  in dec_kn01_be_backend()
111 			entryhi |= vaddr & ~(PAGE_SIZE - 1);  in dec_kn01_be_backend()
119 			offset = vaddr & (PAGE_SIZE - 1);  in dec_kn01_be_backend()
120 			address = (entrylo & ~(PAGE_SIZE - 1)) | offset;  in dec_kn01_be_backend()
124 	/* Treat low 256MB as memory, high -- as I/O. */  in dec_kn01_be_backend()
150 	volatile u16 *csr = (void *)CKSEG1ADDR(KN01_SLOT_BASE + KN01_CSR);  in dec_kn01_be_interrupt()  local
154 	if (!(*csr & KN01_CSR_MEMERR))  in dec_kn01_be_interrupt()
170 	       regs->cp0_epc, regs->regs[31]);  in dec_kn01_be_interrupt()
177 	volatile u16 *csr = (void *)CKSEG1ADDR(KN01_SLOT_BASE + KN01_CSR);  in dec_kn01_be_init()  local
182 	/* Preset write-only bits of the Control Register cache. */  in dec_kn01_be_init()
183 	cached_kn01_csr = *csr;  in dec_kn01_be_init()
189 	*csr = cached_kn01_csr;  in dec_kn01_be_init()