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/freebsd/sys/dev/qat/qat_hw/qat_200xx/
H A Dadf_200xx_hw_data.c1 /* SPDX-License-Identifier: BSD-3-Clause */
2 /* Copyright(c) 2007-2022 Intel Corporation */
30 device_t pdev = accel_dev->accel_pci_dev.pci_dev; in get_accel_mask()
45 device_t pdev = accel_dev->accel_pci_dev.pci_dev; in get_ae_mask()
73 if (!self || !self->accel_mask) in get_num_accels()
77 if (self->accel_mask & (1 << i)) in get_num_accels()
88 if (!self || !self->ae_mask) in get_num_aes()
92 if (self->ae_mask & (1 << i)) in get_num_aes()
132 struct adf_hw_device_data *hw_device = accel_dev->hw_device; in adf_get_arbiter_mapping()
136 if (hw_device->ae_mask & (1 << i)) in adf_get_arbiter_mapping()
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/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Dxgene.txt1 Device Tree Clock bindings for APM X-Gene
5 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
8 - compatible : shall be one of the following:
9 "apm,xgene-socpll-clock" - for a X-Gene SoC PLL clock
10 "apm,xgene-pcppll-clock" - for a X-Gene PCP PLL clock
11 "apm,xgene-pmd-clock" - for a X-Gene PMD clock
12 "apm,xgene-device-clock" - for a X-Gene device clock
13 "apm,xgene-socpll-v2-clock" - for a X-Gene SoC PLL v2 clock
14 "apm,xgene-pcppll-v2-clock" - for a X-Gene PCP PLL v2 clock
17 - reg : shall be the physical PLL register address for the pll clock.
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H A Dapm,xgene-device-clock.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/apm,xgene-device-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: APM X-Gene SoC device clocks
10 - Khuong Dinh <khuong@os.amperecomputing.com>
14 const: apm,xgene-device-clock
20 reg-names:
22 - enum: [ csr-reg, div-reg ]
23 - const: div-reg
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/freebsd/sys/contrib/device-tree/src/arm64/apm/
H A Dapm-storm.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * dts file for AppliedMicro (APM) X-Gene Storm SOC
9 compatible = "apm,xgene-storm";
10 interrupt-parent = <&gic>;
11 #address-cells = <2>;
12 #size-cells = <2>;
15 #address-cells = <2>;
16 #size-cells = <0>;
22 enable-method = "spin-table";
23 cpu-release-addr = <0x1 0x0000fff8>;
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H A Dapm-shadowcat.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * dts file for AppliedMicro (APM) X-Gene Shadowcat SOC
9 compatible = "apm,xgene-shadowcat";
10 interrupt-parent = <&gic>;
11 #address-cells = <2>;
12 #size-cells = <2>;
15 #address-cells = <2>;
16 #size-cells = <0>;
22 enable-method = "spin-table";
23 cpu-release-addr = <0x1 0x0000fff8>;
[all …]
/freebsd/sys/dev/qat/qat_common/
H A Dadf_hw_arbiter.c1 /* SPDX-License-Identifier: BSD-3-Clause */
2 /* Copyright(c) 2007-2022 Intel Corporation */
51 struct adf_hw_device_data *hw_data = accel_dev->hw_device; in adf_init_arb()
53 struct resource *csr = accel_dev->transport->banks[0].csr_addr; in adf_init_arb() local
57 hw_data->get_arb_info(&info); in adf_init_arb()
63 WRITE_CSR_ARB_SARCONFIG(csr, info.arbiter_offset, arb, arb_cfg); in adf_init_arb()
71 struct adf_hw_device_data *hw_data = accel_dev->hw_device; in adf_init_gen2_arb()
73 struct resource *csr = accel_dev->transport->banks[0].csr_addr; in adf_init_gen2_arb() local
80 hw_data->get_arb_info(&info); in adf_init_gen2_arb()
83 hw_data->get_arb_mapping(accel_dev, &thd_2_arb_cfg); in adf_init_gen2_arb()
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H A Dadf_dev_err.c1 /* SPDX-License-Identifier: BSD-3-Clause */
2 /* Copyright(c) 2007-2022 Intel Corporation */
162 sizeof(adf_printf_buf) - adf_printf_len, in adf_print_reg()
175 struct adf_hw_device_data *hw_data = accel_dev->hw_device; in adf_print_err_registers()
177 &GET_BARS(accel_dev)[hw_data->get_misc_bar_id(hw_data)]; in adf_print_err_registers()
178 struct resource *csr = misc_bar->virt_addr; in adf_print_err_registers() local
180 unsigned int mask; in adf_print_err_registers() local
184 val = ADF_CSR_RD(csr, adf_err_regs[i].offs); in adf_print_err_registers()
192 for (accel = 0, mask = hw_data->accel_mask; mask; in adf_print_err_registers()
193 accel++, mask >>= 1) { in adf_print_err_registers()
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H A Dqat_hal.c1 /* SPDX-License-Identifier: BSD-3-Clause */
2 /* Copyright(c) 2007-2025 Intel Corporation */
44 #define AE(handle, ae) ((handle)->hal_handle->aes[ae])
112 unsigned int csr, in qat_hal_rd_ae_csr() argument
118 *value = GET_AE_CSR(handle, ae, csr); in qat_hal_rd_ae_csr()
121 } while (iterations--); in qat_hal_rd_ae_csr()
123 pr_err("QAT: Read CSR timeout\n"); in qat_hal_rd_ae_csr()
130 unsigned int csr, in qat_hal_wr_ae_csr() argument
136 SET_AE_CSR(handle, ae, csr, value); in qat_hal_wr_ae_csr()
139 } while (iterations--); in qat_hal_wr_ae_csr()
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/freebsd/sys/dev/qat/qat_hw/qat_c3xxx/
H A Dadf_c3xxx_hw_data.c1 /* SPDX-License-Identifier: BSD-3-Clause */
2 /* Copyright(c) 2007-2022 Intel Corporation */
29 device_t pdev = accel_dev->accel_pci_dev.pci_dev; in get_accel_mask()
44 device_t pdev = accel_dev->accel_pci_dev.pci_dev; in get_ae_mask()
72 if (!self || !self->accel_mask) in get_num_accels()
76 if (self->accel_mask & (1 << i)) in get_num_accels()
87 if (!self || !self->ae_mask) in get_num_aes()
91 if (self->ae_mask & (1 << i)) in get_num_aes()
131 struct adf_hw_device_data *hw_device = accel_dev->hw_device; in adf_get_arbiter_mapping()
135 if (hw_device->ae_mask & (1 << i)) in adf_get_arbiter_mapping()
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/freebsd/sys/dev/qat/qat_hw/qat_c62x/
H A Dadf_c62x_hw_data.c1 /* SPDX-License-Identifier: BSD-3-Clause */
2 /* Copyright(c) 2007-2022 Intel Corporation */
31 device_t pdev = accel_dev->accel_pci_dev.pci_dev; in get_accel_mask()
46 device_t pdev = accel_dev->accel_pci_dev.pci_dev; in get_ae_mask()
74 if (!self || !self->accel_mask) in get_num_accels()
78 if (self->accel_mask & (1 << i)) in get_num_accels()
89 if (!self || !self->ae_mask) in get_num_aes()
93 if (self->ae_mask & (1 << i)) in get_num_aes()
135 struct adf_hw_device_data *hw_device = accel_dev->hw_device; in adf_get_arbiter_mapping()
139 if (hw_device->ae_mask & (1 << i)) in adf_get_arbiter_mapping()
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/freebsd/sys/dev/qat/qat_hw/qat_dh895xcc/
H A Dadf_dh895xcc_hw_data.c1 /* SPDX-License-Identifier: BSD-3-Clause */
2 /* Copyright(c) 2007-2022 Intel Corporation */
36 device_t pdev = accel_dev->accel_pci_dev.pci_dev; in get_accel_mask()
48 device_t pdev = accel_dev->accel_pci_dev.pci_dev; in get_ae_mask()
61 if (!self || !self->accel_mask) in get_num_accels()
65 if (self->accel_mask & (1 << i)) in get_num_accels()
76 if (!self || !self->ae_mask) in get_num_aes()
80 if (self->ae_mask & (1 << i)) in get_num_aes()
107 int sku = (self->fuses & ADF_DH895XCC_FUSECTL_SKU_MASK) >> in get_sku()
129 switch (accel_dev->accel_pci_dev.sku) { in adf_get_arbiter_mapping()
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/freebsd/sys/dev/qat/include/common/
H A Dadf_accel_devices.h1 /* SPDX-License-Identifier: BSD-3-Clause */
2 /* Copyright(c) 2007-2025 Intel Corporation */
64 BIT((vf_nr_)-ADF_VF2PF_SET_SIZE *ADF_VF2PF_VFNR_TO_SET( \
98 #define GET_CSR_OPS(accel_dev) (&(accel_dev)->hw_device->csr_info.csr_ops)
99 #define GET_PFVF_OPS(accel_dev) (&(accel_dev)->hw_device->csr_info.pfvf_ops)
216 /* Inline Egress mask. "1" = AE is working with egress traffic */
220 /* Initialise CY AE mask, "1" = AE is used for CY operations */
222 /* Initialise DC AE mask, "1" = AE is used for DC operations */
233 * in ARAM (device's on-chip memory).
470 /* helper enum for performing CSR operations */
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/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonGenExtract.cpp1 //===- HexagonGenExtract.cpp ----------------------------------------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
33 static cl::opt<unsigned> ExtractCutoff("extract-cutoff", cl::init(~0U),
38 // One of the reasons for "extract" is to put a sequence of bits in a regis-
40 // "insert"). If the bits are already at offset 0, it is better not to gene-
43 static cl::opt<bool> NoSR0("extract-nosr0", cl::init(true), cl::Hidden,
46 static cl::opt<bool> NeedAnd("extract-needand", cl::init(true), cl::Hidden,
100 ConstantInt *CSL = nullptr, *CSR = nullptr, *CM = nullptr; in INITIALIZE_PASS_DEPENDENCY() local
101 BasicBlock *BB = In->getParent(); in INITIALIZE_PASS_DEPENDENCY()
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/freebsd/sys/contrib/device-tree/Bindings/pci/
H A Dmediatek-pcie-gen3.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/mediatek-pcie-gen3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jianjun Wang <jianjun.wang@mediatek.com>
19 +-----+
21 +-----+
24 port->irq
26 +-+-+-+-+-+-+-+-+
28 +-+-+-+-+-+-+-+-+
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H A Dxgene-pci.txt1 * AppliedMicro X-Gene PCIe interface
4 - device_type: set to "pci"
5 - compatible: should contain "apm,xgene-pcie" to identify the core.
6 - reg: A list of physical base address and length for each set of controller
7 registers. Must contain an entry for each entry in the reg-names
9 - reg-names: Must include the following entries:
10 "csr": controller configuration registers.
12 - #address-cells: set to <3>
13 - #size-cells: set to <2>
14 - ranges: ranges for the outbound memory, I/O regions.
[all …]
H A Dapm,xgene-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/apm,xgene-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: AppliedMicro X-Gene PCIe interface
10 - Toan Le <toan@os.amperecomputing.com>
13 - $ref: /schemas/pci/pci-host-bridge.yaml#
18 - items:
19 - const: apm,xgene-storm-pcie
20 - const: apm,xgene-pcie
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/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchISelLowering.h1 //=- LoongArchISelLowering.h - LoongArch DAG Lowering Interface -*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
37 // 32-bit shifts, directly matching the semantics of the named LoongArch
46 // unsigned 32-bit integer division
50 // FPR<->GPR transfer operations
65 // Byte-swapping and bit-reversal
91 // Write new value to CSR and return old value.
94 // Operand 2: The address of the required CSR.
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/freebsd/sys/dev/qat/qat_hw/qat_c4xxx/
H A Dadf_c4xxx_hw_data.h1 /* SPDX-License-Identifier: BSD-3-Clause */
2 /* Copyright(c) 2007-2022 Intel Corporation */
98 /* Error source mask registers */
127 /* Return interrupt accelerator source mask */
178 /* AEx Correctable Error Mask in ERRMSK8 */
188 * AEx Uncorrectable Error Mask in ERRMSK9
189 * CPP Command Parity Errors Mask in ERRMSK9
190 * RI Memory Parity Errors Mask in ERRMSK9
191 * TI Memory Parity Errors Mask in ERRMSK9
209 * CSR name: hicppagentcmdparerrlog
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H A Dadf_c4xxx_hw_data.c1 /* SPDX-License-Identifier: BSD-3-Clause */
2 /* Copyright(c) 2007-2025 Intel Corporation */
132 device_t pdev = accel_dev->accel_pci_dev.pci_dev; in get_accel_mask()
146 device_t pdev = accel_dev->accel_pci_dev.pci_dev; in get_ae_mask()
155 * checks against the AU mask are performed in get_ae_mask()
163 return self ? hweight32(self->accel_mask) : 0; in get_num_accels()
169 return self ? hweight32(self->ae_mask) : 0; in get_num_aes()
198 * c4xxx_set_ssm_wdtimer() - Initialize the slice hang watchdog timer.
206 struct adf_hw_device_data *hw_device = accel_dev->hw_device; in c4xxx_set_ssm_wdtimer()
208 &GET_BARS(accel_dev)[hw_device->get_misc_bar_id(hw_device)]; in c4xxx_set_ssm_wdtimer()
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DLivePhysRegs.cpp1 //===--- LivePhysRegs.cpp - Live Physical Register Set --------------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
13 //===----------------------------------------------------------------------===//
21 #include "llvm/Config/llvm-config.h"
28 /// mask.
37 Clobbers->push_back(std::make_pair(*LRI, &MO)); in removeRegsInMask()
77 /// killed-uses, add defs. This is the not recommended way, because it depends
84 if (O->isReg()) { in stepForward()
85 if (O->isDebug()) in stepForward()
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/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.h1 //===-- RISCVISelLowering.h - RISC-V DAG Lowering Interface -----*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file defines the interfaces that RISC-V uses to lower LLVM code into a
12 //===----------------------------------------------------------------------===//
30 // clang-format off
37 /// Select with condition operator - This selects between a true value and
57 // Selected as PseudoAddTPRel. Used to emit a TP-relative relocation.
68 // RV64I shifts, directly matching the semantics of the named RISC-V
73 // 32-bit operations from RV64M that can't be simply matched with a pattern
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H A DRISCVInstrInfo.td1 //===-- RISCVInstrInfo.td - Target Description for RISC-V --*- tablegen -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file describes the RISC-V instructions in TableGen format.
11 //===----------------------------------------------------------------------===//
13 //===----------------------------------------------------------------------===//
14 // RISC-V specific DAG Nodes.
15 //===----------------------------------------------------------------------===//
17 // Target-independent type requirements, but with target-specific formats.
23 // Target-dependent type requirements.
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/freebsd/sys/dev/iicbus/rtc/
H A Dnxprtc.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
30 * Driver for NXP real-time clock/calendar chips:
31 * - PCF8563 = low power, countdown timer
32 * - PCA8565 = like PCF8563, automotive temperature range
33 * - PCF8523 = low power, countdown timer, oscillator freq tuning, 2 timers
34 * - PCF2127 = like PCF8523, industrial, tcxo, tamper/ts, i2c & spi, 512B ram
35 * - PCA2129 = like PCF8523, automotive, tcxo, tamper/ts, i2c & spi, (note 1)
36 * - PCF2129 = like PCF8523, industrial, tcxo, tamper/ts, i2c & spi, (note 1)
100 * PCF2127-specific registers, bits, and masks.
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/freebsd/sys/dev/ppc/
H A Dppc.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 1997-2000 Nicolas Souchu
5 * Copyright (c) 2001 Alcove - Nicolas Souchu
92 "SMC-like", "SMC FDC37C665GT", "SMC FDC37C666GT", "PC87332", "PC87306",
99 "COMPATIBLE", "NIBBLE-only", "PS2-only", "PS2/NIBBLE", "EPP-only",
100 "EPP/NIBBLE", "EPP/PS2", "EPP/PS2/NIBBLE", "ECP-only",
119 * BIOS printer list - used by BIOS probe.
136 if (!(ppc->ppc_avm & PPB_ECP) && !(ppc->ppc_dtm & PPB_ECP)) in ppc_ecp_sync()
174 /* read PWord size - transfers in FIFO mode must be PWord aligned */ in ppc_detect_fifo()
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/freebsd/sys/contrib/device-tree/src/arm64/airoha/
H A Den7581.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 #include <dt-bindings/interrupt-controller/irq.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/clock/en7523-clk.h>
6 #include <dt-bindings/reset/airoha,en7581-reset.h>
9 interrupt-parent = <&gic>;
10 #address-cells = <2>;
11 #size-cells = <2>;
13 reserved-memory {
14 #address-cells = <2>;
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