1*c66ec88fSEmmanuel Vadot* AppliedMicro X-Gene PCIe interface 2*c66ec88fSEmmanuel Vadot 3*c66ec88fSEmmanuel VadotRequired properties: 4*c66ec88fSEmmanuel Vadot- device_type: set to "pci" 5*c66ec88fSEmmanuel Vadot- compatible: should contain "apm,xgene-pcie" to identify the core. 6*c66ec88fSEmmanuel Vadot- reg: A list of physical base address and length for each set of controller 7*c66ec88fSEmmanuel Vadot registers. Must contain an entry for each entry in the reg-names 8*c66ec88fSEmmanuel Vadot property. 9*c66ec88fSEmmanuel Vadot- reg-names: Must include the following entries: 10*c66ec88fSEmmanuel Vadot "csr": controller configuration registers. 11*c66ec88fSEmmanuel Vadot "cfg": PCIe configuration space registers. 12*c66ec88fSEmmanuel Vadot- #address-cells: set to <3> 13*c66ec88fSEmmanuel Vadot- #size-cells: set to <2> 14*c66ec88fSEmmanuel Vadot- ranges: ranges for the outbound memory, I/O regions. 15*c66ec88fSEmmanuel Vadot- dma-ranges: ranges for the inbound memory regions. 16*c66ec88fSEmmanuel Vadot- #interrupt-cells: set to <1> 17*c66ec88fSEmmanuel Vadot- interrupt-map-mask and interrupt-map: standard PCI properties 18*c66ec88fSEmmanuel Vadot to define the mapping of the PCIe interface to interrupt 19*c66ec88fSEmmanuel Vadot numbers. 20*c66ec88fSEmmanuel Vadot- clocks: from common clock binding: handle to pci clock. 21*c66ec88fSEmmanuel Vadot 22*c66ec88fSEmmanuel VadotOptional properties: 23*c66ec88fSEmmanuel Vadot- status: Either "ok" or "disabled". 24*c66ec88fSEmmanuel Vadot- dma-coherent: Present if DMA operations are coherent 25*c66ec88fSEmmanuel Vadot 26*c66ec88fSEmmanuel VadotExample: 27*c66ec88fSEmmanuel Vadot 28*c66ec88fSEmmanuel Vadot pcie0: pcie@1f2b0000 { 29*c66ec88fSEmmanuel Vadot status = "disabled"; 30*c66ec88fSEmmanuel Vadot device_type = "pci"; 31*c66ec88fSEmmanuel Vadot compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie"; 32*c66ec88fSEmmanuel Vadot #interrupt-cells = <1>; 33*c66ec88fSEmmanuel Vadot #size-cells = <2>; 34*c66ec88fSEmmanuel Vadot #address-cells = <3>; 35*c66ec88fSEmmanuel Vadot reg = < 0x00 0x1f2b0000 0x0 0x00010000 /* Controller registers */ 36*c66ec88fSEmmanuel Vadot 0xe0 0xd0000000 0x0 0x00040000>; /* PCI config space */ 37*c66ec88fSEmmanuel Vadot reg-names = "csr", "cfg"; 38*c66ec88fSEmmanuel Vadot ranges = <0x01000000 0x00 0x00000000 0xe0 0x10000000 0x00 0x00010000 /* io */ 39*c66ec88fSEmmanuel Vadot 0x02000000 0x00 0x80000000 0xe1 0x80000000 0x00 0x80000000>; /* mem */ 40*c66ec88fSEmmanuel Vadot dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000 41*c66ec88fSEmmanuel Vadot 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; 42*c66ec88fSEmmanuel Vadot interrupt-map-mask = <0x0 0x0 0x0 0x7>; 43*c66ec88fSEmmanuel Vadot interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc2 0x1 44*c66ec88fSEmmanuel Vadot 0x0 0x0 0x0 0x2 &gic 0x0 0xc3 0x1 45*c66ec88fSEmmanuel Vadot 0x0 0x0 0x0 0x3 &gic 0x0 0xc4 0x1 46*c66ec88fSEmmanuel Vadot 0x0 0x0 0x0 0x4 &gic 0x0 0xc5 0x1>; 47*c66ec88fSEmmanuel Vadot dma-coherent; 48*c66ec88fSEmmanuel Vadot clocks = <&pcie0clk 0>; 49*c66ec88fSEmmanuel Vadot }; 50*c66ec88fSEmmanuel Vadot 51