Lines Matching +full:csr +full:- +full:mask
1 //===-- RISCVInstrInfo.td - Target Description for RISC-V --*- tablegen -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file describes the RISC-V instructions in TableGen format.
11 //===----------------------------------------------------------------------===//
13 //===----------------------------------------------------------------------===//
14 // RISC-V specific DAG Nodes.
15 //===----------------------------------------------------------------------===//
17 // Target-independent type requirements, but with target-specific formats.
23 // Target-dependent type requirements.
24 def SDT_RISCVCall : SDTypeProfile<0, -1, [SDTCisVT<0, XLenVT>]>;
50 // Target-independent nodes, but with target-specific formats.
56 // Target-dependent nodes.
97 //===----------------------------------------------------------------------===//
99 //===----------------------------------------------------------------------===//
193 if (Subtarget->is64Bit())
247 // A 12-bit signed immediate which cannot fit in 6-bit signed immediate,
248 // but even negative value fit in 12-bit.
250 return isInt<12>(Imm) && !isInt<6>(Imm) && isInt<12>(-Imm);}]>;
252 // A 13-bit signed immediate where the least significant bit is zero.
303 // A 21-bit signed immediate where the least significant bit is zero.
391 // Standalone (codegen-only) immleaf patterns.
393 // A 6-bit constant greater than 32.
406 return CurDAG->getTargetConstant(-N->getSExtValue(), SDLoc(N),
407 N->getValueType(0));
412 return CurDAG->getTargetConstant(N->getSExtValue() - 32, SDLoc(N),
413 N->getValueType(0));
418 uint64_t XLen = Subtarget->getXLen();
419 return CurDAG->getTargetConstant(XLen - N->getZExtValue(), SDLoc(N),
420 N->getValueType(0));
425 return CurDAG->getTargetConstant(32 - N->getZExtValue(), SDLoc(N),
426 N->getValueType(0));
434 if (!N->hasOneUse())
436 // The immediate operand must be in range [-4096,-2049] or [2048,4094].
437 int64_t Imm = N->getSExtValue();
438 return (-4096 <= Imm && Imm <= -2049) || (2048 <= Imm && Imm <= 4094);
441 // Return imm - (imm < 0 ? -2048 : 2047).
443 int64_t Imm = N->getSExtValue();
444 int64_t Adj = N->getSExtValue() < 0 ? -2048 : 2047;
445 return CurDAG->getTargetConstant(Imm - Adj, SDLoc(N),
446 N->getValueType(0));
449 // Return -2048 if immediate is negative or 2047 if positive. These are the
452 int64_t Imm = N->getSExtValue() < 0 ? -2048 : 2047;
453 return CurDAG->getTargetConstant(Imm, SDLoc(N),
454 N->getValueType(0));
458 return CurDAG->getTargetConstant(llvm::countr_zero(N->getZExtValue()),
459 SDLoc(N), N->getValueType(0));
463 uint64_t XLen = Subtarget->getXLen();
464 uint64_t TrailingOnes = llvm::countr_one(N->getZExtValue());
465 return CurDAG->getTargetConstant(XLen - TrailingOnes, SDLoc(N),
466 N->getValueType(0));
469 // Checks if this mask is a non-empty sequence of ones starting at the
472 if (!N->hasOneUse())
474 return !isInt<32>(N->getSExtValue()) && isMask_64(~N->getSExtValue());
478 if (!N->hasOneUse())
480 return !isInt<12>(N->getSExtValue()) && isMask_64(N->getZExtValue());
486 if (!N->hasOneUse())
489 // bits 63:32 cleared. After that we're looking for a shifted mask but not
490 // an all ones mask.
491 int64_t Imm = N->getSExtValue();
496 //===----------------------------------------------------------------------===//
498 //===----------------------------------------------------------------------===//
502 //===----------------------------------------------------------------------===//
504 //===----------------------------------------------------------------------===//
606 //===----------------------------------------------------------------------===//
608 //===----------------------------------------------------------------------===//
728 // This is a de facto standard (as set by GNU binutils) 32-bit unimplemented
779 //===----------------------------------------------------------------------===//
781 //===----------------------------------------------------------------------===//
843 //===----------------------------------------------------------------------===//
845 //===----------------------------------------------------------------------===//
855 //===----------------------------------------------------------------------===//
856 // Assembler Pseudo Instructions (User-Level ISA, Version 2.2, Chapter 20)
857 //===----------------------------------------------------------------------===//
861 // Note that the size is 32 because up to 8 32-bit instructions are needed to
862 // generate an arbitrary 64-bit immediate. However, the size does not really
888 def : InstAlias<"not $rd, $rs", (XORI GPR:$rd, GPR:$rs, -1)>;
935 // Non-zero offset aliases of "jalr" are the lowest weight, followed by the
936 // two-register form, then the one-register forms and finally "ret".
944 // Non-canonical forms for jump targets also accepted by the assembler.
967 def : InstAlias<"csrr $rd, $csr", (CSRRS GPR:$rd, csr_sysreg:$csr, X0)>;
968 def : InstAlias<"csrw $csr, $rs", (CSRRW X0, csr_sysreg:$csr, GPR:$rs)>;
969 def : InstAlias<"csrs $csr, $rs", (CSRRS X0, csr_sysreg:$csr, GPR:$rs)>;
970 def : InstAlias<"csrc $csr, $rs", (CSRRC X0, csr_sysreg:$csr, GPR:$rs)>;
972 def : InstAlias<"csrwi $csr, $imm", (CSRRWI X0, csr_sysreg:$csr, uimm5:$imm)>;
973 def : InstAlias<"csrsi $csr, $imm", (CSRRSI X0, csr_sysreg:$csr, uimm5:$imm)>;
974 def : InstAlias<"csrci $csr, $imm", (CSRRCI X0, csr_sysreg:$csr, uimm5:$imm)>;
977 def : InstAlias<"csrw $csr, $imm", (CSRRWI X0, csr_sysreg:$csr, uimm5:$imm)>;
978 def : InstAlias<"csrs $csr, $imm", (CSRRSI X0, csr_sysreg:$csr, uimm5:$imm)>;
979 def : InstAlias<"csrc $csr, $imm", (CSRRCI X0, csr_sysreg:$csr, uimm5:$imm)>;
981 def : InstAlias<"csrrw $rd, $csr, $imm", (CSRRWI GPR:$rd, csr_sysreg:$csr, uimm5:$imm)>;
982 def : InstAlias<"csrrs $rd, $csr, $imm", (CSRRSI GPR:$rd, csr_sysreg:$csr, uimm5:$imm)>;
983 def : InstAlias<"csrrc $rd, $csr, $imm", (CSRRCI GPR:$rd, csr_sysreg:$csr, uimm5:$imm)>;
1061 // version 2.1 of the user-level ISA. Like the GNU toolchain, we still accept
1075 //===----------------------------------------------------------------------===//
1077 //===----------------------------------------------------------------------===//
1128 let Inst{31-0} = value;
1179 //===----------------------------------------------------------------------===//
1180 // Pseudo-instructions and codegen patterns
1185 //===----------------------------------------------------------------------===//
1207 return cast<VTSDNode>(N->getOperand(1))->getVT().bitsLE(MVT::i32);
1213 return cast<VTSDNode>(N->getOperand(1))->getVT().bitsLE(MVT::i32);
1226 return N->hasOneUse();
1234 if (auto *N1C = dyn_cast<ConstantSDNode>(N->getOperand(1)))
1235 return N1C->hasOneUse();
1242 return N->hasOneUse();
1252 return CurDAG->ComputeNumSignBits(SDValue(N, 0)) > 32;
1273 if (N->getFlags().hasDisjoint())
1275 KnownBits Known0 = CurDAG->computeKnownBits(N->getOperand(0), 0);
1276 KnownBits Known1 = CurDAG->computeKnownBits(N->getOperand(1), 0);
1291 // AND with leading/trailing ones mask exceeding simm32/simm12.
1292 def : Pat<(i64 (and GPR:$rs, LeadingOnesMask:$mask)),
1293 (SLLI (i64 (SRLI $rs, LeadingOnesMask:$mask)), LeadingOnesMask:$mask)>;
1294 def : Pat<(XLenVT (and GPR:$rs, TrailingOnesMask:$mask)),
1295 (SRLI (XLenVT (SLLI $rs, TrailingOnesMask:$mask)), TrailingOnesMask:$mask)>;
1299 // zero-extends it). For RISC-V, the mask is unnecessary as shifts in the base
1380 // RISC-V doesn't have general instructions for integer setne/seteq, but we can
1388 // handled by a RISC-V instruction.
1391 def : Pat<(XLenVT (setne (XLenVT GPR:$rs1), -1)), (SLTIU GPR:$rs1, -1)>;
1394 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
1396 return CurDAG->getTargetConstant(BrCC, SDLoc(N), Subtarget->getXLenVT());
1431 def OptForMinSize : Predicate<"MF ? MF->getFunction().hasMinSize() : false">;
1440 // Match `riscv_brcc` and lower to the appropriate RISC-V branch instruction.
1524 // Define AsmString to print "call" when compile with -S flag.
1535 // if the offset fits in a signed 21-bit immediate.
1536 // Define AsmString to print "call" when compile with -S flag.
1566 // Define AsmString to print "tail" when compile with -S flag.
1597 // -riscv-use-rematerializable-movimm in RISCVISelDAGToDAG.cpp
1678 // There are single-instruction versions of these in Zbb, so disable these
1722 // Refer to Table A.6 in the version 2.3 draft of the RISC-V Instruction Set
1725 // fence acquire -> fence r, rw
1727 // fence release -> fence rw, w
1729 // fence acq_rel -> fence.tso
1731 // fence seq_cst -> fence rw, rw
1744 // expressed via use-def properties.
1799 /// Other pseudo-instructions
1814 // If we're shifting a 32-bit zero extended value left by 0-31 bits, use 2
1840 return CurDAG->getTargetConstant(SignExtend64<32>(N->getSExtValue()),
1841 SDLoc(N), N->getValueType(0));
1851 def : Pat<(i64 (and GPR:$rs, LeadingOnesWMask:$mask)),
1852 (SLLI (i64 (SRLIW $rs, LeadingOnesWMask:$mask)), LeadingOnesWMask:$mask)>;
1913 // On RV64, we can directly read these 64-bit counter CSRs.
1922 // halves of 64-bit counter CSRs.
1946 // This gets lowered into a 20-byte instruction sequence (at most)
1959 // Select W instructions if only the lower 32-bits of the result are used.
1965 //===----------------------------------------------------------------------===//
1967 //===----------------------------------------------------------------------===//
1974 return CurDAG->getTargetConstant(N->getSExtValue(), SDLoc(N), MVT::i64);
1978 KnownBits Known = CurDAG->computeKnownBits(N->getOperand(0), 0);
2019 def : Pat<(i32 (and GPR:$rs, TrailingOnesMask:$mask)),
2020 (SRLI (i32 (SLLI $rs, (i64 (XLenSubTrailingOnes $mask)))),
2021 (i64 (XLenSubTrailingOnes $mask)))>;
2030 // If we're shifting a 32-bit zero extended value left by 0-31 bits, use 2
2036 //===----------------------------------------------------------------------===//
2038 //===----------------------------------------------------------------------===//
2074 //===----------------------------------------------------------------------===//
2076 //===----------------------------------------------------------------------===//
2085 //===----------------------------------------------------------------------===//
2087 //===----------------------------------------------------------------------===//