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/linux/arch/arm64/boot/dts/exynos/
H A Dexynosautov920-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's ExynosAutov920 SoC pin-mux and pin-config device tree source
7 * Samsung's ExynosAutov920 SoC pin-mux and pin-config options are listed as
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include "exynos-pinctrl.h"
16 gpa0: gpa0-gpio-bank {
17 gpio-controller;
18 #gpio-cells = <2>;
19 interrupt-controller;
20 #interrupt-cells = <2>;
[all …]
H A Dexynosautov9-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's ExynosAutov9 SoC pin-mux and pin-config device tree source
7 * Samsung's ExynosAutov9 SoC pin-mux and pin-config options are listed as
11 #include "exynos-pinctrl.h"
14 gpa0: gpa0-gpio-bank {
15 gpio-controller;
16 #gpio-cells = <2>;
17 interrupt-controller;
18 #interrupt-cells = <2>;
19 interrupt-parent = <&gic>;
[all …]
/linux/arch/arm64/boot/dts/exynos/google/
H A Dgs101-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * GS101 SoC pin-mux and pin-config device tree source
5 * Copyright 2019-2023 Google LLC
6 * Copyright 2023 Linaro Ltd - <peter.griffin@linaro.org>
9 #include "gs101-pinctrl.h"
12 gpa0: gpa0-gpio-bank {
13 gpio-controller;
14 #gpio-cells = <2>;
15 interrupt-controller;
16 #interrupt-cells = <2>;
[all …]
/linux/arch/arm/boot/dts/microchip/
H A Dat91-sama5d3_eds.dts1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 * at91-sama5d3_eds.dts - Device Tree file for the SAMA5D3 Ethernet
10 /dts-v1/;
15 compatible = "microchip,sama5d3-eds", "atmel,sama5d36",
19 stdout-path = "serial0:115200n8";
22 gpio-keys {
23 compatible = "gpio-keys";
25 pinctrl-names = "default";
26 pinctrl-0 = <&pinctrl_key_gpio>;
28 button-3 {
[all …]
H A Dlan966x-kontron-kswitch-d10-mmt.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include "dt-bindings/phy/phy-lan966x-serdes.h"
16 stdout-path = "serial0:115200n8";
19 gpio-restart {
20 compatible = "gpio-restart";
21 pinctrl-0 = <&reset_pins>;
22 pinctrl-names = "default";
29 atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_USART>;
33 pinctrl-0 = <&usart0_pins>;
[all …]
/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx27-eukrea-cpuimx27.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
6 /dts-v1/;
18 clk14745600: clk-uart {
19 compatible = "fixed-clock";
20 #clock-cells = <0>;
21 clock-frequency = <14745600>;
26 pinctrl-names = "default";
27 pinctrl-0 = <&pinctrl_fec>;
32 pinctrl-names = "default";
33 pinctrl-0 = <&pinctrl_i2c1>;
[all …]
H A Dimx6q-prti6q.dts1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
6 /dts-v1/;
8 #include "imx6qdl-prti6q.dtsi"
9 #include <dt-bindings/leds/common.h>
10 #include <dt-bindings/sound/fsl-imx-audmux.h>
21 backlight_lcd: backlight-lcd {
22 compatible = "pwm-backlight";
23 pinctrl-names = "default";
24 pinctrl-0 = <&pinctrl_backlight>;
26 brightness-levels = <0 16 64 255>;
[all …]
H A Dimx6q-evi.dts4 * This file is dual-licensed: you can use it either under the terms
44 /dts-v1/;
46 #include <dt-bindings/gpio/gpio.h>
47 #include <dt-bindings/interrupt-controller/irq.h>
51 compatible = "uniwest,imx6q-evi", "fsl,imx6q";
58 reg_usbh1_vbus: regulator-usbhubreset {
59 compatible = "regulator-fixed";
60 regulator-name = "usbh1_vbus";
61 regulator-min-microvolt = <5000000>;
62 regulator-max-microvolt = <5000000>;
[all …]
H A Dimx27-phytec-phycore-som.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
6 /dts-v1/;
11 compatible = "phytec,imx27-pcm038", "fsl,imx27";
18 reg_3v3: regulator-0 {
19 compatible = "regulator-fixed";
20 regulator-name = "3V3";
21 regulator-min-microvolt = <3300000>;
22 regulator-max-microvolt = <3300000>;
25 reg_5v0: regulator-1 {
26 compatible = "regulator-fixed";
[all …]
H A Dimx6ull-tarragon-common.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR MIT
5 /dts-v1/;
7 #include <dt-bindings/input/input.h>
8 #include <dt-bindings/leds/common.h>
9 #include <dt-bindings/pwm/pwm.h>
18 stdout-path = &uart4;
26 emmc_pwrseq: emmc-pwrseq {
27 compatible = "mmc-pwrseq-emmc";
28 pinctrl-0 = <&pinctrl_emmc_rst>;
29 pinctrl-names = "default";
[all …]
/linux/arch/arm64/boot/dts/xilinx/
H A Dzynqmp-zc1751-xm016-dc2.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP zc1751-xm016-dc2
5 * (C) Copyright 2015 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
11 /dts-v1/;
14 #include "zynqmp-clk-ccf.dtsi"
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
19 model = "ZynqMP zc1751-xm016-dc2 RevA";
20 compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
[all …]
/linux/arch/arm64/boot/dts/qcom/
H A Dsc7280-idp-ec-h1.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
11 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs_gpio_init_high>, <&qup_spi10_cs_gpio>;
12 cs-gpios = <&tlmm 43 GPIO_ACTIVE_LOW>;
15 compatible = "google,cros-ec-spi";
17 interrupt-parent = <&tlmm>;
19 pinctrl-names = "default";
20 pinctrl-0 = <&ap_ec_int_l>;
21 spi-max-frequency = <3000000>;
22 wakeup-source;
25 compatible = "google,cros-ec-pwm";
[all …]
/linux/arch/arm/boot/dts/ti/omap/
H A Domap3-lilly-a83x.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
9 model = "INCOstartec LILLY-A83X module (DM3730)";
10 compatible = "incostartec,omap3-lilly-a83x", "ti,omap3630", "ti,omap36xx", "ti,omap3";
22 compatible = "gpio-leds";
25 label = "lilly-a83x::led1";
27 linux,default-trigger = "default-on";
33 compatible = "ti,omap-twl4030";
34 ti,model = "lilly-a83x";
40 compatible = "regulator-fixed";
41 regulator-name = "VCC3";
[all …]
H A Domap4-duovero-parlor.dts1 // SPDX-License-Identifier: GPL-2.0-only
5 /dts-v1/;
7 #include "omap4-duovero.dtsi"
9 #include <dt-bindings/input/input.h>
13 compatible = "gumstix,omap4-duovero-parlor", "gumstix,omap4-duovero", "ti,omap4430", "ti,omap4";
20 compatible = "gpio-leds";
24 linux,default-trigger = "heartbeat";
29 compatible = "gpio-keys";
30 #address-cells = <1>;
31 #size-cells = <0>;
[all …]
H A Dam335x-nano.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2013 Newflow Ltd - https://www.newflow.co.uk/
5 /dts-v1/;
15 cpu0-supply = <&dcdc2_reg>;
25 compatible = "gpio-leds";
30 default-state = "off";
36 pinctrl-names = "default";
37 pinctrl-0 = <&misc_pins>;
39 misc_pins: misc-pins {
40 pinctrl-single,pins = <
[all …]
H A Domap3-lilly-dbb056.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
5 /dts-v1/;
7 #include "omap3-lilly-a83x.dtsi"
10 model = "INCOstartec LILLY-DBB056 (DM3730)";
11 …compatible = "incostartec,omap3-lilly-dbb056", "incostartec,omap3-lilly-a83x", "ti,omap3630", "ti,…
15 vaux2: regulator-vaux2 {
16 compatible = "ti,twl4030-vaux2";
17 regulator-min-microvolt = <2800000>;
18 regulator-max-microvolt = <2800000>;
19 regulator-always-on;
[all …]
H A Dam335x-myirtech-myc.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* SPDX-FileCopyrightText: Alexander Shiyan, <shc_work@mail.ru> */
5 /* Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ */
7 /dts-v1/;
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/leds/common.h>
15 model = "MYIR MYC-AM335X";
16 compatible = "myir,myc-am335x", "ti,am33xx";
20 cpu0-supply = <&vdd_core>;
21 voltage-tolerance = <2>;
[all …]
/linux/drivers/iio/adc/
H A Dad7606.c1 // SPDX-License-Identifier: GPL-2.0
151 * To activate them, following pins must be pulled high:
152 * -SER/PAR
153 * -SEQEN
154 * And following pins must be pulled low:
155 * -WR/BURST
156 * -DB4/SER1W
193 .name = "ad7605-4",
202 .name = "ad7606-8",
213 .name = "ad7606-6",
[all …]
/linux/arch/arm/boot/dts/intel/pxa/
H A Dpxa300-raumfeld-common.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 #include <dt-bindings/gpio/gpio.h>
5 #include <dt-bindings/input/input.h>
6 #include <dt-bindings/interrupt-controller/irq.h>
10 hw-revision = <0>;
14 stdout-path = &ffuart;
22 reg_3v3: regulator-3v3 {
23 compatible = "regulator-fixed";
24 regulator-name = "3v3-fixed-supply";
25 regulator-min-microvolt = <3300000>;
[all …]
/linux/arch/arm/boot/dts/qcom/
H A Dqcom-ipq4019-ap.dk07.1-c1.dts1 // SPDX-License-Identifier: GPL-2.0
4 #include <dt-bindings/gpio/gpio.h>
5 #include "qcom-ipq4019-ap.dk07.1.dtsi"
8 model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK07.1-C1";
9 compatible = "qcom,ipq4019-ap-dk07.1-c1", "qcom,ipq4019";
14 perst-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>;
22 serial_1_pins: serial1-state {
23 pins = "gpio8", "gpio9",
26 bias-disable;
29 spi_0_pins: spi-0-state {
[all …]
H A Dqcom-ipq4019-ap.dk04.1.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 #include "qcom-ipq4019.dtsi"
5 #include <dt-bindings/input/input.h>
6 #include <dt-bindings/gpio/gpio.h>
9 model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK04.1";
17 stdout-path = "serial0:115200n8";
27 serial_0_pins: serial0-state {
28 pins = "gpio16", "gpio17";
30 bias-disable;
33 serial_1_pins: serial1-state {
[all …]
H A Dqcom-ipq4019-ap.dk01.1.dtsi17 #include <dt-bindings/gpio/gpio.h>
18 #include "qcom-ipq4019.dtsi"
21 model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK01.1";
28 stdout-path = "serial0:115200n8";
37 serial_pins: serial-state {
38 pins = "gpio60", "gpio61";
40 bias-disable;
43 spi_0_pins: spi-0-state {
44 spi0-pins {
45 pins = "gpio55", "gpio56", "gpio57";
[all …]
/linux/Documentation/devicetree/bindings/memory-controllers/ddr/
H A Djedec,lpddr-channel.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr-channel.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 An LPDDR channel is a completely independent set of LPDDR pins (DQ, CA, CS,
16 - Julius Werner <jwerner@chromium.org>
21 - jedec,lpddr2-channel
22 - jedec,lpddr3-channel
23 - jedec,lpddr4-channel
24 - jedec,lpddr5-channel
[all …]
/linux/arch/arm/boot/dts/nxp/lpc/
H A Dlpc4337-ciaa.dts2 * CIAA NXP LPC4337 (http://www.proyecto-ciaa.com.ar)
4 * Copyright (C) 2015 VanguardiaSur - www.vanguardiasur.com.ar
9 * Released under the terms of 3-clause BSD License
12 /dts-v1/;
17 #include "dt-bindings/gpio/gpio.h"
30 stdout-path = &uart2;
40 enet_rmii_pins: enet-rmii-pins {
42 pins = "p1_15", "p0_0";
44 slew-rate = <1>;
45 bias-disable;
[all …]
/linux/Documentation/devicetree/bindings/pinctrl/
H A Dmarvell,kirkwood-pinctrl.txt3 Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
7 - compatible: "marvell,88f6180-pinctrl",
8 "marvell,88f6190-pinctrl", "marvell,88f6192-pinctrl",
9 "marvell,88f6281-pinctrl", "marvell,88f6282-pinctrl",
10 "marvell,98dx4122-pinctrl", "marvell,98dx1135-pinctrl"
11 - reg: register specifier of MPP registers
14 It also support the 88f6281-based variant in the 98dx412x Bobcat SoCs.
16 Available mpp pins/groups and functions:
22 name pins functions
24 mpp0 0 gpio, nand(io2), spi(cs)
[all …]

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