| /linux/Documentation/devicetree/bindings/memory-controllers/ |
| H A D | ti-aemif.txt | 4 provide a glue-less interface to a variety of asynchronous memory devices like
11 Davinci DM646x - http://www.ti.com/lit/ug/sprueq7c/sprueq7c.pdf
12 OMAP-L138 (DA850) - http://www.ti.com/lit/ug/spruh77a/spruh77a.pdf
13 Kestone - http://www.ti.com/lit/ug/sprugz3a/sprugz3a.pdf
17 - compatible: "ti,davinci-aemif"
18 "ti,keystone-aemif"
19 "ti,da850-aemif"
21 - reg: contains offset/length value for AEMIF control registers
24 - #address-cells: Must be 2. The partition number has to be encoded in the
25 first address cell and it may accept values 0..N-1
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| H A D | arm,pl172.txt | 5 - compatible: Must be "arm,primecell" and exactly one from
8 - reg: Must contains offset/length value for controller.
10 - #address-cells: Must be 2. The partition number has to be encoded in the
11 first address cell and it may accept values 0..N-1
12 (N - total number of partitions). The second cell is the
15 - #size-cells: Must be set to 1.
17 - ranges: Must contain one or more chip select memory regions.
19 - clocks: Must contain references to controller clocks.
21 - clock-names: Must contain "mpmcclk" and "apb_pclk".
23 - clock-ranges: Empty property indicating that child nodes can inherit
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| /linux/Documentation/devicetree/bindings/gpio/ |
| H A D | spear_spics.txt | 1 === ST Microelectronics SPEAr SPI CS Driver ===
17 * compatible: should be defined as "st,spear-spics-gpio"
19 * st-spics,peripcfg-reg: peripheral configuration register offset
20 * st-spics,sw-enable-bit: bit offset to enable sw control
21 * st-spics,cs-value-bit: bit offset to drive chipselect low or high
22 * st-spics,cs-enable-mask: chip select number bit mask
23 * st-spics,cs-enable-shift: chip select number program offset
24 * gpio-controller: Marks the device node as gpio controller
25 * #gpio-cells: should be 1 and will mention chip select number
30 -------
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| /linux/drivers/memory/ |
| H A D | ti-aemif.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2010 - 2013 Texas Instruments Incorporated. http://www.ti.com/
8 * Murali Karicheri <m-karicheri2@ti.com>
83 * struct aemif_cs_data: structure to hold cs parameters
84 * @cs: chip-select number
97 u8 cs; member
115 * @num_cs: number of assigned chip-selects
116 * @cs_offset: start number of cs nodes
117 * @cs_data: array of chip-select settings
129 * aemif_calc_rate - calculate timing data.
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| /linux/tools/testing/selftests/cachestat/ |
| H A D | test_cachestat.c | 1 // SPDX-License-Identifier: GPL-2.0
28 void print_cachestat(struct cachestat *cs) in print_cachestat() argument
32 cs->nr_cache, cs->nr_dirty, cs->nr_writeback, in print_cachestat()
33 cs->nr_evicted, cs->nr_recently_evicted); in print_cachestat()
68 remained -= read_len; in write_exactly()
84 remained -= write_len; in write_exactly()
115 * If test_fsync == true, fsync the file, then check the number of dirty
126 struct cachestat cs; in test_cachestat() local
131 if (fd == -1) { in test_cachestat()
147 syscall_ret = syscall(__NR_cachestat, fd, &cs_range, &cs, 0); in test_cachestat()
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| /linux/include/uapi/drm/ |
| H A D | habanalabs_accel.h | 1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note
3 * Copyright 2016-2023 HabanaLabs, Ltd.
14 * Defines that are asic-specific but constitutes as ABI between kernel driver
32 /* Max number of elements in timestamps registration buffers */
195 * stream id is a running number from 0 up to (N-1), where N is the number
656 * enum hl_goya_dma_direction - Direction of DMA operation inside a LIN_DMA packet that is
668 * @HL_DMA_ENUM_MAX: number of values in enum
683 * enum hl_device_status - Device status information.
715 * Notifier event values - for the notification mechanism and the HL_INFO_GET_EVENTS command
717 * HL_NOTIFIER_EVENT_TPC_ASSERT - Indicates TPC assert event
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| /linux/drivers/net/slip/ |
| H A D | slhc.c | 21 * - Initial distribution.
28 * - 01-31-90 initial adaptation (from 1.19)
29 * PPP.05 02-15-90 [ks]
30 * PPP.08 05-02-90 [ks] use PPP protocol field to signal compression
31 * PPP.15 09-90 [ks] improve mbuf handling
32 * PPP.16 11-02 [karn] substantially rewritten to use NOS facilities
34 * - Feb 1991 Bill_Simpson@um.cc.umich.edu
35 * variable number of conversation slots
39 * - Jul 1994 Dmitry Gorodchanin
41 * - Oct 1994 Dmitry Gorodchanin
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| /linux/Documentation/devicetree/bindings/spi/ |
| H A D | spi-davinci.txt | 4 Keystone 2 - https://www.ti.com/lit/ug/sprugp2a/sprugp2a.pdf
5 dm644x - https://www.ti.com/lit/ug/sprue32a/sprue32a.pdf
6 OMAP-L138/da830 - http://www.ti.com/lit/ug/spruh77a/spruh77a.pdf
9 - #address-cells: number of cells required to define a chip select
11 - #size-cells: should be zero.
12 - compatible:
13 - "ti,dm6441-spi" for SPI used similar to that on DM644x SoC family
14 - "ti,da830-spi" for SPI used similar to that on DA8xx SoC family
15 - "ti,keystone-spi" for SPI used similar to that on Keystone2 SoC
17 - reg: Offset and length of SPI controller register space
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| H A D | spi-controller.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/spi/spi-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Mark Brown <broonie@kernel.org>
20 pattern: "^spi(@.*|-([0-9]|[1-9][0-9]+))?$"
22 "#address-cells":
25 "#size-cells":
28 cs-gpios:
31 If that property is used, the number of chip selects will be
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| H A D | spi-lantiq-ssc.txt | 4 - compatible: "lantiq,ase-spi", "lantiq,falcon-spi", "lantiq,xrx100-spi",
5 "intel,lgm-spi"
6 - #address-cells: see spi-bus.txt
7 - #size-cells: see spi-bus.txt
8 - reg: address and length of the spi master registers
9 - interrupts:
10 For compatible "intel,lgm-ssc" - the common interrupt number for
18 - clocks: spi clock phandle
19 - num-cs: see spi-bus.txt, set to 8 if unset
20 - base-cs: the number of the first chip select, set to 1 if unset.
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| H A D | spi-cadence.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/spi-cadence.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Michal Simek <michal.simek@amd.com>
13 - $ref: spi-controller.yaml#
18 - cdns,spi-r1p6
19 - xlnx,zynq-spi-r1p6
27 clock-names:
29 - const: ref_clk
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| /linux/Documentation/usb/ |
| H A D | gadget_configfs.rst | 19 a number of interfaces which, from the gadget's perspective, are known as
22 Linux provides a number of functions for gadgets to use.
50 http://www.spinics.net/lists/linux-usb/msg76388.html)
55 $ mount none $CONFIGFS_HOME -t configfs
60 -----------------------
81 A gadget also needs its serial number, manufacturer and product strings.
89 $ echo <serial number> > strings/0x409/serialnumber
104 ------------------------------
106 Each gadget will consist of a number of configurations, their corresponding
109 $ mkdir configs/<name>.<number>
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| /linux/arch/x86/include/asm/ |
| H A D | ptrace.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
14 * NB: 32-bit x86 CPUs are inconsistent as what happens in the
17 * - pushl %seg: some do a 16-bit write and leave the high
19 * - movl %seg, [mem]: some do a 16-bit write despite the movl
20 * - IDT entry: some (e.g. 486) will leave the high bits of CS
23 * Fortunately, x86-32 doesn't read the high bits on POP or IRET,
24 * so we can just treat all of the segment registers as 16-bit
41 * On interrupt, gs and __gsh store the vector number. They never
49 unsigned short cs; member
60 /* CS selector */
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| /linux/include/linux/ |
| H A D | clocksource.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
36 * struct clocksource - hardware abstraction for a free running counter
37 * Provides mostly state-free accessors to the underlying hardware.
49 * @archdata: Optional arch-specific data
60 * 1-99: Unfit for real use
62 * 100-199: Base level usability.
64 * 200-299: Good.
66 * 300-399: Desired.
68 * 400-499: Perfect
69 * The ideal clocksource. A must-use where
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| /linux/kernel/cgroup/ |
| H A D | cpuset-internal.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
82 * The user-configured masks can only be changed by writing to
96 * The user-configured masks are always the same with effective masks.
99 /* user-configured CPUs and Memory Nodes allow to tasks */
112 * to sub-partitions below & hence excluded from its effective_cpus.
138 * - top_cpuset.old_mems_allowed is initialized to mems_allowed.
139 * - A new cpuset's old_mems_allowed is initialized when some
141 * - old_mems_allowed is used in cpuset_migrate_mm() when we change
151 * zeroing cpus/mems_allowed between ->can_attach() and ->attach().
158 /* number of valid local child partitions */
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| /linux/lib/ |
| H A D | string.c | 1 // SPDX-License-Identifier: GPL-2.0
11 * found in <asm-xx/string.h>), or get overloaded by FORTIFY_SOURCE.
31 #include <asm/word-at-a-time.h>
35 * strncasecmp - Case insensitive, length-limited string comparison
38 * @len: the maximum number of characters to compare
59 } while (--len); in strncasecmp()
60 return (int)c1 - (int)c2; in strncasecmp()
74 return c1 - c2; in strcasecmp()
100 count--; in strncpy()
120 return -E2BIG; in sized_strscpy()
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| /linux/kernel/time/ |
| H A D | clocksource.c | 1 // SPDX-License-Identifier: GPL-2.0+
20 #include "tick-internal.h"
23 static void clocksource_enqueue(struct clocksource *cs);
25 static noinline u64 cycles_to_nsec_safe(struct clocksource *cs, u64 start, u64 end) in cycles_to_nsec_safe() argument
27 u64 delta = clocksource_delta(end, start, cs->mask, cs->max_raw_delta); in cycles_to_nsec_safe()
29 if (likely(delta < cs->max_cycles)) in cycles_to_nsec_safe()
30 return clocksource_cyc2ns(delta, cs->mult, cs->shift); in cycles_to_nsec_safe()
32 return mul_u64_u32_shr(delta, cs->mult, cs->shift); in cycles_to_nsec_safe()
36 * clocks_calc_mult_shift - calculate mult/shift factors for scaled math of clocks
71 sftacc--; in clocks_calc_mult_shift()
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| /linux/Documentation/devicetree/bindings/bus/ |
| H A D | nvidia,tegra20-gmi.txt | 10 - compatible : Should contain one of the following:
11 For Tegra20 must contain "nvidia,tegra20-gmi".
12 For Tegra30 must contain "nvidia,tegra30-gmi".
13 - reg: Should contain GMI controller registers location and length.
14 - clocks: Must contain an entry for each entry in clock-names.
15 - clock-names: Must include the following entries: "gmi"
16 - resets : Must contain an entry for each entry in reset-names.
17 - reset-names : Must include the following entries: "gmi"
18 - #address-cells: The number of cells used to represent physical base
20 - #size-cells: The number of cells used to represent the size of an address
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| /linux/drivers/gpu/drm/i915/gt/ |
| H A D | gen6_engine_cs.c | 1 // SPDX-License-Identifier: MIT
18 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
22 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
23 * produced by non-pipelined state commands), software needs to first
24 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
27 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
28 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
32 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
33 * BEFORE the pipe-control with a post-sync op and no write-cache
41 * - Render Target Cache Flush Enable ([12] of DW1)
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| /linux/drivers/mfd/ |
| H A D | atmel-smc.c | 1 // SPDX-License-Identifier: GPL-2.0-only
8 * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
11 #include <linux/mfd/syscon/atmel-smc.h>
15 * atmel_smc_cs_conf_init - initialize a SMC CS conf
16 * @conf: the SMC CS conf to initialize
27 * atmel_smc_cs_encode_ncycles - encode a number of MCK clk cycles in the
29 * @ncycles: number of MCK clk cycles
40 * If the @ncycles value is too big to be encoded, -ERANGE is returned and
49 unsigned int lsbmask = GENMASK(msbpos - 1, 0); in atmel_smc_cs_encode_ncycles()
50 unsigned int msbmask = GENMASK(msbwidth - 1, 0); in atmel_smc_cs_encode_ncycles()
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| /linux/drivers/firmware/efi/libstub/ |
| H A D | string.c | 1 // SPDX-License-Identifier: GPL-2.0
16 * strlen - Find the length of a string
25 return sc - s; in strlen()
31 * strnlen - Find the length of a length-limited string
33 * @count: The maximum number of bytes to search
39 for (sc = s; count-- && *sc != '\0'; ++sc) in strnlen()
41 return sc - s; in strnlen()
46 * strstr - Find the first substring in a %NUL terminated string
59 l1--; in strstr()
69 * strcmp - Compare two strings
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| /linux/drivers/accel/habanalabs/common/ |
| H A D | habanalabs.h | 1 /* SPDX-License-Identifier: GPL-2.0
3 * Copyright 2016-2023 HabanaLabs, Ltd.
19 #include <linux/dma-direction.h>
28 #include <linux/io-64-nonatomic-lo-hi.h>
30 #include <linux/dma-buf.h>
45 * bits[63:59] - Encode mmap type
46 * bits[45:0] - mmap offset value
51 #define HL_MMAP_TYPE_SHIFT (59 - PAGE_SHIFT)
110 * enum hl_mmu_page_table_location - mmu page table location
111 * @MMU_DR_PGT: page-table is located on device DRAM.
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| /linux/Documentation/ABI/testing/ |
| H A D | sysfs-kernel-slab | 4 Contact: Pekka Enberg <penberg@cs.helsinki.fi>,
5 Christoph Lameter <cl@linux-foundation.org>
16 Contact: Pekka Enberg <penberg@cs.helsinki.fi>,
17 Christoph Lameter <cl@linux-foundation.org>
19 The aliases file is read-only and specifies how many caches
25 Contact: Pekka Enberg <penberg@cs.helsinki.fi>,
26 Christoph Lameter <cl@linux-foundation.org>
28 The align file is read-only and specifies the cache's object
34 Contact: Pekka Enberg <penberg@cs.helsinki.fi>,
35 Christoph Lameter <cl@linux-foundation.org>
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| /linux/drivers/clocksource/ |
| H A D | mmio.c | 1 // SPDX-License-Identifier: GPL-2.0-only
22 return (u64)readl_relaxed(to_mmio_clksrc(c)->reg); in clocksource_mmio_readl_up()
27 return ~(u64)readl_relaxed(to_mmio_clksrc(c)->reg) & c->mask; in clocksource_mmio_readl_down()
32 return (u64)readw_relaxed(to_mmio_clksrc(c)->reg); in clocksource_mmio_readw_up()
37 return ~(u64)readw_relaxed(to_mmio_clksrc(c)->reg) & c->mask; in clocksource_mmio_readw_down()
41 * clocksource_mmio_init - Initialize a simple mmio based clocksource
46 * @bits: Number of valid bits
53 struct clocksource_mmio *cs; in clocksource_mmio_init() local
56 return -EINVAL; in clocksource_mmio_init()
58 cs = kzalloc(sizeof(struct clocksource_mmio), GFP_KERNEL); in clocksource_mmio_init()
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| /linux/arch/arm/plat-orion/ |
| H A D | pcie.c | 2 * arch/arm/plat-orion/pcie.c
16 #include <plat/addr-map.h>
28 #define PCIE_BAR_CTRL_OFF(n) (0x1804 + ((n - 1) * 4))
98 * MV-S104860-U0, Rev. C: in orion_pcie_reset()
101 * This bit should be cleared after the link is re-established. in orion_pcie_reset()
120 * BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks
121 * WIN[0-3] -> DRAM bank[0-3]
154 for (i = 0; i < dram->num_cs; i++) { in orion_pcie_setup_wins()
155 const struct mbus_dram_window *cs = dram->cs + i; in orion_pcie_setup_wins() local
157 writel(cs->base & 0xffff0000, base + PCIE_WIN04_BASE_OFF(i)); in orion_pcie_setup_wins()
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