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/linux/Documentation/devicetree/bindings/memory-controllers/
H A Dti-aemif.txt4 provide a glue-less interface to a variety of asynchronous memory devices like
11 Davinci DM646x - http://www.ti.com/lit/ug/sprueq7c/sprueq7c.pdf
12 OMAP-L138 (DA850) - http://www.ti.com/lit/ug/spruh77a/spruh77a.pdf
13 Kestone - http://www.ti.com/lit/ug/sprugz3a/sprugz3a.pdf
17 - compatible: "ti,davinci-aemif"
18 "ti,keystone-aemif"
19 "ti,da850-aemif"
21 - reg: contains offset/length value for AEMIF control registers
24 - #address-cells: Must be 2. The partition number has to be encoded in the
25 first address cell and it may accept values 0..N-1
[all …]
H A Dti,gpmc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/ti,gpmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Tony Lindgren <tony@atomide.com>
11 - Roger Quadros <rogerq@kernel.org>
16 - Asynchronous SRAM-like memories and ASICs
17 - Asynchronous, synchronous, and page mode burst NOR flash
18 - NAND flash
19 - Pseudo-SRAM devices
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/linux/include/uapi/drm/
H A Dhabanalabs_accel.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note
3 * Copyright 2016-2023 HabanaLabs, Ltd.
14 * Defines that are asic-specific but constitutes as ABI between kernel driver
32 /* Max number of elements in timestamps registration buffers */
195 * stream id is a running number from 0 up to (N-1), where N is the number
656 * enum hl_goya_dma_direction - Direction of DMA operation inside a LIN_DMA packet that is
668 * @HL_DMA_ENUM_MAX: number of values in enum
683 * enum hl_device_status - Device status information.
715 * Notifier event values - for the notification mechanism and the HL_INFO_GET_EVENTS command
717 * HL_NOTIFIER_EVENT_TPC_ASSERT - Indicates TPC assert event
[all …]
/linux/tools/testing/selftests/cachestat/
H A Dtest_cachestat.c1 // SPDX-License-Identifier: GPL-2.0
28 void print_cachestat(struct cachestat *cs) in print_cachestat() argument
32 cs->nr_cache, cs->nr_dirty, cs->nr_writeback, in print_cachestat()
33 cs->nr_evicted, cs->nr_recently_evicted); in print_cachestat()
73 remained -= read_len; in write_exactly()
89 remained -= write_len; in write_exactly()
120 * If test_fsync == true, fsync the file, then check the number of dirty
131 struct cachestat cs; in test_cachestat() local
136 if (fd == -1) { in test_cachestat()
152 syscall_ret = syscall(__NR_cachestat, fd, &cs_range, &cs, 0); in test_cachestat()
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/linux/drivers/net/slip/
H A Dslhc.c21 * - Initial distribution.
28 * - 01-31-90 initial adaptation (from 1.19)
29 * PPP.05 02-15-90 [ks]
30 * PPP.08 05-02-90 [ks] use PPP protocol field to signal compression
31 * PPP.15 09-90 [ks] improve mbuf handling
32 * PPP.16 11-02 [karn] substantially rewritten to use NOS facilities
34 * - Feb 1991 Bill_Simpson@um.cc.umich.edu
35 * variable number of conversation slots
39 * - Jul 1994 Dmitry Gorodchanin
41 * - Oct 1994 Dmitry Gorodchanin
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/linux/Documentation/devicetree/bindings/spi/
H A Dspi-davinci.txt4 Keystone 2 - https://www.ti.com/lit/ug/sprugp2a/sprugp2a.pdf
5 dm644x - https://www.ti.com/lit/ug/sprue32a/sprue32a.pdf
6 OMAP-L138/da830 - http://www.ti.com/lit/ug/spruh77a/spruh77a.pdf
9 - #address-cells: number of cells required to define a chip select
11 - #size-cells: should be zero.
12 - compatible:
13 - "ti,dm6441-spi" for SPI used similar to that on DM644x SoC family
14 - "ti,da830-spi" for SPI used similar to that on DA8xx SoC family
15 - "ti,keystone-spi" for SPI used similar to that on Keystone2 SoC
17 - reg: Offset and length of SPI controller register space
[all …]
H A Dspi-lantiq-ssc.txt4 - compatible: "lantiq,ase-spi", "lantiq,falcon-spi", "lantiq,xrx100-spi",
5 "intel,lgm-spi"
6 - #address-cells: see spi-bus.txt
7 - #size-cells: see spi-bus.txt
8 - reg: address and length of the spi master registers
9 - interrupts:
10 For compatible "intel,lgm-ssc" - the common interrupt number for
18 - clocks: spi clock phandle
19 - num-cs: see spi-bus.txt, set to 8 if unset
20 - base-cs: the number of the first chip select, set to 1 if unset.
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H A Dspi-cadence.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/spi-cadence.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Michal Simek <michal.simek@amd.com>
13 - $ref: spi-controller.yaml#
18 - cdns,spi-r1p6
19 - xlnx,zynq-spi-r1p6
27 clock-names:
29 - const: ref_clk
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/linux/Documentation/usb/
H A Dgadget_configfs.rst19 a number of interfaces which, from the gadget's perspective, are known as
22 Linux provides a number of functions for gadgets to use.
50 http://www.spinics.net/lists/linux-usb/msg76388.html)
55 $ mount none $CONFIGFS_HOME -t configfs
60 -----------------------
81 A gadget also needs its serial number, manufacturer and product strings.
89 $ echo <serial number> > strings/0x409/serialnumber
104 ------------------------------
106 Each gadget will consist of a number of configurations, their corresponding
109 $ mkdir configs/<name>.<number>
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/linux/drivers/clocksource/
H A Dtimer-nxp-stm.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Copyright 2018,2021-2025 NXP
9 * timing functions. STM includes a 32-bit count-up timer and four
10 * 32-bit compare channels with a separate interrupt source for each
12 * 8-bit prescale value (1 to 256). It has ability to stop the timer
61 struct clocksource cs; member
82 static struct stm_timer *cs_to_stm(struct clocksource *cs) in DEFINE_GUARD()
84 return container_of(cs, struct stm_timer, cs); in DEFINE_GUARD()
94 return readl(STM_CNT(stm_sched_clock->base)); in nxp_stm_read_sched_clock()
99 return readl(STM_CNT(stm_timer->base)); in nxp_stm_clocksource_getcnt()
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H A Dmmio.c1 // SPDX-License-Identifier: GPL-2.0-only
22 return (u64)readl_relaxed(to_mmio_clksrc(c)->reg); in clocksource_mmio_readl_up()
27 return ~(u64)readl_relaxed(to_mmio_clksrc(c)->reg) & c->mask; in clocksource_mmio_readl_down()
32 return (u64)readw_relaxed(to_mmio_clksrc(c)->reg); in clocksource_mmio_readw_up()
37 return ~(u64)readw_relaxed(to_mmio_clksrc(c)->reg) & c->mask; in clocksource_mmio_readw_down()
41 * clocksource_mmio_init - Initialize a simple mmio based clocksource
46 * @bits: Number of valid bits
53 struct clocksource_mmio *cs; in clocksource_mmio_init() local
56 return -EINVAL; in clocksource_mmio_init()
58 cs = kzalloc(sizeof(struct clocksource_mmio), GFP_KERNEL); in clocksource_mmio_init()
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/linux/include/linux/
H A Dclocksource.h1 /* SPDX-License-Identifier: GPL-2.0 */
36 * struct clocksource - hardware abstraction for a free running counter
37 * Provides mostly state-free accessors to the underlying hardware.
49 * @archdata: Optional arch-specific data
60 * 1-99: Unfit for real use
62 * 100-199: Base level usability.
64 * 200-299: Good.
66 * 300-399: Desired.
68 * 400-499: Perfect
69 * The ideal clocksource. A must-use where
[all …]
/linux/kernel/cgroup/
H A Dcpuset-internal.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
83 * The user-configured masks can only be changed by writing to
97 * The user-configured masks are always the same with effective masks.
100 /* user-configured CPUs and Memory Nodes allow to tasks */
113 * to sub-partitions below & hence excluded from its effective_cpus.
139 * - top_cpuset.old_mems_allowed is initialized to mems_allowed.
140 * - A new cpuset's old_mems_allowed is initialized when some
142 * - old_mems_allowed is used in cpuset_migrate_mm() when we change
152 * zeroing cpus/mems_allowed between ->can_attach() and ->attach().
159 /* number of valid local child partitions */
[all …]
/linux/kernel/time/
H A Dclocksource.c1 // SPDX-License-Identifier: GPL-2.0+
20 #include "tick-internal.h"
23 static void clocksource_enqueue(struct clocksource *cs);
25 static noinline u64 cycles_to_nsec_safe(struct clocksource *cs, u64 start, u64 end) in cycles_to_nsec_safe() argument
27 u64 delta = clocksource_delta(end, start, cs->mask, cs->max_raw_delt in cycles_to_nsec_safe()
195 clocksource_change_rating(struct clocksource * cs,int rating) clocksource_change_rating() argument
202 __clocksource_unstable(struct clocksource * cs) __clocksource_unstable() argument
231 clocksource_mark_unstable(struct clocksource * cs) clocksource_mark_unstable() argument
253 cs_watchdog_read(struct clocksource * cs,u64 * csnow,u64 * wdnow) cs_watchdog_read() argument
357 struct clocksource *cs = (struct clocksource *)csin; clocksource_verify_one_cpu() local
362 clocksource_verify_percpu(struct clocksource * cs) clocksource_verify_percpu() argument
421 struct clocksource *cs; clocksource_reset_watchdog() local
433 struct clocksource *cs; clocksource_watchdog() local
627 clocksource_enqueue_watchdog(struct clocksource * cs) clocksource_enqueue_watchdog() argument
644 struct clocksource *cs, *old_wd; clocksource_select_watchdog() local
679 clocksource_dequeue_watchdog(struct clocksource * cs) clocksource_dequeue_watchdog() argument
693 struct clocksource *cs, *tmp; __clocksource_watchdog_kthread() local
731 clocksource_is_watchdog(struct clocksource * cs) clocksource_is_watchdog() argument
738 clocksource_enqueue_watchdog(struct clocksource * cs) clocksource_enqueue_watchdog() argument
745 clocksource_dequeue_watchdog(struct clocksource * cs) clocksource_dequeue_watchdog() argument
748 clocksource_is_watchdog(struct clocksource * cs) clocksource_is_watchdog() argument
749 clocksource_mark_unstable(struct clocksource * cs) clocksource_mark_unstable() argument
756 clocksource_is_suspend(struct clocksource * cs) clocksource_is_suspend() argument
761 __clocksource_suspend_select(struct clocksource * cs) __clocksource_suspend_select() argument
790 struct clocksource *cs, *old_suspend; clocksource_suspend_select() local
818 clocksource_start_suspend_timing(struct clocksource * cs,u64 start_cycles) clocksource_start_suspend_timing() argument
856 clocksource_stop_suspend_timing(struct clocksource * cs,u64 cycle_now) clocksource_stop_suspend_timing() argument
891 struct clocksource *cs; clocksource_suspend() local
903 struct clocksource *cs; clocksource_resume() local
929 clocksource_max_adjustment(struct clocksource * cs) clocksource_max_adjustment() argument
990 clocksource_update_max_deferment(struct clocksource * cs) clocksource_update_max_deferment() argument
1008 struct clocksource *cs; clocksource_find_best() local
1031 struct clocksource *best, *cs; __clocksource_select() local
1122 clocksource_enqueue(struct clocksource * cs) clocksource_enqueue() argument
1148 __clocksource_update_freq_scale(struct clocksource * cs,u32 scale,u32 freq) __clocksource_update_freq_scale() argument
1240 __clocksource_register_scale(struct clocksource * cs,u32 scale,u32 freq) __clocksource_register_scale() argument
1277 clocksource_unbind(struct clocksource * cs) clocksource_unbind() argument
1316 clocksource_unregister(struct clocksource * cs) clocksource_unregister() argument
1408 struct clocksource *cs; unbind_clocksource_store() local
[all...]
/linux/drivers/gpu/drm/i915/gt/
H A Dgen6_engine_cs.c1 // SPDX-License-Identifier: MIT
18 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
22 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
23 * produced by non-pipelined state commands), software needs to first
24 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
27 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
28 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
32 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
33 * BEFORE the pipe-control with a post-sync op and no write-cache
41 * - Render Target Cache Flush Enable ([12] of DW1)
[all …]
/linux/Documentation/devicetree/bindings/bus/
H A Dnvidia,tegra20-gmi.txt10 - compatible : Should contain one of the following:
11 For Tegra20 must contain "nvidia,tegra20-gmi".
12 For Tegra30 must contain "nvidia,tegra30-gmi".
13 - reg: Should contain GMI controller registers location and length.
14 - clocks: Must contain an entry for each entry in clock-names.
15 - clock-names: Must include the following entries: "gmi"
16 - resets : Must contain an entry for each entry in reset-names.
17 - reset-names : Must include the following entries: "gmi"
18 - #address-cells: The number of cells used to represent physical base
20 - #size-cells: The number of cells used to represent the size of an address
[all …]
/linux/lib/
H A Dstring.c1 // SPDX-License-Identifier: GPL-2.0
11 * found in <asm-xx/string.h>), or get overloaded by FORTIFY_SOURCE.
31 #include <asm/word-at-a-time.h>
35 * strncasecmp - Case insensitive, length-limited string comparison
38 * @len: the maximum number of characters to compare
59 } while (--len); in strncasecmp()
60 return (int)c1 - (int)c2; in strncasecmp()
74 return c1 - c2; in strcasecmp()
100 count--; in strncpy()
120 return -E2BIG; in sized_strscpy()
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/linux/drivers/firmware/efi/libstub/
H A Dstring.c1 // SPDX-License-Identifier: GPL-2.0
16 * strlen - Find the length of a string
25 return sc - s; in strlen()
31 * strnlen - Find the length of a length-limited string
33 * @count: The maximum number of bytes to search
39 for (sc = s; count-- && *sc != '\0'; ++sc) in strnlen()
41 return sc - s; in strnlen()
46 * strstr - Find the first substring in a %NUL terminated string
59 l1--; in strstr()
69 * strcmp - Compare two strings
[all …]
/linux/drivers/accel/habanalabs/common/
H A Dhabanalabs.h1 /* SPDX-License-Identifier: GPL-2.0
3 * Copyright 2016-2023 HabanaLabs, Ltd.
19 #include <linux/dma-direction.h>
28 #include <linux/io-64-nonatomic-lo-hi.h>
30 #include <linux/dma-buf.h>
45 * bits[63:59] - Encode mmap type
46 * bits[45:0] - mmap offset value
51 #define HL_MMAP_TYPE_SHIFT (59 - PAGE_SHIFT)
110 * enum hl_mmu_page_table_location - mmu page table location
111 * @MMU_DR_PGT: page-table is located on device DRAM.
[all …]
/linux/Documentation/ABI/testing/
H A Dsysfs-kernel-slab4 Contact: Pekka Enberg <penberg@cs.helsinki.fi>,
16 Contact: Pekka Enberg <penberg@cs.helsinki.fi>,
19 The aliases file is read-only and specifies how many caches
25 Contact: Pekka Enberg <penberg@cs.helsinki.fi>,
28 The align file is read-only and specifies the cache's object
34 Contact: Pekka Enberg <penberg@cs.helsinki.fi>,
37 The alloc_calls file is read-only and lists the kernel code
41 Documentation/admin-guide/mm/slab.rst).
46 Contact: Pekka Enberg <penberg@cs.helsinki.fi>,
57 Contact: Pekka Enberg <penberg@cs.helsinki.fi>,
[all …]
/linux/arch/arm/plat-orion/
H A Dpcie.c2 * arch/arm/plat-orion/pcie.c
16 #include <plat/addr-map.h>
28 #define PCIE_BAR_CTRL_OFF(n) (0x1804 + ((n - 1) * 4))
98 * MV-S104860-U0, Rev. C: in orion_pcie_reset()
101 * This bit should be cleared after the link is re-established. in orion_pcie_reset()
120 * BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks
121 * WIN[0-3] -> DRAM bank[0-3]
154 for (i = 0; i < dram->num_cs; i++) { in orion_pcie_setup_wins()
155 const struct mbus_dram_window *cs = dram->cs + i; in orion_pcie_setup_wins() local
157 writel(cs->base & 0xffff0000, base + PCIE_WIN04_BASE_OFF(i)); in orion_pcie_setup_wins()
[all …]
/linux/arch/arm/mach-orion5x/
H A Dpci.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * arch/arm/mach-orion5x/pci.c
18 #include <plat/addr-map.h>
25 * Note1: The local PCIe bus number is '0'. The local PCI bus number
49 * Don't go out when trying to access -- in pcie_valid_config()
79 if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) { in pcie_rd_conf()
96 if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) { in pcie_rd_conf_wa()
102 * We only support access to the non-extended configuration in pcie_rd_conf_wa()
123 if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) in pcie_wr_conf()
151 * Check whether to apply Orion-1/Orion-NAS PCIe config in pcie_setup()
[all …]
/linux/drivers/mtd/nand/raw/
H A Dau1550nd.c1 // SPDX-License-Identifier: GPL-2.0-only
15 #include <asm/mach-au1x00/au1000.h>
16 #include <asm/mach-au1x00/au1550nd.h>
23 int cs; member
33 * au_write_buf - write buffer to chip
36 * @len: number of bytes to write
48 writeb(p[i], ctx->base + MEM_STNAND_DATA); in au_write_buf()
54 * au_read_buf - read chip data into buffer
57 * @len: number of bytes to read
69 p[i] = readb(ctx->base + MEM_STNAND_DATA); in au_read_buf()
[all …]
/linux/Documentation/devicetree/bindings/gpio/
H A Dst,spear-spics-gpio.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/st,spear-spics-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ST Microelectronics SPEAr SPI CS GPIO Controller
10 - Viresh Kumar <vireshk@kernel.org>
27 const: st,spear-spics-gpio
32 gpio-controller: true
34 '#gpio-cells':
37 st-spics,peripcfg-reg:
[all …]
/linux/drivers/bus/
H A Dqcom-ebi2.c1 // SPDX-License-Identifier: GPL-2.0-only
41 * Bits 31-28: RECOVERY recovery cycles (0 = 1, 1 = 2 etc) this is the time the
42 * memory continues to drive the data bus after OE is de-asserted.
43 * Inserted when reading one CS and switching to another CS or read
44 * followed by write on the same CS. Valid values 0 thru 15.
45 * Bits 27-24: WR_HOLD write hold cycles, these are extra cycles inserted after
47 * asserted until CS is asserted. With a hold of 1, the CS stays
49 * Bits 23-16: WR_DELTA initial latency for write cycles inserted for the first
51 * Bits 15-8: RD_DELTA initial latency for read cycles inserted for the first
53 * Bits 7-4: WR_WAIT number of wait cycles for every write access, 0=1 cycle
[all …]

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