Lines Matching +full:cs +full:- +full:number
1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/spi/spi-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Mark Brown <broonie@kernel.org>
20 pattern: "^spi(@.*|-([0-9]|[1-9][0-9]+))?$"
22 "#address-cells":
25 "#size-cells":
28 cs-gpios:
31 If that property is used, the number of chip selects will be
32 increased automatically with max(cs-gpios, hardware chip selects).
34 So if, for example, the controller has 4 CS lines, and the
35 cs-gpios looks like this
36 cs-gpios = <&gpio1 0 0>, <0>, <&gpio1 1 0>, <&gpio1 2 0>;
49 cs-gpio with the optional spi-cs-high flag for SPI slaves.
51 Each table entry defines how the CS pin is to be physically
54 device node | cs-gpio | CS pin state active | Note
56 spi-cs-high | - | H |
57 - | - | L |
58 spi-cs-high | ACTIVE_HIGH | H |
59 - | ACTIVE_HIGH | L | 1
60 spi-cs-high | ACTIVE_LOW | H | 2
61 - | ACTIVE_LOW | L |
68 because ACTIVE_LOW is overridden by spi-cs-high.
70 spi-cs-high + ACTIVE_HIGH.
72 fifo-depth:
77 rx-fifo-depth:
82 tx-fifo-depth:
87 num-cs:
90 Total number of chip selects.
92 spi-slave:
106 - compatible
109 "^.*@[0-9a-f]+$":
111 $ref: spi-peripheral-props.yaml
115 spi-3wire:
118 The device requires 3-wire mode.
120 spi-cpha:
125 spi-cpol:
131 - compatible
132 - reg
135 rx-fifo-depth: [ tx-fifo-depth ]
136 tx-fifo-depth: [ rx-fifo-depth ]
139 - if:
142 - spi-slave
145 "#address-cells":
149 "#address-cells":
151 - not:
153 - fifo-depth
154 - rx-fifo-depth
155 - not:
157 - fifo-depth
158 - tx-fifo-depth
163 - |
165 #address-cells = <1>;
166 #size-cells = <0>;
167 compatible = "fsl,imx28-spi";
171 dma-names = "rx-tx";
175 spi-max-frequency = <1000000>;
181 spi-max-frequency = <100000>;
186 compatible = "jedec,spi-nor";
187 spi-max-frequency = <50000000>;
189 stacked-memories = /bits/ 64 <0x10000000 0x10000000>;