1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/spi/spi-cadence.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Cadence SPI controller 8 9maintainers: 10 - Michal Simek <michal.simek@amd.com> 11 12allOf: 13 - $ref: spi-controller.yaml# 14 15properties: 16 compatible: 17 enum: 18 - cdns,spi-r1p6 19 - xlnx,zynq-spi-r1p6 20 21 reg: 22 maxItems: 1 23 24 interrupts: 25 maxItems: 1 26 27 clock-names: 28 items: 29 - const: ref_clk 30 - const: pclk 31 32 clocks: 33 maxItems: 2 34 35 num-cs: 36 description: | 37 Number of chip selects used. If a decoder is used, 38 this will be the number of chip selects after the 39 decoder. 40 $ref: /schemas/types.yaml#/definitions/uint32 41 minimum: 1 42 maximum: 4 43 default: 4 44 45 is-decoded-cs: 46 description: | 47 Flag to indicate whether decoder is used or not. 48 $ref: /schemas/types.yaml#/definitions/uint32 49 enum: [ 0, 1 ] 50 default: 0 51 52 power-domains: 53 maxItems: 1 54 55 label: 56 description: Descriptive name of the SPI controller. 57 58 resets: 59 maxItems: 1 60 61 reset-names: 62 items: 63 - const: spi 64 65required: 66 - compatible 67 - reg 68 - interrupts 69 - clock-names 70 - clocks 71 72unevaluatedProperties: false 73 74examples: 75 - | 76 spi@e0007000 { 77 compatible = "xlnx,zynq-spi-r1p6"; 78 clock-names = "ref_clk", "pclk"; 79 clocks = <&clkc 26>, <&clkc 35>; 80 interrupt-parent = <&intc>; 81 interrupts = <0 49 4>; 82 num-cs = <4>; 83 is-decoded-cs = <0>; 84 reg = <0xe0007000 0x1000>; 85 }; 86... 87