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/freebsd/sys/contrib/device-tree/Bindings/soc/altera/
H A Daltr,sys-mgr.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/altera/altr,sys-mgr.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dinh Nguyen <dinguyen@kernel.org>
15 - description: Cyclone5/Arria5/Arria10
16 const: altr,sys-mgr
17 - description: Stratix10 SoC
19 - const: altr,sys-mgr-s10
20 - const: altr,sys-mgr
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/freebsd/sys/contrib/device-tree/Bindings/arm/altera/
H A Dsocfpga-system.txt4 - compatible : "altr,sys-mgr"
5 - reg : Should contain 1 register ranges(address and length)
6 - cpu1-start-addr : CPU1 start address in hex.
10 compatible = "altr,sys-mgr";
12 cpu1-start-addr = <0xffd080c4>;
15 ARM64 - Stratix10
17 - compatible : "altr,sys-mgr-s10"
18 - reg : Should contain 1 register range(address and length)
23 compatible = "altr,sys-mgr-s10";
/freebsd/sys/contrib/device-tree/src/arm64/altera/
H A Dsocfpga_stratix10_swvp.dts1 // SPDX-License-Identifier: GPL-2.0
10 compatible = "altr,socfpga-stratix10-swvp", "altr,socfpga-stratix10";
27 stdout-path = "serial1:115200n8";
28 linux,initrd-start = <0x10000000>;
29 linux,initrd-end = <0x125c8324>;
39 enable-method = "spin-table";
40 cpu-release-addr = <0x0 0x0000fff8>;
43 &cpu1 {
44 enable-method = "spin-table";
45 cpu-release-addr = <0x0 0x0000fff8>;
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/freebsd/sys/contrib/device-tree/src/arm/intel/socfpga/
H A Dsocfpga_arria5.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
16 clock-frequency = <25000000>;
22 broken-cd;
23 bus-width = <4>;
24 cap-mmc-highspeed;
25 cap-sd-highspeed;
26 clk-phase-sd-hs = <0>, <135>;
30 cpu1-start-addr = <0xffd080c4>;
H A Dsocfpga_cyclone5.dtsi1 // SPDX-License-Identifier: GPL-2.0+
6 /dts-v1/;
16 clock-frequency = <25000000>;
22 broken-cd;
23 bus-width = <4>;
24 cap-mmc-highspeed;
25 cap-sd-highspeed;
26 clk-phase-sd-hs = <0>, <135>;
30 cpu1-start-addr = <0xffd080c4>;
H A Dsocfpga_vt.dts1 // SPDX-License-Identifier: GPL-2.0+
6 /dts-v1/;
11 compatible = "altr,socfpga-vt", "altr,socfpga";
27 clock-frequency = <10000000>;
33 broken-cd;
34 bus-width = <4>;
35 cap-mmc-highspeed;
36 cap-sd-highspeed;
40 phy-mode = "gmii";
45 clock-frequency = <7000000>;
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H A Dsocfpga_arria10.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/reset/altr,rst-mgr-a10.h>
10 #address-cells = <1>;
11 #size-cells = <1>;
14 #address-cells = <1>;
15 #size-cells = <0>;
16 enable-method = "altr,socfpga-a10-smp";
19 compatible = "arm,cortex-a9";
22 next-level-cache = <&L2>;
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/freebsd/sys/contrib/dev/iwlwifi/fw/
H A Dpaging.c1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
3 * Copyright (C) 2012-2014, 2018-2019, 2021, 2025 Intel Corporation
4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH
5 * Copyright (C) 2016-2017 Intel Deutschland GmbH
7 #include "iwl-drv.h"
15 if (!fwrt->fw_paging_db[0].fw_paging_block) in iwl_free_fw_paging()
19 struct iwl_fw_paging *paging = &fwrt->fw_paging_db[i]; in iwl_free_fw_paging()
21 if (!paging->fw_paging_block) { in iwl_free_fw_paging()
28 dma_unmap_page(fwrt->trans->dev, paging->fw_paging_phys, in iwl_free_fw_paging()
29 paging->fw_paging_size, DMA_BIDIRECTIONAL); in iwl_free_fw_paging()
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/freebsd/sys/arm64/coresight/
H A Dcoresight_etm4x.c1 /*-
2 * Copyright (c) 2018-2020 Ruslan Bukin <br@bsdpad.com>
7 * FA8650-15-C-7558 ("CADETS"), as part of the DARPA Transparent Computing
57 * CPU0 -> ETM0 -> funnel1 -> funnel0 -> ETF -> replicator -> ETR -> DRAM
58 * CPU1 -> ETM1 -> funnel1 -^
59 * CPU2 -> ETM2 -> funnel1 -^
60 * CPU3 -> ETM3 -> funnel1 -^
65 { -1, 0 }
87 bus_write_4(sc->res, TRCCONFIGR, reg); in etm_prepare()
90 bus_write_4(sc->res, TRCEVENTCTL0R, 0); in etm_prepare()
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/freebsd/sys/contrib/device-tree/src/arm/broadcom/
H A Dbcm2711.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/soc/bcm2835-pm.h>
10 #address-cells = <2>;
11 #size-cells = <1>;
13 interrupt-parent = <&gicv2>;
16 compatible = "brcm,bcm2711-vc5";
20 clk_27MHz: clk-27M {
21 #clock-cells = <0>;
22 compatible = "fixed-clock";
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/freebsd/sys/contrib/device-tree/src/arm/nvidia/
H A Dtegra20-paz00.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/input.h>
5 #include <dt-bindings/thermal/thermal.h>
8 #include "tegra20-cpu-opp.dtsi"
9 #include "tegra20-cpu-opp-microvolt.dtsi"
25 stdout-path = "serial0:115200n8";
44 vdd-supply = <&hdmi_vdd_reg>;
45 pll-supply = <&hdmi_pll_reg>;
47 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
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H A Dtegra30-asus-transformer-common.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include <dt-bindings/input/gpio-keys.h>
4 #include <dt-bindings/input/input.h>
5 #include <dt-bindings/thermal/thermal.h>
8 #include "tegra30-cpu-opp.dtsi"
9 #include "tegra30-cp
1501 cpu1: cpu@1 { global() label
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H A Dtegra30-lg-x3.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include <dt-bindings/input/gpio-keys.h>
4 #include <dt-bindings/input/input.h>
5 #include <dt-bindings/leds/common.h>
6 #include <dt-bindings/mfd/max77620.h>
7 #include <dt-bindings/thermal/thermal.h>
10 #include "tegra30-cpu-opp.dtsi"
11 #include "tegra30-cpu-opp-microvolt.dtsi"
14 chassis-type = "handset";
30 * pre-existing /chosen node to be available to insert the
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H A Dtegra30-asus-p1801-t.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/gpio-keys.h>
5 #include <dt-bindings/input/input.h>
6 #include <dt-bindings/thermal/thermal.h>
9 #include "tegra30-cpu-opp.dtsi"
10 #include "tegra30-cpu-opp-microvolt.dtsi"
13 model = "Asus Portable AiO P1801-T";
14 compatible = "asus,p1801-t", "nvidia,tegra30";
15 chassis-type = "convertible";
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H A Dtegra30-asus-tf600t.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/gpio-keys.h>
5 #include <dt-bindings/input/input.h>
6 #include <dt-bindings/leds/common.h>
7 #include <dt-bindings/thermal/thermal.h>
10 #include "tegra30-cpu-opp.dtsi"
11 #include "tegra30-cpu-opp-microvolt.dtsi"
16 chassis-type = "convertible";
34 * pre-existing /chosen node to be available to insert the
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H A Dtegra30-pegatron-chagall.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/gpio-keys.h>
5 #include <dt-bindings/input/input.h>
6 #include <dt-bindings/thermal/thermal.h>
9 #include "tegra30-cpu-opp.dtsi"
10 #include "tegra30-cpu-opp-microvolt.dtsi"
11 #include "tegra30-asus-lvds-display.dtsi"
16 chassis-type = "tablet";
35 * pre-existing /chosen node to be available to insert the
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/freebsd/sys/contrib/device-tree/src/arm/samsung/
H A Dexynos4212-tab3.dtsi1 // SPDX-License-Identifier: GPL-2.0
9 /dts-v1/;
11 #include "exynos4412-ppmu-common.dtsi"
12 #include "exynos-mfc-reserved-memory.dtsi"
13 #include <dt-bindings/clock/samsung,s2mps11.h>
14 #include <dt-bindings/gpio/gpio.h>
15 #include <dt-bindings/leds/common.h>
16 #include <dt-bindings/input/gpio-keys.h>
17 #include <dt-bindings/input/input.h>
18 #include <dt-bindings/interrupt-controller/irq.h>
[all …]
/freebsd/sys/contrib/dev/iwlwifi/pcie/gen1_2/
H A Dtrans.c1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
3 * Copyright (C) 2007-2015, 2018-2024 Intel Corporation
4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH
5 * Copyright (C) 2016-2017 Intel Deutschland GmbH
22 #include "iwl-drv.h"
23 #include "iwl-trans.h"
24 #include "iwl-csr.h"
25 #include "iwl-prph.h"
26 #include "iwl-scd.h"
27 #include "iwl-agn-hw.h"
[all …]
/freebsd/sys/contrib/ncsw/inc/cores/
H A De500v2_ext.h2 * Copyright 2008-2012 Freescale Semiconductor Inc.
67 uint32_t L1DCache_LineLock(uint32_t addr);
68 uint32_t L1ICache_LineLock(uint32_t addr);
205 @param[in] mode - L2 cache mode: data only, instruction only or instruction and data.
210 not possible to call this routine for i-cache and than to call
211 again for d-cache; The second call will override the first one.
252 @param[in] mode - L2 cache mode: support data & instruction only.
257 not possible to call this routine for i-cache and than to call
258 again for d-cache; The second call will override the first one.
358 @Retval TRUE - Tasklets are supported.
[all …]
/freebsd/sys/dev/iwm/
H A Dif_iwm.c20 /*-
21 * Based on BSD-licensed source modules in the Linux iwlwifi driver,
34 * Copyright(c) 2007 - 2013 Intel Corporation. All rights reserved.
55 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
60 * Copyright(c) 2005 - 2013 Intel Corporation. All rights reserved.
90 /*-
91 * Copyright (c) 2007-2010 Damien Bergamini <damien.bergamini@free.fr>
173 #define mtodoff(m, t, off) ((t)((m)->m_data + (off)))
230 #define IWM_RIDX_MAX (nitems(iwm_rates)-1)
440 dlen < sizeof(l->size) + l->size * sizeof(*l->cs)) in iwm_store_cscheme()
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