1*01950c46SEmmanuel Vadot// SPDX-License-Identifier: GPL-2.0 2*01950c46SEmmanuel Vadot 3*01950c46SEmmanuel Vadot#include <dt-bindings/input/gpio-keys.h> 4*01950c46SEmmanuel Vadot#include <dt-bindings/input/input.h> 5*01950c46SEmmanuel Vadot#include <dt-bindings/leds/common.h> 6*01950c46SEmmanuel Vadot#include <dt-bindings/mfd/max77620.h> 7*01950c46SEmmanuel Vadot#include <dt-bindings/thermal/thermal.h> 8*01950c46SEmmanuel Vadot 9*01950c46SEmmanuel Vadot#include "tegra30.dtsi" 10*01950c46SEmmanuel Vadot#include "tegra30-cpu-opp.dtsi" 11*01950c46SEmmanuel Vadot#include "tegra30-cpu-opp-microvolt.dtsi" 12*01950c46SEmmanuel Vadot 13*01950c46SEmmanuel Vadot/ { 14*01950c46SEmmanuel Vadot chassis-type = "handset"; 15*01950c46SEmmanuel Vadot 16*01950c46SEmmanuel Vadot aliases { 17*01950c46SEmmanuel Vadot mmc0 = &sdmmc4; /* eMMC */ 18*01950c46SEmmanuel Vadot mmc1 = &sdmmc1; /* WiFi */ 19*01950c46SEmmanuel Vadot 20*01950c46SEmmanuel Vadot rtc0 = &pmic; 21*01950c46SEmmanuel Vadot rtc1 = "/rtc@7000e000"; 22*01950c46SEmmanuel Vadot 23*01950c46SEmmanuel Vadot serial0 = &uartd; /* Console */ 24*01950c46SEmmanuel Vadot serial1 = &uartc; /* Bluetooth */ 25*01950c46SEmmanuel Vadot serial2 = &uartb; /* GPS */ 26*01950c46SEmmanuel Vadot }; 27*01950c46SEmmanuel Vadot 28*01950c46SEmmanuel Vadot /* 29*01950c46SEmmanuel Vadot * The decompressor and also some bootloaders rely on a 30*01950c46SEmmanuel Vadot * pre-existing /chosen node to be available to insert the 31*01950c46SEmmanuel Vadot * command line and merge other ATAGS info. 32*01950c46SEmmanuel Vadot */ 33*01950c46SEmmanuel Vadot chosen { }; 34*01950c46SEmmanuel Vadot 35*01950c46SEmmanuel Vadot firmware { 36*01950c46SEmmanuel Vadot trusted-foundations { 37*01950c46SEmmanuel Vadot compatible = "tlm,trusted-foundations"; 38*01950c46SEmmanuel Vadot tlm,version-major = <2>; 39*01950c46SEmmanuel Vadot tlm,version-minor = <8>; 40*01950c46SEmmanuel Vadot }; 41*01950c46SEmmanuel Vadot }; 42*01950c46SEmmanuel Vadot 43*01950c46SEmmanuel Vadot memory@80000000 { 44*01950c46SEmmanuel Vadot reg = <0x80000000 0x40000000>; 45*01950c46SEmmanuel Vadot }; 46*01950c46SEmmanuel Vadot 47*01950c46SEmmanuel Vadot reserved-memory { 48*01950c46SEmmanuel Vadot #address-cells = <1>; 49*01950c46SEmmanuel Vadot #size-cells = <1>; 50*01950c46SEmmanuel Vadot ranges; 51*01950c46SEmmanuel Vadot 52*01950c46SEmmanuel Vadot linux,cma@80000000 { 53*01950c46SEmmanuel Vadot compatible = "shared-dma-pool"; 54*01950c46SEmmanuel Vadot alloc-ranges = <0x80000000 0x30000000>; 55*01950c46SEmmanuel Vadot size = <0x10000000>; /* 256MiB */ 56*01950c46SEmmanuel Vadot linux,cma-default; 57*01950c46SEmmanuel Vadot reusable; 58*01950c46SEmmanuel Vadot }; 59*01950c46SEmmanuel Vadot 60*01950c46SEmmanuel Vadot ramoops@bed00000 { 61*01950c46SEmmanuel Vadot compatible = "ramoops"; 62*01950c46SEmmanuel Vadot reg = <0xbed00000 0x10000>; /* 64kB */ 63*01950c46SEmmanuel Vadot console-size = <0x8000>; /* 32kB */ 64*01950c46SEmmanuel Vadot record-size = <0x400>; /* 1kB */ 65*01950c46SEmmanuel Vadot ecc-size = <16>; 66*01950c46SEmmanuel Vadot }; 67*01950c46SEmmanuel Vadot 68*01950c46SEmmanuel Vadot trustzone@bfe00000 { 69*01950c46SEmmanuel Vadot reg = <0xbfe00000 0x200000>; /* 2MB */ 70*01950c46SEmmanuel Vadot no-map; 71*01950c46SEmmanuel Vadot }; 72*01950c46SEmmanuel Vadot }; 73*01950c46SEmmanuel Vadot 74*01950c46SEmmanuel Vadot vde@6001a000 { 75*01950c46SEmmanuel Vadot assigned-clocks = <&tegra_car TEGRA30_CLK_VDE>; 76*01950c46SEmmanuel Vadot assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_P>; 77*01950c46SEmmanuel Vadot assigned-clock-rates = <408000000>; 78*01950c46SEmmanuel Vadot }; 79*01950c46SEmmanuel Vadot 80*01950c46SEmmanuel Vadot pinmux@70000868 { 81*01950c46SEmmanuel Vadot pinctrl-names = "default"; 82*01950c46SEmmanuel Vadot pinctrl-0 = <&state_default>; 83*01950c46SEmmanuel Vadot 84*01950c46SEmmanuel Vadot state_default: pinmux { 85*01950c46SEmmanuel Vadot /* WLAN SDIO pinmux */ 86*01950c46SEmmanuel Vadot sdmmc1-clk { 87*01950c46SEmmanuel Vadot nvidia,pins = "sdmmc1_clk_pz0"; 88*01950c46SEmmanuel Vadot nvidia,function = "sdmmc1"; 89*01950c46SEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 90*01950c46SEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 91*01950c46SEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_ENABLE>; 92*01950c46SEmmanuel Vadot }; 93*01950c46SEmmanuel Vadot sdmmc1-cmd { 94*01950c46SEmmanuel Vadot nvidia,pins = "sdmmc1_cmd_pz1", 95*01950c46SEmmanuel Vadot "sdmmc1_dat3_py4", 96*01950c46SEmmanuel Vadot "sdmmc1_dat2_py5", 97*01950c46SEmmanuel Vadot "sdmmc1_dat1_py6", 98*01950c46SEmmanuel Vadot "sdmmc1_dat0_py7"; 99*01950c46SEmmanuel Vadot nvidia,function = "sdmmc1"; 100*01950c46SEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_UP>; 101*01950c46SEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 102*01950c46SEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_ENABLE>; 103*01950c46SEmmanuel Vadot }; 104*01950c46SEmmanuel Vadot wlan-reset { 105*01950c46SEmmanuel Vadot nvidia,pins = "pv3"; 106*01950c46SEmmanuel Vadot nvidia,function = "rsvd2"; 107*01950c46SEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 108*01950c46SEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 109*01950c46SEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_DISABLE>; 110*01950c46SEmmanuel Vadot }; 111*01950c46SEmmanuel Vadot wlan-host-wake { 112*01950c46SEmmanuel Vadot nvidia,pins = "pu6"; 113*01950c46SEmmanuel Vadot nvidia,function = "pwm3"; 114*01950c46SEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 115*01950c46SEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 116*01950c46SEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_ENABLE>; 117*01950c46SEmmanuel Vadot }; 118*01950c46SEmmanuel Vadot 119*01950c46SEmmanuel Vadot /* GNSS UART-B pinmux */ 120*01950c46SEmmanuel Vadot gps-pwr-en { 121*01950c46SEmmanuel Vadot nvidia,pins = "kb_row6_pr6"; 122*01950c46SEmmanuel Vadot nvidia,function = "kbc"; 123*01950c46SEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 124*01950c46SEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 125*01950c46SEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_DISABLE>; 126*01950c46SEmmanuel Vadot }; 127*01950c46SEmmanuel Vadot gps-ldo-en { 128*01950c46SEmmanuel Vadot nvidia,pins = "ulpi_dir_py1"; 129*01950c46SEmmanuel Vadot nvidia,function = "rsvd2"; 130*01950c46SEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 131*01950c46SEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 132*01950c46SEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_DISABLE>; 133*01950c46SEmmanuel Vadot }; 134*01950c46SEmmanuel Vadot gps-clk-ref { 135*01950c46SEmmanuel Vadot nvidia,pins = "gmi_ad8_ph0"; 136*01950c46SEmmanuel Vadot nvidia,function = "gmi"; 137*01950c46SEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 138*01950c46SEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 139*01950c46SEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_DISABLE>; 140*01950c46SEmmanuel Vadot }; 141*01950c46SEmmanuel Vadot 142*01950c46SEmmanuel Vadot /* Bluetooth UART-C pinmux */ 143*01950c46SEmmanuel Vadot uartc-cts-rxd { 144*01950c46SEmmanuel Vadot nvidia,pins = "uart3_cts_n_pa1", 145*01950c46SEmmanuel Vadot "uart3_rxd_pw7"; 146*01950c46SEmmanuel Vadot nvidia,function = "uartc"; 147*01950c46SEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 148*01950c46SEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 149*01950c46SEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_ENABLE>; 150*01950c46SEmmanuel Vadot }; 151*01950c46SEmmanuel Vadot uartc-rts-txd { 152*01950c46SEmmanuel Vadot nvidia,pins = "uart3_rts_n_pc0", 153*01950c46SEmmanuel Vadot "uart3_txd_pw6"; 154*01950c46SEmmanuel Vadot nvidia,function = "uartc"; 155*01950c46SEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 156*01950c46SEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 157*01950c46SEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_DISABLE>; 158*01950c46SEmmanuel Vadot }; 159*01950c46SEmmanuel Vadot bt-reset { 160*01950c46SEmmanuel Vadot nvidia,pins = "clk2_req_pcc5"; 161*01950c46SEmmanuel Vadot nvidia,function = "dap"; 162*01950c46SEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 163*01950c46SEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 164*01950c46SEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_DISABLE>; 165*01950c46SEmmanuel Vadot }; 166*01950c46SEmmanuel Vadot bt-dev-wake { 167*01950c46SEmmanuel Vadot nvidia,pins = "kb_row11_ps3"; 168*01950c46SEmmanuel Vadot nvidia,function = "kbc"; 169*01950c46SEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 170*01950c46SEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 171*01950c46SEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_DISABLE>; 172*01950c46SEmmanuel Vadot }; 173*01950c46SEmmanuel Vadot bt-host-wake { 174*01950c46SEmmanuel Vadot nvidia,pins = "kb_row12_ps4"; 175*01950c46SEmmanuel Vadot nvidia,function = "kbc"; 176*01950c46SEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 177*01950c46SEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 178*01950c46SEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_ENABLE>; 179*01950c46SEmmanuel Vadot }; 180*01950c46SEmmanuel Vadot bt-pcm-dap4 { 181*01950c46SEmmanuel Vadot nvidia,pins = "dap4_fs_pp4", 182*01950c46SEmmanuel Vadot "dap4_din_pp5", 183*01950c46SEmmanuel Vadot "dap4_dout_pp6", 184*01950c46SEmmanuel Vadot "dap4_sclk_pp7"; 185*01950c46SEmmanuel Vadot nvidia,function = "i2s3"; 186*01950c46SEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 187*01950c46SEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 188*01950c46SEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_ENABLE>; 189*01950c46SEmmanuel Vadot }; 190*01950c46SEmmanuel Vadot 191*01950c46SEmmanuel Vadot /* EMMC pinmux */ 192*01950c46SEmmanuel Vadot sdmmc4-clk { 193*01950c46SEmmanuel Vadot nvidia,pins = "sdmmc4_clk_pcc4"; 194*01950c46SEmmanuel Vadot nvidia,function = "sdmmc4"; 195*01950c46SEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 196*01950c46SEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 197*01950c46SEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_ENABLE>; 198*01950c46SEmmanuel Vadot }; 199*01950c46SEmmanuel Vadot sdmmc4-data { 200*01950c46SEmmanuel Vadot nvidia,pins = "sdmmc4_cmd_pt7", 201*01950c46SEmmanuel Vadot "sdmmc4_dat0_paa0", 202*01950c46SEmmanuel Vadot "sdmmc4_dat1_paa1", 203*01950c46SEmmanuel Vadot "sdmmc4_dat2_paa2", 204*01950c46SEmmanuel Vadot "sdmmc4_dat3_paa3", 205*01950c46SEmmanuel Vadot "sdmmc4_dat4_paa4", 206*01950c46SEmmanuel Vadot "sdmmc4_dat5_paa5", 207*01950c46SEmmanuel Vadot "sdmmc4_dat6_paa6", 208*01950c46SEmmanuel Vadot "sdmmc4_dat7_paa7"; 209*01950c46SEmmanuel Vadot nvidia,function = "sdmmc4"; 210*01950c46SEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_UP>; 211*01950c46SEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 212*01950c46SEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_ENABLE>; 213*01950c46SEmmanuel Vadot }; 214*01950c46SEmmanuel Vadot sdmmc4-reset { 215*01950c46SEmmanuel Vadot nvidia,pins = "sdmmc4_rst_n_pcc3"; 216*01950c46SEmmanuel Vadot nvidia,function = "rsvd2"; 217*01950c46SEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 218*01950c46SEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 219*01950c46SEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_ENABLE>; 220*01950c46SEmmanuel Vadot }; 221*01950c46SEmmanuel Vadot 222*01950c46SEmmanuel Vadot /* I2C pinmux */ 223*01950c46SEmmanuel Vadot gen1-i2c { 224*01950c46SEmmanuel Vadot nvidia,pins = "gen1_i2c_scl_pc4", 225*01950c46SEmmanuel Vadot "gen1_i2c_sda_pc5"; 226*01950c46SEmmanuel Vadot nvidia,function = "i2c1"; 227*01950c46SEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 228*01950c46SEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 229*01950c46SEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_ENABLE>; 230*01950c46SEmmanuel Vadot nvidia,open-drain = <TEGRA_PIN_ENABLE>; 231*01950c46SEmmanuel Vadot nvidia,lock = <TEGRA_PIN_DISABLE>; 232*01950c46SEmmanuel Vadot }; 233*01950c46SEmmanuel Vadot gen2-i2c { 234*01950c46SEmmanuel Vadot nvidia,pins = "gen2_i2c_scl_pt5", 235*01950c46SEmmanuel Vadot "gen2_i2c_sda_pt6"; 236*01950c46SEmmanuel Vadot nvidia,function = "i2c2"; 237*01950c46SEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 238*01950c46SEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 239*01950c46SEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_ENABLE>; 240*01950c46SEmmanuel Vadot nvidia,open-drain = <TEGRA_PIN_ENABLE>; 241*01950c46SEmmanuel Vadot nvidia,lock = <TEGRA_PIN_DISABLE>; 242*01950c46SEmmanuel Vadot }; 243*01950c46SEmmanuel Vadot cam-i2c { 244*01950c46SEmmanuel Vadot nvidia,pins = "cam_i2c_scl_pbb1", 245*01950c46SEmmanuel Vadot "cam_i2c_sda_pbb2"; 246*01950c46SEmmanuel Vadot nvidia,function = "i2c3"; 247*01950c46SEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 248*01950c46SEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 249*01950c46SEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_ENABLE>; 250*01950c46SEmmanuel Vadot nvidia,open-drain = <TEGRA_PIN_ENABLE>; 251*01950c46SEmmanuel Vadot nvidia,lock = <TEGRA_PIN_DISABLE>; 252*01950c46SEmmanuel Vadot }; 253*01950c46SEmmanuel Vadot ddc-i2c { 254*01950c46SEmmanuel Vadot nvidia,pins = "ddc_scl_pv4", 255*01950c46SEmmanuel Vadot "ddc_sda_pv5"; 256*01950c46SEmmanuel Vadot nvidia,function = "i2c4"; 257*01950c46SEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 258*01950c46SEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 259*01950c46SEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_ENABLE>; 260*01950c46SEmmanuel Vadot nvidia,lock = <TEGRA_PIN_DISABLE>; 261*01950c46SEmmanuel Vadot }; 262*01950c46SEmmanuel Vadot pwr-i2c { 263*01950c46SEmmanuel Vadot nvidia,pins = "pwr_i2c_scl_pz6", 264*01950c46SEmmanuel Vadot "pwr_i2c_sda_pz7"; 265*01950c46SEmmanuel Vadot nvidia,function = "i2cpwr"; 266*01950c46SEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 267*01950c46SEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 268*01950c46SEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_ENABLE>; 269*01950c46SEmmanuel Vadot nvidia,open-drain = <TEGRA_PIN_ENABLE>; 270*01950c46SEmmanuel Vadot nvidia,lock = <TEGRA_PIN_DISABLE>; 271*01950c46SEmmanuel Vadot }; 272*01950c46SEmmanuel Vadot mhl-i2c { 273*01950c46SEmmanuel Vadot nvidia,pins = "kb_col6_pq6", 274*01950c46SEmmanuel Vadot "kb_col7_pq7"; 275*01950c46SEmmanuel Vadot nvidia,function = "kbc"; 276*01950c46SEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 277*01950c46SEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 278*01950c46SEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_ENABLE>; 279*01950c46SEmmanuel Vadot }; 280*01950c46SEmmanuel Vadot 281*01950c46SEmmanuel Vadot /* GPIO keys pinmux */ 282*01950c46SEmmanuel Vadot power-key { 283*01950c46SEmmanuel Vadot nvidia,pins = "gmi_wp_n_pc7"; 284*01950c46SEmmanuel Vadot nvidia,function = "gmi"; 285*01950c46SEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_UP>; 286*01950c46SEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 287*01950c46SEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_ENABLE>; 288*01950c46SEmmanuel Vadot }; 289*01950c46SEmmanuel Vadot volume-down { 290*01950c46SEmmanuel Vadot nvidia,pins = "ulpi_data3_po4"; 291*01950c46SEmmanuel Vadot nvidia,function = "spi3"; 292*01950c46SEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_UP>; 293*01950c46SEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 294*01950c46SEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_ENABLE>; 295*01950c46SEmmanuel Vadot }; 296*01950c46SEmmanuel Vadot 297*01950c46SEmmanuel Vadot /* Sensors pinmux */ 298*01950c46SEmmanuel Vadot sen-vdd { 299*01950c46SEmmanuel Vadot nvidia,pins = "spi1_miso_px7"; 300*01950c46SEmmanuel Vadot nvidia,function = "rsvd4"; 301*01950c46SEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 302*01950c46SEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 303*01950c46SEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_DISABLE>; 304*01950c46SEmmanuel Vadot }; 305*01950c46SEmmanuel Vadot proxi-vdd { 306*01950c46SEmmanuel Vadot nvidia,pins = "spi2_miso_px1"; 307*01950c46SEmmanuel Vadot nvidia,function = "gmi"; 308*01950c46SEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 309*01950c46SEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 310*01950c46SEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_DISABLE>; 311*01950c46SEmmanuel Vadot }; 312*01950c46SEmmanuel Vadot sen-vio { 313*01950c46SEmmanuel Vadot nvidia,pins = "lcd_dc1_pd2"; 314*01950c46SEmmanuel Vadot nvidia,function = "rsvd4"; 315*01950c46SEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 316*01950c46SEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 317*01950c46SEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_DISABLE>; 318*01950c46SEmmanuel Vadot }; 319*01950c46SEmmanuel Vadot nct-irq { 320*01950c46SEmmanuel Vadot nvidia,pins = "gmi_iordy_pi5"; 321*01950c46SEmmanuel Vadot nvidia,function = "rsvd1"; 322*01950c46SEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 323*01950c46SEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 324*01950c46SEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_ENABLE>; 325*01950c46SEmmanuel Vadot }; 326*01950c46SEmmanuel Vadot bat-irq { 327*01950c46SEmmanuel Vadot nvidia,pins = "kb_row8_ps0"; 328*01950c46SEmmanuel Vadot nvidia,function = "kbc"; 329*01950c46SEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_UP>; 330*01950c46SEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 331*01950c46SEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_ENABLE>; 332*01950c46SEmmanuel Vadot }; 333*01950c46SEmmanuel Vadot charger-irq { 334*01950c46SEmmanuel Vadot nvidia,pins = "gmi_cs1_n_pj2"; 335*01950c46SEmmanuel Vadot nvidia,function = "rsvd1"; 336*01950c46SEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_UP>; 337*01950c46SEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 338*01950c46SEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_ENABLE>; 339*01950c46SEmmanuel Vadot }; 340*01950c46SEmmanuel Vadot mpu-irq { 341*01950c46SEmmanuel Vadot nvidia,pins = "gmi_ad12_ph4"; 342*01950c46SEmmanuel Vadot nvidia,function = "rsvd1"; 343*01950c46SEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_UP>; 344*01950c46SEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 345*01950c46SEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_ENABLE>; 346*01950c46SEmmanuel Vadot }; 347*01950c46SEmmanuel Vadot compass-irq { 348*01950c46SEmmanuel Vadot nvidia,pins = "gmi_ad13_ph5"; 349*01950c46SEmmanuel Vadot nvidia,function = "rsvd1"; 350*01950c46SEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_UP>; 351*01950c46SEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 352*01950c46SEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_ENABLE>; 353*01950c46SEmmanuel Vadot }; 354*01950c46SEmmanuel Vadot light-irq { 355*01950c46SEmmanuel Vadot nvidia,pins = "gmi_cs4_n_pk2"; 356*01950c46SEmmanuel Vadot nvidia,function = "rsvd1"; 357*01950c46SEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_UP>; 358*01950c46SEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 359*01950c46SEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_ENABLE>; 360*01950c46SEmmanuel Vadot }; 361*01950c46SEmmanuel Vadot 362*01950c46SEmmanuel Vadot /* LED pinmux */ 363*01950c46SEmmanuel Vadot backlight-en { 364*01950c46SEmmanuel Vadot nvidia,pins = "lcd_dc0_pn6"; 365*01950c46SEmmanuel Vadot nvidia,function = "rsvd3"; 366*01950c46SEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 367*01950c46SEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 368*01950c46SEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_DISABLE>; 369*01950c46SEmmanuel Vadot }; 370*01950c46SEmmanuel Vadot flash-led-en { 371*01950c46SEmmanuel Vadot nvidia,pins = "pbb3"; 372*01950c46SEmmanuel Vadot nvidia,function = "vgp3"; 373*01950c46SEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 374*01950c46SEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 375*01950c46SEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_DISABLE>; 376*01950c46SEmmanuel Vadot }; 377*01950c46SEmmanuel Vadot keypad-led { 378*01950c46SEmmanuel Vadot nvidia,pins = "kb_row2_pr2", 379*01950c46SEmmanuel Vadot "kb_row3_pr3"; 380*01950c46SEmmanuel Vadot nvidia,function = "rsvd3"; 381*01950c46SEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 382*01950c46SEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 383*01950c46SEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_DISABLE>; 384*01950c46SEmmanuel Vadot }; 385*01950c46SEmmanuel Vadot 386*01950c46SEmmanuel Vadot /* NFC pinmux */ 387*01950c46SEmmanuel Vadot nfc-irq { 388*01950c46SEmmanuel Vadot nvidia,pins = "spi2_cs1_n_pw2"; 389*01950c46SEmmanuel Vadot nvidia,function = "spi2"; 390*01950c46SEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 391*01950c46SEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 392*01950c46SEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_ENABLE>; 393*01950c46SEmmanuel Vadot }; 394*01950c46SEmmanuel Vadot nfc-ven { 395*01950c46SEmmanuel Vadot nvidia,pins = "spi1_sck_px5"; 396*01950c46SEmmanuel Vadot nvidia,function = "spi1"; 397*01950c46SEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 398*01950c46SEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 399*01950c46SEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_DISABLE>; 400*01950c46SEmmanuel Vadot }; 401*01950c46SEmmanuel Vadot nfc-firm { 402*01950c46SEmmanuel Vadot nvidia,pins = "kb_row0_pr0"; 403*01950c46SEmmanuel Vadot nvidia,function = "rsvd4"; 404*01950c46SEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 405*01950c46SEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 406*01950c46SEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_DISABLE>; 407*01950c46SEmmanuel Vadot }; 408*01950c46SEmmanuel Vadot 409*01950c46SEmmanuel Vadot /* DC pinmux */ 410*01950c46SEmmanuel Vadot lcd-pwr { 411*01950c46SEmmanuel Vadot nvidia,pins = "lcd_pwr0_pb2", 412*01950c46SEmmanuel Vadot "lcd_pwr1_pc1"; 413*01950c46SEmmanuel Vadot nvidia,function = "displaya"; 414*01950c46SEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 415*01950c46SEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 416*01950c46SEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_DISABLE>; 417*01950c46SEmmanuel Vadot }; 418*01950c46SEmmanuel Vadot lcd-wr-n { 419*01950c46SEmmanuel Vadot nvidia,pins = "lcd_wr_n_pz3"; 420*01950c46SEmmanuel Vadot nvidia,function = "displaya"; 421*01950c46SEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 422*01950c46SEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 423*01950c46SEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_ENABLE>; 424*01950c46SEmmanuel Vadot }; 425*01950c46SEmmanuel Vadot lcd-id { 426*01950c46SEmmanuel Vadot nvidia,pins = "lcd_m1_pw1"; 427*01950c46SEmmanuel Vadot nvidia,function = "displaya"; 428*01950c46SEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 429*01950c46SEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_ENABLE>; 430*01950c46SEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_DISABLE>; 431*01950c46SEmmanuel Vadot }; 432*01950c46SEmmanuel Vadot lcd-pclk { 433*01950c46SEmmanuel Vadot nvidia,pins = "lcd_pclk_pb3", 434*01950c46SEmmanuel Vadot "lcd_de_pj1", 435*01950c46SEmmanuel Vadot "lcd_hsync_pj3", 436*01950c46SEmmanuel Vadot "lcd_vsync_pj4"; 437*01950c46SEmmanuel Vadot nvidia,function = "displaya"; 438*01950c46SEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 439*01950c46SEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 440*01950c46SEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_ENABLE>; 441*01950c46SEmmanuel Vadot }; 442*01950c46SEmmanuel Vadot lcd-rgb-blue { 443*01950c46SEmmanuel Vadot nvidia,pins = "lcd_d0_pe0", 444*01950c46SEmmanuel Vadot "lcd_d1_pe1", 445*01950c46SEmmanuel Vadot "lcd_d2_pe2", 446*01950c46SEmmanuel Vadot "lcd_d3_pe3", 447*01950c46SEmmanuel Vadot "lcd_d4_pe4", 448*01950c46SEmmanuel Vadot "lcd_d5_pe5", 449*01950c46SEmmanuel Vadot "lcd_d18_pm2", 450*01950c46SEmmanuel Vadot "lcd_d19_pm3"; 451*01950c46SEmmanuel Vadot nvidia,function = "displaya"; 452*01950c46SEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 453*01950c46SEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 454*01950c46SEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_ENABLE>; 455*01950c46SEmmanuel Vadot }; 456*01950c46SEmmanuel Vadot lcd-rgb-green { 457*01950c46SEmmanuel Vadot nvidia,pins = "lcd_d6_pe6", 458*01950c46SEmmanuel Vadot "lcd_d7_pe7", 459*01950c46SEmmanuel Vadot "lcd_d8_pf0", 460*01950c46SEmmanuel Vadot "lcd_d9_pf1", 461*01950c46SEmmanuel Vadot "lcd_d10_pf2", 462*01950c46SEmmanuel Vadot "lcd_d11_pf3", 463*01950c46SEmmanuel Vadot "lcd_d20_pm4", 464*01950c46SEmmanuel Vadot "lcd_d21_pm5"; 465*01950c46SEmmanuel Vadot nvidia,function = "displaya"; 466*01950c46SEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 467*01950c46SEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 468*01950c46SEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_ENABLE>; 469*01950c46SEmmanuel Vadot }; 470*01950c46SEmmanuel Vadot lcd-rgb-red { 471*01950c46SEmmanuel Vadot nvidia,pins = "lcd_d12_pf4", 472*01950c46SEmmanuel Vadot "lcd_d13_pf5", 473*01950c46SEmmanuel Vadot "lcd_d14_pf6", 474*01950c46SEmmanuel Vadot "lcd_d15_pf7", 475*01950c46SEmmanuel Vadot "lcd_d16_pm0", 476*01950c46SEmmanuel Vadot "lcd_d17_pm1", 477*01950c46SEmmanuel Vadot "lcd_d22_pm6", 478*01950c46SEmmanuel Vadot "lcd_d23_pm7"; 479*01950c46SEmmanuel Vadot nvidia,function = "displaya"; 480*01950c46SEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 481*01950c46SEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 482*01950c46SEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_ENABLE>; 483*01950c46SEmmanuel Vadot }; 484*01950c46SEmmanuel Vadot 485*01950c46SEmmanuel Vadot /* Bridge pinmux */ 486*01950c46SEmmanuel Vadot bridge-reset { 487*01950c46SEmmanuel Vadot nvidia,pins = "ulpi_data1_po2"; 488*01950c46SEmmanuel Vadot nvidia,function = "spi3"; 489*01950c46SEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_UP>; 490*01950c46SEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 491*01950c46SEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_DISABLE>; 492*01950c46SEmmanuel Vadot }; 493*01950c46SEmmanuel Vadot rgb-ic-en { 494*01950c46SEmmanuel Vadot nvidia,pins = "gmi_a18_pb1"; 495*01950c46SEmmanuel Vadot nvidia,function = "uartd"; 496*01950c46SEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 497*01950c46SEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 498*01950c46SEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_DISABLE>; 499*01950c46SEmmanuel Vadot }; 500*01950c46SEmmanuel Vadot bridge-clk { 501*01950c46SEmmanuel Vadot nvidia,pins = "clk3_out_pee0"; 502*01950c46SEmmanuel Vadot nvidia,function = "extperiph3"; 503*01950c46SEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 504*01950c46SEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 505*01950c46SEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_ENABLE>; 506*01950c46SEmmanuel Vadot }; 507*01950c46SEmmanuel Vadot rgb-bridge { 508*01950c46SEmmanuel Vadot nvidia,pins = "lcd_sdin_pz2", 509*01950c46SEmmanuel Vadot "lcd_sdout_pn5", 510*01950c46SEmmanuel Vadot "lcd_cs0_n_pn4", 511*01950c46SEmmanuel Vadot "lcd_sck_pz4"; 512*01950c46SEmmanuel Vadot nvidia,function = "spi5"; 513*01950c46SEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 514*01950c46SEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 515*01950c46SEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_ENABLE>; 516*01950c46SEmmanuel Vadot }; 517*01950c46SEmmanuel Vadot 518*01950c46SEmmanuel Vadot /* Panel pinmux */ 519*01950c46SEmmanuel Vadot panel-reset { 520*01950c46SEmmanuel Vadot nvidia,pins = "lcd_cs1_n_pw0"; 521*01950c46SEmmanuel Vadot nvidia,function = "rsvd4"; 522*01950c46SEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_UP>; 523*01950c46SEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 524*01950c46SEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_DISABLE>; 525*01950c46SEmmanuel Vadot }; 526*01950c46SEmmanuel Vadot panel-vio { 527*01950c46SEmmanuel Vadot nvidia,pins = "ulpi_clk_py0"; 528*01950c46SEmmanuel Vadot nvidia,function = "rsvd2"; 529*01950c46SEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 530*01950c46SEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 531*01950c46SEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_DISABLE>; 532*01950c46SEmmanuel Vadot }; 533*01950c46SEmmanuel Vadot 534*01950c46SEmmanuel Vadot /* Touchscreen pinmux */ 535*01950c46SEmmanuel Vadot touch-vdd { 536*01950c46SEmmanuel Vadot nvidia,pins = "kb_col1_pq1"; 537*01950c46SEmmanuel Vadot nvidia,function = "kbc"; 538*01950c46SEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 539*01950c46SEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 540*01950c46SEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_DISABLE>; 541*01950c46SEmmanuel Vadot }; 542*01950c46SEmmanuel Vadot touch-vio { 543*01950c46SEmmanuel Vadot nvidia,pins = "spi1_mosi_px4"; 544*01950c46SEmmanuel Vadot nvidia,function = "spi2"; 545*01950c46SEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 546*01950c46SEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 547*01950c46SEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_DISABLE>; 548*01950c46SEmmanuel Vadot }; 549*01950c46SEmmanuel Vadot touch-irq-n { 550*01950c46SEmmanuel Vadot nvidia,pins = "kb_col3_pq3"; 551*01950c46SEmmanuel Vadot nvidia,function = "kbc"; 552*01950c46SEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 553*01950c46SEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 554*01950c46SEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_ENABLE>; 555*01950c46SEmmanuel Vadot }; 556*01950c46SEmmanuel Vadot touch-rst-n { 557*01950c46SEmmanuel Vadot nvidia,pins = "ulpi_data0_po1"; 558*01950c46SEmmanuel Vadot nvidia,function = "spi3"; 559*01950c46SEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_UP>; 560*01950c46SEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_ENABLE>; 561*01950c46SEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_DISABLE>; 562*01950c46SEmmanuel Vadot }; 563*01950c46SEmmanuel Vadot touch-maker-id { 564*01950c46SEmmanuel Vadot nvidia,pins = "kb_col2_pq2"; 565*01950c46SEmmanuel Vadot nvidia,function = "kbc"; 566*01950c46SEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_UP>; 567*01950c46SEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 568*01950c46SEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_ENABLE>; 569*01950c46SEmmanuel Vadot }; 570*01950c46SEmmanuel Vadot 571*01950c46SEmmanuel Vadot /* MHL pinmux */ 572*01950c46SEmmanuel Vadot mhl-vio { 573*01950c46SEmmanuel Vadot nvidia,pins = "pv2"; 574*01950c46SEmmanuel Vadot nvidia,function = "owr"; 575*01950c46SEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 576*01950c46SEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 577*01950c46SEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_DISABLE>; 578*01950c46SEmmanuel Vadot }; 579*01950c46SEmmanuel Vadot mhl-rst-n { 580*01950c46SEmmanuel Vadot nvidia,pins = "clk3_req_pee1"; 581*01950c46SEmmanuel Vadot nvidia,function = "dev3"; 582*01950c46SEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_UP>; 583*01950c46SEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 584*01950c46SEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_DISABLE>; 585*01950c46SEmmanuel Vadot }; 586*01950c46SEmmanuel Vadot mhl-irq { 587*01950c46SEmmanuel Vadot nvidia,pins = "crt_vsync_pv7"; 588*01950c46SEmmanuel Vadot nvidia,function = "rsvd2"; 589*01950c46SEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 590*01950c46SEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 591*01950c46SEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_ENABLE>; 592*01950c46SEmmanuel Vadot }; 593*01950c46SEmmanuel Vadot mhl-sel { 594*01950c46SEmmanuel Vadot nvidia,pins = "kb_row10_ps2"; 595*01950c46SEmmanuel Vadot nvidia,function = "kbc"; 596*01950c46SEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 597*01950c46SEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 598*01950c46SEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_DISABLE>; 599*01950c46SEmmanuel Vadot }; 600*01950c46SEmmanuel Vadot hdmi-hpd { 601*01950c46SEmmanuel Vadot nvidia,pins = "hdmi_int_pn7"; 602*01950c46SEmmanuel Vadot nvidia,function = "hdmi"; 603*01950c46SEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 604*01950c46SEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_ENABLE>; 605*01950c46SEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_ENABLE>; 606*01950c46SEmmanuel Vadot }; 607*01950c46SEmmanuel Vadot 608*01950c46SEmmanuel Vadot /* AUDIO pinmux */ 609*01950c46SEmmanuel Vadot hp-detect { 610*01950c46SEmmanuel Vadot nvidia,pins = "pbb6"; 611*01950c46SEmmanuel Vadot nvidia,function = "vgp6"; 612*01950c46SEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 613*01950c46SEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 614*01950c46SEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_ENABLE>; 615*01950c46SEmmanuel Vadot }; 616*01950c46SEmmanuel Vadot hp-hook { 617*01950c46SEmmanuel Vadot nvidia,pins = "ulpi_data4_po5"; 618*01950c46SEmmanuel Vadot nvidia,function = "ulpi"; 619*01950c46SEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 620*01950c46SEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 621*01950c46SEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_ENABLE>; 622*01950c46SEmmanuel Vadot }; 623*01950c46SEmmanuel Vadot ear-mic-en { 624*01950c46SEmmanuel Vadot nvidia,pins = "spi2_mosi_px0"; 625*01950c46SEmmanuel Vadot nvidia,function = "spi2"; 626*01950c46SEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 627*01950c46SEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 628*01950c46SEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_DISABLE>; 629*01950c46SEmmanuel Vadot }; 630*01950c46SEmmanuel Vadot audio-irq { 631*01950c46SEmmanuel Vadot nvidia,pins = "spi2_cs2_n_pw3"; 632*01950c46SEmmanuel Vadot nvidia,function = "spi3"; 633*01950c46SEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 634*01950c46SEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 635*01950c46SEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_ENABLE>; 636*01950c46SEmmanuel Vadot }; 637*01950c46SEmmanuel Vadot audio-mclk { 638*01950c46SEmmanuel Vadot nvidia,pins = "clk1_out_pw4"; 639*01950c46SEmmanuel Vadot nvidia,function = "extperiph1"; 640*01950c46SEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 641*01950c46SEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 642*01950c46SEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_ENABLE>; 643*01950c46SEmmanuel Vadot }; 644*01950c46SEmmanuel Vadot dap-i2s0 { 645*01950c46SEmmanuel Vadot nvidia,pins = "dap1_fs_pn0", 646*01950c46SEmmanuel Vadot "dap1_din_pn1", 647*01950c46SEmmanuel Vadot "dap1_dout_pn2", 648*01950c46SEmmanuel Vadot "dap1_sclk_pn3"; 649*01950c46SEmmanuel Vadot nvidia,function = "i2s0"; 650*01950c46SEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 651*01950c46SEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 652*01950c46SEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_ENABLE>; 653*01950c46SEmmanuel Vadot }; 654*01950c46SEmmanuel Vadot dap-i2s1 { 655*01950c46SEmmanuel Vadot nvidia,pins = "dap2_fs_pa2", 656*01950c46SEmmanuel Vadot "dap2_sclk_pa3", 657*01950c46SEmmanuel Vadot "dap2_din_pa4", 658*01950c46SEmmanuel Vadot "dap2_dout_pa5"; 659*01950c46SEmmanuel Vadot nvidia,function = "i2s1"; 660*01950c46SEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 661*01950c46SEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 662*01950c46SEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_ENABLE>; 663*01950c46SEmmanuel Vadot }; 664*01950c46SEmmanuel Vadot 665*01950c46SEmmanuel Vadot /* MUIC pinmux */ 666*01950c46SEmmanuel Vadot muic-irq { 667*01950c46SEmmanuel Vadot nvidia,pins = "gmi_cs0_n_pj0"; 668*01950c46SEmmanuel Vadot nvidia,function = "gmi"; 669*01950c46SEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_UP>; 670*01950c46SEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 671*01950c46SEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_ENABLE>; 672*01950c46SEmmanuel Vadot }; 673*01950c46SEmmanuel Vadot muic-dp2t { 674*01950c46SEmmanuel Vadot nvidia,pins = "pcc2"; 675*01950c46SEmmanuel Vadot nvidia,function = "rsvd2"; 676*01950c46SEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 677*01950c46SEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 678*01950c46SEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_DISABLE>; 679*01950c46SEmmanuel Vadot }; 680*01950c46SEmmanuel Vadot muic-usif { 681*01950c46SEmmanuel Vadot nvidia,pins = "ulpi_stp_py3"; 682*01950c46SEmmanuel Vadot nvidia,function = "spi1"; 683*01950c46SEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 684*01950c46SEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 685*01950c46SEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_DISABLE>; 686*01950c46SEmmanuel Vadot }; 687*01950c46SEmmanuel Vadot ifx-usb-vbus-en { 688*01950c46SEmmanuel Vadot nvidia,pins = "kb_row4_pr4"; 689*01950c46SEmmanuel Vadot nvidia,function = "rsvd4"; 690*01950c46SEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 691*01950c46SEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 692*01950c46SEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_DISABLE>; 693*01950c46SEmmanuel Vadot }; 694*01950c46SEmmanuel Vadot pcb-rev { 695*01950c46SEmmanuel Vadot nvidia,pins = "gmi_wait_pi7", 696*01950c46SEmmanuel Vadot "gmi_rst_n_pi4"; 697*01950c46SEmmanuel Vadot nvidia,function = "gmi"; 698*01950c46SEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_UP>; 699*01950c46SEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 700*01950c46SEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_ENABLE>; 701*01950c46SEmmanuel Vadot }; 702*01950c46SEmmanuel Vadot jtag-rtck { 703*01950c46SEmmanuel Vadot nvidia,pins = "jtag_rtck_pu7"; 704*01950c46SEmmanuel Vadot nvidia,function = "rtck"; 705*01950c46SEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 706*01950c46SEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 707*01950c46SEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_DISABLE>; 708*01950c46SEmmanuel Vadot }; 709*01950c46SEmmanuel Vadot 710*01950c46SEmmanuel Vadot /* Camera pinmux */ 711*01950c46SEmmanuel Vadot cam-mclk { 712*01950c46SEmmanuel Vadot nvidia,pins = "cam_mclk_pcc0"; 713*01950c46SEmmanuel Vadot nvidia,function = "vi_alt3"; 714*01950c46SEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_UP>; 715*01950c46SEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 716*01950c46SEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_ENABLE>; 717*01950c46SEmmanuel Vadot }; 718*01950c46SEmmanuel Vadot cam-pmic-en { 719*01950c46SEmmanuel Vadot nvidia,pins = "pbb4"; 720*01950c46SEmmanuel Vadot nvidia,function = "vgp4"; 721*01950c46SEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 722*01950c46SEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 723*01950c46SEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_DISABLE>; 724*01950c46SEmmanuel Vadot }; 725*01950c46SEmmanuel Vadot front-cam-rst { 726*01950c46SEmmanuel Vadot nvidia,pins = "pbb5"; 727*01950c46SEmmanuel Vadot nvidia,function = "vgp5"; 728*01950c46SEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 729*01950c46SEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 730*01950c46SEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_DISABLE>; 731*01950c46SEmmanuel Vadot }; 732*01950c46SEmmanuel Vadot front-cam-vio { 733*01950c46SEmmanuel Vadot nvidia,pins = "ulpi_nxt_py2"; 734*01950c46SEmmanuel Vadot nvidia,function = "rsvd2"; 735*01950c46SEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 736*01950c46SEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 737*01950c46SEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_DISABLE>; 738*01950c46SEmmanuel Vadot }; 739*01950c46SEmmanuel Vadot rear-cam-rst { 740*01950c46SEmmanuel Vadot nvidia,pins = "gmi_cs3_n_pk4"; 741*01950c46SEmmanuel Vadot nvidia,function = "rsvd1"; 742*01950c46SEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 743*01950c46SEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 744*01950c46SEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_DISABLE>; 745*01950c46SEmmanuel Vadot }; 746*01950c46SEmmanuel Vadot rear-cam-eprom-pr { 747*01950c46SEmmanuel Vadot nvidia,pins = "gmi_cs2_n_pk3"; 748*01950c46SEmmanuel Vadot nvidia,function = "rsvd1"; 749*01950c46SEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 750*01950c46SEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 751*01950c46SEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_DISABLE>; 752*01950c46SEmmanuel Vadot }; 753*01950c46SEmmanuel Vadot rear-cam-vcm-pwdn { 754*01950c46SEmmanuel Vadot nvidia,pins = "kb_row1_pr1"; 755*01950c46SEmmanuel Vadot nvidia,function = "kbc"; 756*01950c46SEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_UP>; 757*01950c46SEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 758*01950c46SEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_ENABLE>; 759*01950c46SEmmanuel Vadot }; 760*01950c46SEmmanuel Vadot 761*01950c46SEmmanuel Vadot /* Haptic pinmux */ 762*01950c46SEmmanuel Vadot haptic-en { 763*01950c46SEmmanuel Vadot nvidia,pins = "gmi_ad9_ph1"; 764*01950c46SEmmanuel Vadot nvidia,function = "gmi"; 765*01950c46SEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 766*01950c46SEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 767*01950c46SEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_DISABLE>; 768*01950c46SEmmanuel Vadot }; 769*01950c46SEmmanuel Vadot haptic-osc { 770*01950c46SEmmanuel Vadot nvidia,pins = "gmi_ad11_ph3"; 771*01950c46SEmmanuel Vadot nvidia,function = "pwm3"; 772*01950c46SEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 773*01950c46SEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 774*01950c46SEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_DISABLE>; 775*01950c46SEmmanuel Vadot }; 776*01950c46SEmmanuel Vadot 777*01950c46SEmmanuel Vadot /* Modem pinmux */ 778*01950c46SEmmanuel Vadot cp2ap-ack1-host-active { 779*01950c46SEmmanuel Vadot nvidia,pins = "pu5"; 780*01950c46SEmmanuel Vadot nvidia,function = "rsvd4"; 781*01950c46SEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 782*01950c46SEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 783*01950c46SEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_DISABLE>; 784*01950c46SEmmanuel Vadot }; 785*01950c46SEmmanuel Vadot cp2ap-ack2-host-wakeup { 786*01950c46SEmmanuel Vadot nvidia,pins = "pv0"; 787*01950c46SEmmanuel Vadot nvidia,function = "rsvd4"; 788*01950c46SEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_UP>; 789*01950c46SEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 790*01950c46SEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_ENABLE>; 791*01950c46SEmmanuel Vadot }; 792*01950c46SEmmanuel Vadot ap2cp-ack2-suspend-req { 793*01950c46SEmmanuel Vadot nvidia,pins = "kb_row14_ps6"; 794*01950c46SEmmanuel Vadot nvidia,function = "kbc"; 795*01950c46SEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 796*01950c46SEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 797*01950c46SEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_ENABLE>; 798*01950c46SEmmanuel Vadot }; 799*01950c46SEmmanuel Vadot ap2cp-ack1-slave-wakeup { 800*01950c46SEmmanuel Vadot nvidia,pins = "kb_row15_ps7"; 801*01950c46SEmmanuel Vadot nvidia,function = "kbc"; 802*01950c46SEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 803*01950c46SEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 804*01950c46SEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_DISABLE>; 805*01950c46SEmmanuel Vadot }; 806*01950c46SEmmanuel Vadot cp-kkp { 807*01950c46SEmmanuel Vadot nvidia,pins = "kb_col0_pq0"; 808*01950c46SEmmanuel Vadot nvidia,function = "kbc"; 809*01950c46SEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_UP>; 810*01950c46SEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 811*01950c46SEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_ENABLE>; 812*01950c46SEmmanuel Vadot }; 813*01950c46SEmmanuel Vadot cp-crash-irq { 814*01950c46SEmmanuel Vadot nvidia,pins = "kb_row13_ps5"; 815*01950c46SEmmanuel Vadot nvidia,function = "kbc"; 816*01950c46SEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_UP>; 817*01950c46SEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 818*01950c46SEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_ENABLE>; 819*01950c46SEmmanuel Vadot }; 820*01950c46SEmmanuel Vadot ap2cp-uarta-tx-ipc { 821*01950c46SEmmanuel Vadot nvidia,pins = "pu0"; 822*01950c46SEmmanuel Vadot nvidia,function = "uarta"; 823*01950c46SEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 824*01950c46SEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 825*01950c46SEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_DISABLE>; 826*01950c46SEmmanuel Vadot }; 827*01950c46SEmmanuel Vadot ap2cp-uarta-rx-ipc { 828*01950c46SEmmanuel Vadot nvidia,pins = "pu1"; 829*01950c46SEmmanuel Vadot nvidia,function = "uarta"; 830*01950c46SEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 831*01950c46SEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 832*01950c46SEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_ENABLE>; 833*01950c46SEmmanuel Vadot }; 834*01950c46SEmmanuel Vadot fota-ap-cts-cp-rts { 835*01950c46SEmmanuel Vadot nvidia,pins = "pu2"; 836*01950c46SEmmanuel Vadot nvidia,function = "uarta"; 837*01950c46SEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 838*01950c46SEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_ENABLE>; 839*01950c46SEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_ENABLE>; 840*01950c46SEmmanuel Vadot }; 841*01950c46SEmmanuel Vadot fota-ap-rts-cp-cts { 842*01950c46SEmmanuel Vadot nvidia,pins = "pu3"; 843*01950c46SEmmanuel Vadot nvidia,function = "uarta"; 844*01950c46SEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 845*01950c46SEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_ENABLE>; 846*01950c46SEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_ENABLE>; 847*01950c46SEmmanuel Vadot }; 848*01950c46SEmmanuel Vadot modem-enable { 849*01950c46SEmmanuel Vadot nvidia,pins = "ulpi_data7_po0"; 850*01950c46SEmmanuel Vadot nvidia,function = "hsi"; 851*01950c46SEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 852*01950c46SEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 853*01950c46SEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_DISABLE>; 854*01950c46SEmmanuel Vadot }; 855*01950c46SEmmanuel Vadot modem-reset { 856*01950c46SEmmanuel Vadot nvidia,pins = "pv1"; 857*01950c46SEmmanuel Vadot nvidia,function = "rsvd1"; 858*01950c46SEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 859*01950c46SEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 860*01950c46SEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_DISABLE>; 861*01950c46SEmmanuel Vadot }; 862*01950c46SEmmanuel Vadot dap-i2s2 { 863*01950c46SEmmanuel Vadot nvidia,pins = "dap3_fs_pp0", 864*01950c46SEmmanuel Vadot "dap3_din_pp1", 865*01950c46SEmmanuel Vadot "dap3_dout_pp2", 866*01950c46SEmmanuel Vadot "dap3_sclk_pp3"; 867*01950c46SEmmanuel Vadot nvidia,function = "i2s2"; 868*01950c46SEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 869*01950c46SEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 870*01950c46SEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_ENABLE>; 871*01950c46SEmmanuel Vadot }; 872*01950c46SEmmanuel Vadot 873*01950c46SEmmanuel Vadot /* GPIO power/drive control */ 874*01950c46SEmmanuel Vadot drive-i2c { 875*01950c46SEmmanuel Vadot nvidia,pins = "drive_dbg", 876*01950c46SEmmanuel Vadot "drive_at5", 877*01950c46SEmmanuel Vadot "drive_gme", 878*01950c46SEmmanuel Vadot "drive_ddc", 879*01950c46SEmmanuel Vadot "drive_ao1"; 880*01950c46SEmmanuel Vadot nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>; 881*01950c46SEmmanuel Vadot nvidia,schmitt = <TEGRA_PIN_ENABLE>; 882*01950c46SEmmanuel Vadot nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>; 883*01950c46SEmmanuel Vadot nvidia,pull-down-strength = <31>; 884*01950c46SEmmanuel Vadot nvidia,pull-up-strength = <31>; 885*01950c46SEmmanuel Vadot nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; 886*01950c46SEmmanuel Vadot nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>; 887*01950c46SEmmanuel Vadot }; 888*01950c46SEmmanuel Vadot 889*01950c46SEmmanuel Vadot drive-uart3 { 890*01950c46SEmmanuel Vadot nvidia,pins = "drive_uart3"; 891*01950c46SEmmanuel Vadot nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>; 892*01950c46SEmmanuel Vadot nvidia,schmitt = <TEGRA_PIN_ENABLE>; 893*01950c46SEmmanuel Vadot nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>; 894*01950c46SEmmanuel Vadot nvidia,pull-down-strength = <31>; 895*01950c46SEmmanuel Vadot nvidia,pull-up-strength = <31>; 896*01950c46SEmmanuel Vadot nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; 897*01950c46SEmmanuel Vadot nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>; 898*01950c46SEmmanuel Vadot }; 899*01950c46SEmmanuel Vadot 900*01950c46SEmmanuel Vadot drive-gmi { 901*01950c46SEmmanuel Vadot nvidia,pins = "drive_at3"; 902*01950c46SEmmanuel Vadot nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>; 903*01950c46SEmmanuel Vadot nvidia,schmitt = <TEGRA_PIN_ENABLE>; 904*01950c46SEmmanuel Vadot nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>; 905*01950c46SEmmanuel Vadot nvidia,pull-down-strength = <31>; 906*01950c46SEmmanuel Vadot nvidia,pull-up-strength = <31>; 907*01950c46SEmmanuel Vadot nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; 908*01950c46SEmmanuel Vadot nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>; 909*01950c46SEmmanuel Vadot }; 910*01950c46SEmmanuel Vadot }; 911*01950c46SEmmanuel Vadot }; 912*01950c46SEmmanuel Vadot 913*01950c46SEmmanuel Vadot uartb: serial@70006040 { 914*01950c46SEmmanuel Vadot compatible = "nvidia,tegra30-hsuart"; 915*01950c46SEmmanuel Vadot reset-names = "serial"; 916*01950c46SEmmanuel Vadot /delete-property/ reg-shift; 917*01950c46SEmmanuel Vadot status = "okay"; 918*01950c46SEmmanuel Vadot 919*01950c46SEmmanuel Vadot /* GNSS GSD5T */ 920*01950c46SEmmanuel Vadot }; 921*01950c46SEmmanuel Vadot 922*01950c46SEmmanuel Vadot uartc: serial@70006200 { 923*01950c46SEmmanuel Vadot compatible = "nvidia,tegra30-hsuart"; 924*01950c46SEmmanuel Vadot reset-names = "serial"; 925*01950c46SEmmanuel Vadot /delete-property/ reg-shift; 926*01950c46SEmmanuel Vadot status = "okay"; 927*01950c46SEmmanuel Vadot 928*01950c46SEmmanuel Vadot nvidia,adjust-baud-rates = <0 9600 100>, 929*01950c46SEmmanuel Vadot <9600 115200 200>, 930*01950c46SEmmanuel Vadot <1000000 4000000 136>; 931*01950c46SEmmanuel Vadot 932*01950c46SEmmanuel Vadot /* BCM4330B1 37.4 MHz Class 1.5 ExtLNA */ 933*01950c46SEmmanuel Vadot bluetooth { 934*01950c46SEmmanuel Vadot compatible = "brcm,bcm4330-bt"; 935*01950c46SEmmanuel Vadot max-speed = <4000000>; 936*01950c46SEmmanuel Vadot 937*01950c46SEmmanuel Vadot clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>; 938*01950c46SEmmanuel Vadot clock-names = "txco"; 939*01950c46SEmmanuel Vadot 940*01950c46SEmmanuel Vadot interrupt-parent = <&gpio>; 941*01950c46SEmmanuel Vadot interrupts = <TEGRA_GPIO(S, 4) IRQ_TYPE_EDGE_RISING>; 942*01950c46SEmmanuel Vadot interrupt-names = "host-wakeup"; 943*01950c46SEmmanuel Vadot 944*01950c46SEmmanuel Vadot device-wakeup-gpios = <&gpio TEGRA_GPIO(S, 3) GPIO_ACTIVE_HIGH>; 945*01950c46SEmmanuel Vadot shutdown-gpios = <&gpio TEGRA_GPIO(CC, 5) GPIO_ACTIVE_HIGH>; 946*01950c46SEmmanuel Vadot 947*01950c46SEmmanuel Vadot vbat-supply = <&vdd_3v3_vbat>; 948*01950c46SEmmanuel Vadot vddio-supply = <&vdd_1v8_vio>; 949*01950c46SEmmanuel Vadot }; 950*01950c46SEmmanuel Vadot }; 951*01950c46SEmmanuel Vadot 952*01950c46SEmmanuel Vadot uartd: serial@70006300 { 953*01950c46SEmmanuel Vadot /delete-property/ dmas; 954*01950c46SEmmanuel Vadot /delete-property/ dma-names; 955*01950c46SEmmanuel Vadot status = "okay"; 956*01950c46SEmmanuel Vadot 957*01950c46SEmmanuel Vadot /* Console */ 958*01950c46SEmmanuel Vadot }; 959*01950c46SEmmanuel Vadot 960*01950c46SEmmanuel Vadot pwm@7000a000 { 961*01950c46SEmmanuel Vadot status = "okay"; 962*01950c46SEmmanuel Vadot }; 963*01950c46SEmmanuel Vadot 964*01950c46SEmmanuel Vadot gen1_i2c: i2c@7000c000 { 965*01950c46SEmmanuel Vadot status = "okay"; 966*01950c46SEmmanuel Vadot clock-frequency = <400000>; 967*01950c46SEmmanuel Vadot 968*01950c46SEmmanuel Vadot /* Aichi AMI306 digital compass */ 969*01950c46SEmmanuel Vadot magnetometer@e { 970*01950c46SEmmanuel Vadot compatible = "asahi-kasei,ak8974"; 971*01950c46SEmmanuel Vadot reg = <0x0e>; 972*01950c46SEmmanuel Vadot 973*01950c46SEmmanuel Vadot interrupt-parent = <&gpio>; 974*01950c46SEmmanuel Vadot interrupts = <TEGRA_GPIO(H, 5) IRQ_TYPE_EDGE_RISING>; 975*01950c46SEmmanuel Vadot 976*01950c46SEmmanuel Vadot avdd-supply = <&vdd_3v0_sen>; 977*01950c46SEmmanuel Vadot dvdd-supply = <&vdd_1v8_vio>; 978*01950c46SEmmanuel Vadot 979*01950c46SEmmanuel Vadot mount-matrix = "-1", "0", "0", 980*01950c46SEmmanuel Vadot "0", "1", "0", 981*01950c46SEmmanuel Vadot "0", "0", "-1"; 982*01950c46SEmmanuel Vadot }; 983*01950c46SEmmanuel Vadot 984*01950c46SEmmanuel Vadot max98089: audio-codec@10 { 985*01950c46SEmmanuel Vadot compatible = "maxim,max98089"; 986*01950c46SEmmanuel Vadot reg = <0x10>; 987*01950c46SEmmanuel Vadot 988*01950c46SEmmanuel Vadot clocks = <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; 989*01950c46SEmmanuel Vadot clock-names = "mclk"; 990*01950c46SEmmanuel Vadot 991*01950c46SEmmanuel Vadot assigned-clocks = <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; 992*01950c46SEmmanuel Vadot assigned-clock-parents = <&tegra_car TEGRA30_CLK_EXTERN1>; 993*01950c46SEmmanuel Vadot }; 994*01950c46SEmmanuel Vadot 995*01950c46SEmmanuel Vadot nfc@28 { 996*01950c46SEmmanuel Vadot compatible = "nxp,pn544-i2c"; 997*01950c46SEmmanuel Vadot reg = <0x28>; 998*01950c46SEmmanuel Vadot 999*01950c46SEmmanuel Vadot interrupt-parent = <&gpio>; 1000*01950c46SEmmanuel Vadot interrupts = <TEGRA_GPIO(W, 2) IRQ_TYPE_EDGE_RISING>; 1001*01950c46SEmmanuel Vadot 1002*01950c46SEmmanuel Vadot enable-gpios = <&gpio TEGRA_GPIO(X, 5) GPIO_ACTIVE_HIGH>; 1003*01950c46SEmmanuel Vadot firmware-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>; 1004*01950c46SEmmanuel Vadot }; 1005*01950c46SEmmanuel Vadot 1006*01950c46SEmmanuel Vadot imu@68 { 1007*01950c46SEmmanuel Vadot compatible = "invensense,mpu6050"; 1008*01950c46SEmmanuel Vadot reg = <0x68>; 1009*01950c46SEmmanuel Vadot 1010*01950c46SEmmanuel Vadot interrupt-parent = <&gpio>; 1011*01950c46SEmmanuel Vadot interrupts = <TEGRA_GPIO(H, 4) IRQ_TYPE_EDGE_RISING>; 1012*01950c46SEmmanuel Vadot 1013*01950c46SEmmanuel Vadot vdd-supply = <&vdd_3v0_sen>; 1014*01950c46SEmmanuel Vadot vddio-supply = <&vdd_1v8_sen>; 1015*01950c46SEmmanuel Vadot 1016*01950c46SEmmanuel Vadot mount-matrix = "1", "0", "0", 1017*01950c46SEmmanuel Vadot "0", "1", "0", 1018*01950c46SEmmanuel Vadot "0", "0", "-1"; 1019*01950c46SEmmanuel Vadot }; 1020*01950c46SEmmanuel Vadot }; 1021*01950c46SEmmanuel Vadot 1022*01950c46SEmmanuel Vadot gen2_i2c: i2c@7000c400 { 1023*01950c46SEmmanuel Vadot status = "okay"; 1024*01950c46SEmmanuel Vadot clock-frequency = <400000>; 1025*01950c46SEmmanuel Vadot 1026*01950c46SEmmanuel Vadot /* Synaptics RMI4 S3203B touchcreen */ 1027*01950c46SEmmanuel Vadot touchscreen@20 { 1028*01950c46SEmmanuel Vadot compatible = "syna,rmi4-i2c"; 1029*01950c46SEmmanuel Vadot reg = <0x20>; 1030*01950c46SEmmanuel Vadot 1031*01950c46SEmmanuel Vadot interrupt-parent = <&gpio>; 1032*01950c46SEmmanuel Vadot interrupts = <TEGRA_GPIO(Q, 3) IRQ_TYPE_EDGE_FALLING>; 1033*01950c46SEmmanuel Vadot 1034*01950c46SEmmanuel Vadot vdd-supply = <&vdd_3v0_touch>; 1035*01950c46SEmmanuel Vadot vio-supply = <&vdd_1v8_touch>; 1036*01950c46SEmmanuel Vadot 1037*01950c46SEmmanuel Vadot syna,reset-delay-ms = <20>; 1038*01950c46SEmmanuel Vadot syna,startup-delay-ms = <200>; 1039*01950c46SEmmanuel Vadot 1040*01950c46SEmmanuel Vadot #address-cells = <1>; 1041*01950c46SEmmanuel Vadot #size-cells = <0>; 1042*01950c46SEmmanuel Vadot 1043*01950c46SEmmanuel Vadot rmi4-f01@1 { 1044*01950c46SEmmanuel Vadot reg = <0x1>; 1045*01950c46SEmmanuel Vadot syna,nosleep-mode = <1>; 1046*01950c46SEmmanuel Vadot }; 1047*01950c46SEmmanuel Vadot 1048*01950c46SEmmanuel Vadot rmi4-f11@11 { 1049*01950c46SEmmanuel Vadot reg = <0x11>; 1050*01950c46SEmmanuel Vadot syna,sensor-type = <1>; 1051*01950c46SEmmanuel Vadot 1052*01950c46SEmmanuel Vadot syna,clip-x-low = <0>; 1053*01950c46SEmmanuel Vadot syna,clip-y-low = <0>; 1054*01950c46SEmmanuel Vadot }; 1055*01950c46SEmmanuel Vadot }; 1056*01950c46SEmmanuel Vadot }; 1057*01950c46SEmmanuel Vadot 1058*01950c46SEmmanuel Vadot cam_i2c: i2c@7000c500 { 1059*01950c46SEmmanuel Vadot status = "okay"; 1060*01950c46SEmmanuel Vadot clock-frequency = <400000>; 1061*01950c46SEmmanuel Vadot 1062*01950c46SEmmanuel Vadot dw9714: coil@c { 1063*01950c46SEmmanuel Vadot compatible = "dongwoon,dw9714"; 1064*01950c46SEmmanuel Vadot reg = <0x0c>; 1065*01950c46SEmmanuel Vadot 1066*01950c46SEmmanuel Vadot enable-gpios = <&gpio TEGRA_GPIO(R, 1) GPIO_ACTIVE_HIGH>; 1067*01950c46SEmmanuel Vadot 1068*01950c46SEmmanuel Vadot vcc-supply = <&vcc_focuser>; 1069*01950c46SEmmanuel Vadot }; 1070*01950c46SEmmanuel Vadot 1071*01950c46SEmmanuel Vadot camera-pmic@7d { 1072*01950c46SEmmanuel Vadot compatible = "ti,lp8720"; 1073*01950c46SEmmanuel Vadot reg = <0x7d>; 1074*01950c46SEmmanuel Vadot 1075*01950c46SEmmanuel Vadot enable-gpios = <&gpio TEGRA_GPIO(BB, 4) GPIO_ACTIVE_HIGH>; 1076*01950c46SEmmanuel Vadot 1077*01950c46SEmmanuel Vadot vt_1v2_front: ldo1 { 1078*01950c46SEmmanuel Vadot regulator-name = "vt_1v2_dig"; 1079*01950c46SEmmanuel Vadot regulator-min-microvolt = <1200000>; 1080*01950c46SEmmanuel Vadot regulator-max-microvolt = <1200000>; 1081*01950c46SEmmanuel Vadot }; 1082*01950c46SEmmanuel Vadot 1083*01950c46SEmmanuel Vadot vt_2v7_front: ldo2 { 1084*01950c46SEmmanuel Vadot regulator-name = "vt_2v7_vana"; 1085*01950c46SEmmanuel Vadot regulator-min-microvolt = <2700000>; 1086*01950c46SEmmanuel Vadot regulator-max-microvolt = <2700000>; 1087*01950c46SEmmanuel Vadot }; 1088*01950c46SEmmanuel Vadot 1089*01950c46SEmmanuel Vadot vdd_2v7_rear: ldo3 { 1090*01950c46SEmmanuel Vadot regulator-name = "8m_2v7_vana"; 1091*01950c46SEmmanuel Vadot regulator-min-microvolt = <2700000>; 1092*01950c46SEmmanuel Vadot regulator-max-microvolt = <2800000>; 1093*01950c46SEmmanuel Vadot }; 1094*01950c46SEmmanuel Vadot 1095*01950c46SEmmanuel Vadot vio_1v8_rear: ldo4 { 1096*01950c46SEmmanuel Vadot regulator-name = "vio_1v8_cam"; 1097*01950c46SEmmanuel Vadot regulator-min-microvolt = <1800000>; 1098*01950c46SEmmanuel Vadot regulator-max-microvolt = <1800000>; 1099*01950c46SEmmanuel Vadot }; 1100*01950c46SEmmanuel Vadot 1101*01950c46SEmmanuel Vadot vcc_focuser: ldo5 { 1102*01950c46SEmmanuel Vadot regulator-name = "8m_2v8_vcm"; 1103*01950c46SEmmanuel Vadot regulator-min-microvolt = <2800000>; 1104*01950c46SEmmanuel Vadot regulator-max-microvolt = <2800000>; 1105*01950c46SEmmanuel Vadot }; 1106*01950c46SEmmanuel Vadot 1107*01950c46SEmmanuel Vadot vdd_1v2_rear: buck { 1108*01950c46SEmmanuel Vadot regulator-name = "8m_1v2_cam"; 1109*01950c46SEmmanuel Vadot regulator-min-microvolt = <1200000>; 1110*01950c46SEmmanuel Vadot regulator-max-microvolt = <1200000>; 1111*01950c46SEmmanuel Vadot }; 1112*01950c46SEmmanuel Vadot }; 1113*01950c46SEmmanuel Vadot }; 1114*01950c46SEmmanuel Vadot 1115*01950c46SEmmanuel Vadot hdmi_ddc: i2c@7000c700 { 1116*01950c46SEmmanuel Vadot status = "okay"; 1117*01950c46SEmmanuel Vadot clock-frequency = <100000>; 1118*01950c46SEmmanuel Vadot }; 1119*01950c46SEmmanuel Vadot 1120*01950c46SEmmanuel Vadot pwr_i2c: i2c@7000d000 { 1121*01950c46SEmmanuel Vadot status = "okay"; 1122*01950c46SEmmanuel Vadot clock-frequency = <400000>; 1123*01950c46SEmmanuel Vadot 1124*01950c46SEmmanuel Vadot pmic: max77663@1c { 1125*01950c46SEmmanuel Vadot compatible = "maxim,max77663"; 1126*01950c46SEmmanuel Vadot reg = <0x1c>; 1127*01950c46SEmmanuel Vadot 1128*01950c46SEmmanuel Vadot interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 1129*01950c46SEmmanuel Vadot #interrupt-cells = <2>; 1130*01950c46SEmmanuel Vadot interrupt-controller; 1131*01950c46SEmmanuel Vadot 1132*01950c46SEmmanuel Vadot #gpio-cells = <2>; 1133*01950c46SEmmanuel Vadot gpio-controller; 1134*01950c46SEmmanuel Vadot 1135*01950c46SEmmanuel Vadot system-power-controller; 1136*01950c46SEmmanuel Vadot 1137*01950c46SEmmanuel Vadot pinctrl-names = "default"; 1138*01950c46SEmmanuel Vadot pinctrl-0 = <&max77663_default>; 1139*01950c46SEmmanuel Vadot 1140*01950c46SEmmanuel Vadot max77663_default: pinmux { 1141*01950c46SEmmanuel Vadot gpio1 { 1142*01950c46SEmmanuel Vadot pins = "gpio1"; 1143*01950c46SEmmanuel Vadot function = "gpio"; 1144*01950c46SEmmanuel Vadot drive-open-drain = <1>; 1145*01950c46SEmmanuel Vadot }; 1146*01950c46SEmmanuel Vadot 1147*01950c46SEmmanuel Vadot gpio4 { 1148*01950c46SEmmanuel Vadot pins = "gpio4"; 1149*01950c46SEmmanuel Vadot function = "32k-out1"; 1150*01950c46SEmmanuel Vadot }; 1151*01950c46SEmmanuel Vadot }; 1152*01950c46SEmmanuel Vadot 1153*01950c46SEmmanuel Vadot fps { 1154*01950c46SEmmanuel Vadot fps0 { 1155*01950c46SEmmanuel Vadot maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>; 1156*01950c46SEmmanuel Vadot }; 1157*01950c46SEmmanuel Vadot 1158*01950c46SEmmanuel Vadot fps1 { 1159*01950c46SEmmanuel Vadot maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN1>; 1160*01950c46SEmmanuel Vadot }; 1161*01950c46SEmmanuel Vadot 1162*01950c46SEmmanuel Vadot fps2 { 1163*01950c46SEmmanuel Vadot maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>; 1164*01950c46SEmmanuel Vadot }; 1165*01950c46SEmmanuel Vadot }; 1166*01950c46SEmmanuel Vadot 1167*01950c46SEmmanuel Vadot regulators { 1168*01950c46SEmmanuel Vadot in-sd0-supply = <&vdd_5v0_vbus>; 1169*01950c46SEmmanuel Vadot in-sd1-supply = <&vdd_5v0_vbus>; 1170*01950c46SEmmanuel Vadot in-sd2-supply = <&vdd_5v0_vbus>; 1171*01950c46SEmmanuel Vadot in-sd3-supply = <&vdd_5v0_vbus>; 1172*01950c46SEmmanuel Vadot 1173*01950c46SEmmanuel Vadot in-ldo0-1-supply = <&vdd_1v8_vio>; 1174*01950c46SEmmanuel Vadot in-ldo2-supply = <&vdd_3v3_vbat>; 1175*01950c46SEmmanuel Vadot in-ldo3-5-supply = <&vdd_3v3_vbat>; 1176*01950c46SEmmanuel Vadot in-ldo4-6-supply = <&vdd_3v3_vbat>; 1177*01950c46SEmmanuel Vadot in-ldo7-8-supply = <&vdd_1v8_vio>; 1178*01950c46SEmmanuel Vadot 1179*01950c46SEmmanuel Vadot vdd_cpu: sd0 { 1180*01950c46SEmmanuel Vadot regulator-name = "vdd_cpu"; 1181*01950c46SEmmanuel Vadot regulator-min-microvolt = <800000>; 1182*01950c46SEmmanuel Vadot regulator-max-microvolt = <1250000>; 1183*01950c46SEmmanuel Vadot regulator-coupled-with = <&vdd_core>; 1184*01950c46SEmmanuel Vadot regulator-coupled-max-spread = <300000>; 1185*01950c46SEmmanuel Vadot regulator-max-step-microvolt = <100000>; 1186*01950c46SEmmanuel Vadot regulator-always-on; 1187*01950c46SEmmanuel Vadot regulator-boot-on; 1188*01950c46SEmmanuel Vadot 1189*01950c46SEmmanuel Vadot nvidia,tegra-cpu-regulator; 1190*01950c46SEmmanuel Vadot maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>; 1191*01950c46SEmmanuel Vadot }; 1192*01950c46SEmmanuel Vadot 1193*01950c46SEmmanuel Vadot vdd_core: sd1 { 1194*01950c46SEmmanuel Vadot regulator-name = "vdd_core"; 1195*01950c46SEmmanuel Vadot regulator-min-microvolt = <950000>; 1196*01950c46SEmmanuel Vadot regulator-max-microvolt = <1350000>; 1197*01950c46SEmmanuel Vadot regulator-coupled-with = <&vdd_cpu>; 1198*01950c46SEmmanuel Vadot regulator-coupled-max-spread = <300000>; 1199*01950c46SEmmanuel Vadot regulator-max-step-microvolt = <100000>; 1200*01950c46SEmmanuel Vadot regulator-always-on; 1201*01950c46SEmmanuel Vadot regulator-boot-on; 1202*01950c46SEmmanuel Vadot 1203*01950c46SEmmanuel Vadot nvidia,tegra-core-regulator; 1204*01950c46SEmmanuel Vadot maxim,active-fps-source = <MAX77620_FPS_SRC_1>; 1205*01950c46SEmmanuel Vadot }; 1206*01950c46SEmmanuel Vadot 1207*01950c46SEmmanuel Vadot vdd_1v8_vio: sd2 { 1208*01950c46SEmmanuel Vadot regulator-name = "vdd_1v8_gen"; 1209*01950c46SEmmanuel Vadot regulator-min-microvolt = <1800000>; 1210*01950c46SEmmanuel Vadot regulator-max-microvolt = <1800000>; 1211*01950c46SEmmanuel Vadot regulator-always-on; 1212*01950c46SEmmanuel Vadot regulator-boot-on; 1213*01950c46SEmmanuel Vadot 1214*01950c46SEmmanuel Vadot maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>; 1215*01950c46SEmmanuel Vadot }; 1216*01950c46SEmmanuel Vadot 1217*01950c46SEmmanuel Vadot sd3 { 1218*01950c46SEmmanuel Vadot regulator-name = "vddio_ddr"; 1219*01950c46SEmmanuel Vadot regulator-min-microvolt = <1200000>; 1220*01950c46SEmmanuel Vadot regulator-max-microvolt = <1200000>; 1221*01950c46SEmmanuel Vadot regulator-always-on; 1222*01950c46SEmmanuel Vadot regulator-boot-on; 1223*01950c46SEmmanuel Vadot 1224*01950c46SEmmanuel Vadot maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>; 1225*01950c46SEmmanuel Vadot }; 1226*01950c46SEmmanuel Vadot 1227*01950c46SEmmanuel Vadot ldo0 { 1228*01950c46SEmmanuel Vadot regulator-name = "avdd_pll"; 1229*01950c46SEmmanuel Vadot regulator-min-microvolt = <1200000>; 1230*01950c46SEmmanuel Vadot regulator-max-microvolt = <1200000>; 1231*01950c46SEmmanuel Vadot regulator-always-on; 1232*01950c46SEmmanuel Vadot regulator-boot-on; 1233*01950c46SEmmanuel Vadot 1234*01950c46SEmmanuel Vadot maxim,active-fps-source = <MAX77620_FPS_SRC_1>; 1235*01950c46SEmmanuel Vadot }; 1236*01950c46SEmmanuel Vadot 1237*01950c46SEmmanuel Vadot ldo1 { 1238*01950c46SEmmanuel Vadot regulator-name = "vdd_ddr_hs"; 1239*01950c46SEmmanuel Vadot regulator-min-microvolt = <1000000>; 1240*01950c46SEmmanuel Vadot regulator-max-microvolt = <1000000>; 1241*01950c46SEmmanuel Vadot regulator-always-on; 1242*01950c46SEmmanuel Vadot regulator-boot-on; 1243*01950c46SEmmanuel Vadot 1244*01950c46SEmmanuel Vadot maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>; 1245*01950c46SEmmanuel Vadot }; 1246*01950c46SEmmanuel Vadot 1247*01950c46SEmmanuel Vadot avdd_3v3_periph: ldo2 { 1248*01950c46SEmmanuel Vadot regulator-name = "avdd_usb"; 1249*01950c46SEmmanuel Vadot regulator-min-microvolt = <3300000>; 1250*01950c46SEmmanuel Vadot regulator-max-microvolt = <3300000>; 1251*01950c46SEmmanuel Vadot 1252*01950c46SEmmanuel Vadot maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>; 1253*01950c46SEmmanuel Vadot }; 1254*01950c46SEmmanuel Vadot 1255*01950c46SEmmanuel Vadot vdd_usd: ldo3 { 1256*01950c46SEmmanuel Vadot regulator-name = "vdd_sdmmc3"; 1257*01950c46SEmmanuel Vadot regulator-min-microvolt = <3000000>; 1258*01950c46SEmmanuel Vadot regulator-max-microvolt = <3000000>; 1259*01950c46SEmmanuel Vadot regulator-always-on; 1260*01950c46SEmmanuel Vadot 1261*01950c46SEmmanuel Vadot maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>; 1262*01950c46SEmmanuel Vadot }; 1263*01950c46SEmmanuel Vadot 1264*01950c46SEmmanuel Vadot ldo4 { 1265*01950c46SEmmanuel Vadot regulator-name = "vdd_rtc"; 1266*01950c46SEmmanuel Vadot regulator-min-microvolt = <1200000>; 1267*01950c46SEmmanuel Vadot regulator-max-microvolt = <1200000>; 1268*01950c46SEmmanuel Vadot regulator-always-on; 1269*01950c46SEmmanuel Vadot regulator-boot-on; 1270*01950c46SEmmanuel Vadot 1271*01950c46SEmmanuel Vadot maxim,active-fps-source = <MAX77620_FPS_SRC_0>; 1272*01950c46SEmmanuel Vadot }; 1273*01950c46SEmmanuel Vadot 1274*01950c46SEmmanuel Vadot vcore_emmc: ldo5 { 1275*01950c46SEmmanuel Vadot regulator-name = "vdd_ddr_rx"; 1276*01950c46SEmmanuel Vadot regulator-min-microvolt = <2850000>; 1277*01950c46SEmmanuel Vadot regulator-max-microvolt = <2850000>; 1278*01950c46SEmmanuel Vadot regulator-always-on; 1279*01950c46SEmmanuel Vadot regulator-boot-on; 1280*01950c46SEmmanuel Vadot 1281*01950c46SEmmanuel Vadot maxim,active-fps-source = <MAX77620_FPS_SRC_0>; 1282*01950c46SEmmanuel Vadot }; 1283*01950c46SEmmanuel Vadot 1284*01950c46SEmmanuel Vadot avdd_1v8_hdmi_pll: ldo6 { 1285*01950c46SEmmanuel Vadot regulator-name = "avdd_osc"; 1286*01950c46SEmmanuel Vadot regulator-min-microvolt = <1800000>; 1287*01950c46SEmmanuel Vadot regulator-max-microvolt = <1800000>; 1288*01950c46SEmmanuel Vadot regulator-always-on; 1289*01950c46SEmmanuel Vadot regulator-boot-on; 1290*01950c46SEmmanuel Vadot 1291*01950c46SEmmanuel Vadot maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>; 1292*01950c46SEmmanuel Vadot }; 1293*01950c46SEmmanuel Vadot 1294*01950c46SEmmanuel Vadot vdd_1v2_mhl: ldo7 { 1295*01950c46SEmmanuel Vadot regulator-name = "vdd_1v2_mhl"; 1296*01950c46SEmmanuel Vadot regulator-min-microvolt = <1050000>; 1297*01950c46SEmmanuel Vadot regulator-max-microvolt = <1250000>; 1298*01950c46SEmmanuel Vadot 1299*01950c46SEmmanuel Vadot maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>; 1300*01950c46SEmmanuel Vadot }; 1301*01950c46SEmmanuel Vadot 1302*01950c46SEmmanuel Vadot ldo8 { 1303*01950c46SEmmanuel Vadot regulator-name = "avdd_dsi_csi"; 1304*01950c46SEmmanuel Vadot regulator-min-microvolt = <1200000>; 1305*01950c46SEmmanuel Vadot regulator-max-microvolt = <1200000>; 1306*01950c46SEmmanuel Vadot 1307*01950c46SEmmanuel Vadot maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>; 1308*01950c46SEmmanuel Vadot }; 1309*01950c46SEmmanuel Vadot }; 1310*01950c46SEmmanuel Vadot }; 1311*01950c46SEmmanuel Vadot 1312*01950c46SEmmanuel Vadot fuel-gauge@36 { 1313*01950c46SEmmanuel Vadot compatible = "maxim,max17043"; 1314*01950c46SEmmanuel Vadot reg = <0x36>; 1315*01950c46SEmmanuel Vadot 1316*01950c46SEmmanuel Vadot interrupt-parent = <&gpio>; 1317*01950c46SEmmanuel Vadot interrupts = <TEGRA_GPIO(S, 0) IRQ_TYPE_EDGE_FALLING>; 1318*01950c46SEmmanuel Vadot 1319*01950c46SEmmanuel Vadot monitored-battery = <&battery>; 1320*01950c46SEmmanuel Vadot 1321*01950c46SEmmanuel Vadot maxim,alert-low-soc-level = <10>; 1322*01950c46SEmmanuel Vadot wakeup-source; 1323*01950c46SEmmanuel Vadot }; 1324*01950c46SEmmanuel Vadot 1325*01950c46SEmmanuel Vadot power-sensor@40 { 1326*01950c46SEmmanuel Vadot compatible = "ti,ina230"; 1327*01950c46SEmmanuel Vadot reg = <0x40>; 1328*01950c46SEmmanuel Vadot 1329*01950c46SEmmanuel Vadot vs-supply = <&vdd_3v0_sen>; 1330*01950c46SEmmanuel Vadot }; 1331*01950c46SEmmanuel Vadot 1332*01950c46SEmmanuel Vadot nct72: temperature-sensor@4c { 1333*01950c46SEmmanuel Vadot compatible = "onnn,nct1008"; 1334*01950c46SEmmanuel Vadot reg = <0x4c>; 1335*01950c46SEmmanuel Vadot 1336*01950c46SEmmanuel Vadot interrupt-parent = <&gpio>; 1337*01950c46SEmmanuel Vadot interrupts = <TEGRA_GPIO(I, 5) IRQ_TYPE_EDGE_FALLING>; 1338*01950c46SEmmanuel Vadot 1339*01950c46SEmmanuel Vadot vcc-supply = <&vdd_3v0_sen>; 1340*01950c46SEmmanuel Vadot #thermal-sensor-cells = <1>; 1341*01950c46SEmmanuel Vadot }; 1342*01950c46SEmmanuel Vadot }; 1343*01950c46SEmmanuel Vadot 1344*01950c46SEmmanuel Vadot i2c-mhl { 1345*01950c46SEmmanuel Vadot compatible = "i2c-gpio"; 1346*01950c46SEmmanuel Vadot 1347*01950c46SEmmanuel Vadot sda-gpios = <&gpio TEGRA_GPIO(Q, 7) (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 1348*01950c46SEmmanuel Vadot scl-gpios = <&gpio TEGRA_GPIO(Q, 6) (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 1349*01950c46SEmmanuel Vadot 1350*01950c46SEmmanuel Vadot i2c-gpio,delay-us = <5>; 1351*01950c46SEmmanuel Vadot 1352*01950c46SEmmanuel Vadot #address-cells = <1>; 1353*01950c46SEmmanuel Vadot #size-cells = <0>; 1354*01950c46SEmmanuel Vadot }; 1355*01950c46SEmmanuel Vadot 1356*01950c46SEmmanuel Vadot spi@7000dc00 { 1357*01950c46SEmmanuel Vadot status = "okay"; 1358*01950c46SEmmanuel Vadot spi-max-frequency = <25000000>; 1359*01950c46SEmmanuel Vadot 1360*01950c46SEmmanuel Vadot /* DSI bridge */ 1361*01950c46SEmmanuel Vadot }; 1362*01950c46SEmmanuel Vadot 1363*01950c46SEmmanuel Vadot pmc@7000e400 { 1364*01950c46SEmmanuel Vadot status = "okay"; 1365*01950c46SEmmanuel Vadot nvidia,invert-interrupt; 1366*01950c46SEmmanuel Vadot nvidia,suspend-mode = <2>; 1367*01950c46SEmmanuel Vadot nvidia,cpu-pwr-good-time = <2000>; 1368*01950c46SEmmanuel Vadot nvidia,cpu-pwr-off-time = <200>; 1369*01950c46SEmmanuel Vadot nvidia,core-pwr-good-time = <3845 3845>; 1370*01950c46SEmmanuel Vadot nvidia,core-pwr-off-time = <0>; 1371*01950c46SEmmanuel Vadot nvidia,core-power-req-active-high; 1372*01950c46SEmmanuel Vadot nvidia,sys-clock-req-active-high; 1373*01950c46SEmmanuel Vadot core-supply = <&vdd_core>; 1374*01950c46SEmmanuel Vadot 1375*01950c46SEmmanuel Vadot i2c-thermtrip { 1376*01950c46SEmmanuel Vadot nvidia,i2c-controller-id = <4>; 1377*01950c46SEmmanuel Vadot nvidia,bus-addr = <0x1c>; 1378*01950c46SEmmanuel Vadot nvidia,reg-addr = <0x41>; 1379*01950c46SEmmanuel Vadot nvidia,reg-data = <0x02>; 1380*01950c46SEmmanuel Vadot }; 1381*01950c46SEmmanuel Vadot }; 1382*01950c46SEmmanuel Vadot 1383*01950c46SEmmanuel Vadot hda@70030000 { 1384*01950c46SEmmanuel Vadot status = "okay"; 1385*01950c46SEmmanuel Vadot }; 1386*01950c46SEmmanuel Vadot 1387*01950c46SEmmanuel Vadot ahub@70080000 { 1388*01950c46SEmmanuel Vadot /* HIFI CODEC */ 1389*01950c46SEmmanuel Vadot i2s@70080300 { /* i2s0 */ 1390*01950c46SEmmanuel Vadot status = "okay"; 1391*01950c46SEmmanuel Vadot }; 1392*01950c46SEmmanuel Vadot 1393*01950c46SEmmanuel Vadot /* BASEBAND */ 1394*01950c46SEmmanuel Vadot i2s@70080500 { /* i2s2 */ 1395*01950c46SEmmanuel Vadot status = "okay"; 1396*01950c46SEmmanuel Vadot }; 1397*01950c46SEmmanuel Vadot 1398*01950c46SEmmanuel Vadot /* BT SCO */ 1399*01950c46SEmmanuel Vadot i2s@70080600 { /* i2s3 */ 1400*01950c46SEmmanuel Vadot status = "okay"; 1401*01950c46SEmmanuel Vadot }; 1402*01950c46SEmmanuel Vadot }; 1403*01950c46SEmmanuel Vadot 1404*01950c46SEmmanuel Vadot sdmmc1: mmc@78000000 { 1405*01950c46SEmmanuel Vadot status = "okay"; 1406*01950c46SEmmanuel Vadot 1407*01950c46SEmmanuel Vadot #address-cells = <1>; 1408*01950c46SEmmanuel Vadot #size-cells = <0>; 1409*01950c46SEmmanuel Vadot 1410*01950c46SEmmanuel Vadot assigned-clocks = <&tegra_car TEGRA30_CLK_SDMMC1>; 1411*01950c46SEmmanuel Vadot assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_C>; 1412*01950c46SEmmanuel Vadot assigned-clock-rates = <50000000>; 1413*01950c46SEmmanuel Vadot 1414*01950c46SEmmanuel Vadot max-frequency = <50000000>; 1415*01950c46SEmmanuel Vadot keep-power-in-suspend; 1416*01950c46SEmmanuel Vadot bus-width = <4>; 1417*01950c46SEmmanuel Vadot non-removable; 1418*01950c46SEmmanuel Vadot 1419*01950c46SEmmanuel Vadot mmc-pwrseq = <&brcm_wifi_pwrseq>; 1420*01950c46SEmmanuel Vadot vmmc-supply = <&vdd_3v3_vbat>; 1421*01950c46SEmmanuel Vadot vqmmc-supply = <&vdd_1v8_vio>; 1422*01950c46SEmmanuel Vadot 1423*01950c46SEmmanuel Vadot /* BCM4330B1 37.4 MHz Class 1.5 ExtLNA */ 1424*01950c46SEmmanuel Vadot wifi@1 { 1425*01950c46SEmmanuel Vadot compatible = "brcm,bcm4329-fmac"; 1426*01950c46SEmmanuel Vadot reg = <1>; 1427*01950c46SEmmanuel Vadot 1428*01950c46SEmmanuel Vadot interrupt-parent = <&gpio>; 1429*01950c46SEmmanuel Vadot interrupts = <TEGRA_GPIO(U, 6) IRQ_TYPE_LEVEL_HIGH>; 1430*01950c46SEmmanuel Vadot interrupt-names = "host-wake"; 1431*01950c46SEmmanuel Vadot }; 1432*01950c46SEmmanuel Vadot }; 1433*01950c46SEmmanuel Vadot 1434*01950c46SEmmanuel Vadot sdmmc4: mmc@78000600 { 1435*01950c46SEmmanuel Vadot status = "okay"; 1436*01950c46SEmmanuel Vadot bus-width = <8>; 1437*01950c46SEmmanuel Vadot 1438*01950c46SEmmanuel Vadot non-removable; 1439*01950c46SEmmanuel Vadot mmc-ddr-1_8v; 1440*01950c46SEmmanuel Vadot 1441*01950c46SEmmanuel Vadot vmmc-supply = <&vcore_emmc>; 1442*01950c46SEmmanuel Vadot vqmmc-supply = <&vdd_1v8_vio>; 1443*01950c46SEmmanuel Vadot }; 1444*01950c46SEmmanuel Vadot 1445*01950c46SEmmanuel Vadot /* Micro USB */ 1446*01950c46SEmmanuel Vadot usb@7d000000 { 1447*01950c46SEmmanuel Vadot compatible = "nvidia,tegra30-udc"; 1448*01950c46SEmmanuel Vadot status = "okay"; 1449*01950c46SEmmanuel Vadot dr_mode = "peripheral"; 1450*01950c46SEmmanuel Vadot }; 1451*01950c46SEmmanuel Vadot 1452*01950c46SEmmanuel Vadot usb-phy@7d000000 { 1453*01950c46SEmmanuel Vadot status = "okay"; 1454*01950c46SEmmanuel Vadot dr_mode = "peripheral"; 1455*01950c46SEmmanuel Vadot nvidia,hssync-start-delay = <0>; 1456*01950c46SEmmanuel Vadot nvidia,xcvr-lsfslew = <2>; 1457*01950c46SEmmanuel Vadot nvidia,xcvr-lsrslew = <2>; 1458*01950c46SEmmanuel Vadot vbus-supply = <&avdd_3v3_periph>; 1459*01950c46SEmmanuel Vadot }; 1460*01950c46SEmmanuel Vadot 1461*01950c46SEmmanuel Vadot /* PMIC has a built-in 32KHz oscillator which is used by PMC */ 1462*01950c46SEmmanuel Vadot clk32k_in: clock-32k { 1463*01950c46SEmmanuel Vadot compatible = "fixed-clock"; 1464*01950c46SEmmanuel Vadot #clock-cells = <0>; 1465*01950c46SEmmanuel Vadot clock-frequency = <32768>; 1466*01950c46SEmmanuel Vadot clock-output-names = "pmic-oscillator"; 1467*01950c46SEmmanuel Vadot }; 1468*01950c46SEmmanuel Vadot 1469*01950c46SEmmanuel Vadot gps_refclk: clock-gps { 1470*01950c46SEmmanuel Vadot compatible = "fixed-clock"; 1471*01950c46SEmmanuel Vadot clock-frequency = <26000000>; 1472*01950c46SEmmanuel Vadot clock-accuracy = <100>; 1473*01950c46SEmmanuel Vadot #clock-cells = <0>; 1474*01950c46SEmmanuel Vadot }; 1475*01950c46SEmmanuel Vadot 1476*01950c46SEmmanuel Vadot gps_osc: clock-gps-osc-gate { 1477*01950c46SEmmanuel Vadot compatible = "gpio-gate-clock"; 1478*01950c46SEmmanuel Vadot enable-gpios = <&gpio TEGRA_GPIO(H, 0) GPIO_ACTIVE_HIGH>; 1479*01950c46SEmmanuel Vadot clocks = <&gps_refclk>; 1480*01950c46SEmmanuel Vadot #clock-cells = <0>; 1481*01950c46SEmmanuel Vadot }; 1482*01950c46SEmmanuel Vadot 1483*01950c46SEmmanuel Vadot cpus { 1484*01950c46SEmmanuel Vadot cpu0: cpu@0 { 1485*01950c46SEmmanuel Vadot cpu-supply = <&vdd_cpu>; 1486*01950c46SEmmanuel Vadot operating-points-v2 = <&cpu0_opp_table>; 1487*01950c46SEmmanuel Vadot #cooling-cells = <2>; 1488*01950c46SEmmanuel Vadot }; 1489*01950c46SEmmanuel Vadot cpu1: cpu@1 { 1490*01950c46SEmmanuel Vadot cpu-supply = <&vdd_cpu>; 1491*01950c46SEmmanuel Vadot operating-points-v2 = <&cpu0_opp_table>; 1492*01950c46SEmmanuel Vadot #cooling-cells = <2>; 1493*01950c46SEmmanuel Vadot }; 1494*01950c46SEmmanuel Vadot cpu2: cpu@2 { 1495*01950c46SEmmanuel Vadot cpu-supply = <&vdd_cpu>; 1496*01950c46SEmmanuel Vadot operating-points-v2 = <&cpu0_opp_table>; 1497*01950c46SEmmanuel Vadot #cooling-cells = <2>; 1498*01950c46SEmmanuel Vadot }; 1499*01950c46SEmmanuel Vadot cpu3: cpu@3 { 1500*01950c46SEmmanuel Vadot cpu-supply = <&vdd_cpu>; 1501*01950c46SEmmanuel Vadot operating-points-v2 = <&cpu0_opp_table>; 1502*01950c46SEmmanuel Vadot #cooling-cells = <2>; 1503*01950c46SEmmanuel Vadot }; 1504*01950c46SEmmanuel Vadot }; 1505*01950c46SEmmanuel Vadot 1506*01950c46SEmmanuel Vadot gpio-keys { 1507*01950c46SEmmanuel Vadot compatible = "gpio-keys"; 1508*01950c46SEmmanuel Vadot 1509*01950c46SEmmanuel Vadot key-power { 1510*01950c46SEmmanuel Vadot label = "Power"; 1511*01950c46SEmmanuel Vadot gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>; 1512*01950c46SEmmanuel Vadot linux,code = <KEY_POWER>; 1513*01950c46SEmmanuel Vadot debounce-interval = <10>; 1514*01950c46SEmmanuel Vadot wakeup-event-action = <EV_ACT_ASSERTED>; 1515*01950c46SEmmanuel Vadot wakeup-source; 1516*01950c46SEmmanuel Vadot }; 1517*01950c46SEmmanuel Vadot 1518*01950c46SEmmanuel Vadot key-volume-down { 1519*01950c46SEmmanuel Vadot label = "Volume Down"; 1520*01950c46SEmmanuel Vadot gpios = <&gpio TEGRA_GPIO(O, 4) GPIO_ACTIVE_LOW>; 1521*01950c46SEmmanuel Vadot linux,code = <KEY_VOLUMEDOWN>; 1522*01950c46SEmmanuel Vadot debounce-interval = <10>; 1523*01950c46SEmmanuel Vadot wakeup-event-action = <EV_ACT_ASSERTED>; 1524*01950c46SEmmanuel Vadot wakeup-source; 1525*01950c46SEmmanuel Vadot }; 1526*01950c46SEmmanuel Vadot }; 1527*01950c46SEmmanuel Vadot 1528*01950c46SEmmanuel Vadot gpio-leds { 1529*01950c46SEmmanuel Vadot compatible = "gpio-leds"; 1530*01950c46SEmmanuel Vadot 1531*01950c46SEmmanuel Vadot led-keypad { 1532*01950c46SEmmanuel Vadot label = "keypad::white"; 1533*01950c46SEmmanuel Vadot gpios = <&gpio TEGRA_GPIO(R, 2) GPIO_ACTIVE_HIGH>; 1534*01950c46SEmmanuel Vadot 1535*01950c46SEmmanuel Vadot color = <LED_COLOR_ID_WHITE>; 1536*01950c46SEmmanuel Vadot function = LED_FUNCTION_KBD_BACKLIGHT; 1537*01950c46SEmmanuel Vadot }; 1538*01950c46SEmmanuel Vadot }; 1539*01950c46SEmmanuel Vadot 1540*01950c46SEmmanuel Vadot opp-table-actmon { 1541*01950c46SEmmanuel Vadot /delete-node/ opp-625000000; 1542*01950c46SEmmanuel Vadot /delete-node/ opp-667000000; 1543*01950c46SEmmanuel Vadot /delete-node/ opp-750000000; 1544*01950c46SEmmanuel Vadot /delete-node/ opp-800000000; 1545*01950c46SEmmanuel Vadot /delete-node/ opp-900000000; 1546*01950c46SEmmanuel Vadot }; 1547*01950c46SEmmanuel Vadot 1548*01950c46SEmmanuel Vadot opp-table-emc { 1549*01950c46SEmmanuel Vadot /delete-node/ opp-625000000-1200; 1550*01950c46SEmmanuel Vadot /delete-node/ opp-625000000-1250; 1551*01950c46SEmmanuel Vadot /delete-node/ opp-667000000-1200; 1552*01950c46SEmmanuel Vadot /delete-node/ opp-750000000-1300; 1553*01950c46SEmmanuel Vadot /delete-node/ opp-800000000-1300; 1554*01950c46SEmmanuel Vadot /delete-node/ opp-900000000-1350; 1555*01950c46SEmmanuel Vadot }; 1556*01950c46SEmmanuel Vadot 1557*01950c46SEmmanuel Vadot brcm_wifi_pwrseq: pwrseq-wifi { 1558*01950c46SEmmanuel Vadot compatible = "mmc-pwrseq-simple"; 1559*01950c46SEmmanuel Vadot 1560*01950c46SEmmanuel Vadot clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>; 1561*01950c46SEmmanuel Vadot clock-names = "ext_clock"; 1562*01950c46SEmmanuel Vadot 1563*01950c46SEmmanuel Vadot reset-gpios = <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_LOW>; 1564*01950c46SEmmanuel Vadot post-power-on-delay-ms = <300>; 1565*01950c46SEmmanuel Vadot power-off-delay-us = <300>; 1566*01950c46SEmmanuel Vadot }; 1567*01950c46SEmmanuel Vadot 1568*01950c46SEmmanuel Vadot vdd_5v0_vbus: regulator-vbus { 1569*01950c46SEmmanuel Vadot compatible = "regulator-fixed"; 1570*01950c46SEmmanuel Vadot regulator-name = "vdd_vbus"; 1571*01950c46SEmmanuel Vadot regulator-min-microvolt = <5000000>; 1572*01950c46SEmmanuel Vadot regulator-max-microvolt = <5000000>; 1573*01950c46SEmmanuel Vadot regulator-always-on; 1574*01950c46SEmmanuel Vadot regulator-boot-on; 1575*01950c46SEmmanuel Vadot }; 1576*01950c46SEmmanuel Vadot 1577*01950c46SEmmanuel Vadot vdd_3v3_vbat: regulator-vbat { 1578*01950c46SEmmanuel Vadot compatible = "regulator-fixed"; 1579*01950c46SEmmanuel Vadot regulator-name = "vdd_vbat"; 1580*01950c46SEmmanuel Vadot regulator-min-microvolt = <3300000>; 1581*01950c46SEmmanuel Vadot regulator-max-microvolt = <3300000>; 1582*01950c46SEmmanuel Vadot regulator-always-on; 1583*01950c46SEmmanuel Vadot regulator-boot-on; 1584*01950c46SEmmanuel Vadot vin-supply = <&vdd_5v0_vbus>; 1585*01950c46SEmmanuel Vadot }; 1586*01950c46SEmmanuel Vadot 1587*01950c46SEmmanuel Vadot vdd_3v0_sen: regulator-sen3v { 1588*01950c46SEmmanuel Vadot compatible = "regulator-fixed"; 1589*01950c46SEmmanuel Vadot regulator-name = "vdd_3v0_sensor"; 1590*01950c46SEmmanuel Vadot regulator-min-microvolt = <3000000>; 1591*01950c46SEmmanuel Vadot regulator-max-microvolt = <3000000>; 1592*01950c46SEmmanuel Vadot regulator-boot-on; 1593*01950c46SEmmanuel Vadot gpio = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_HIGH>; 1594*01950c46SEmmanuel Vadot enable-active-high; 1595*01950c46SEmmanuel Vadot vin-supply = <&vdd_3v3_vbat>; 1596*01950c46SEmmanuel Vadot }; 1597*01950c46SEmmanuel Vadot 1598*01950c46SEmmanuel Vadot vdd_3v0_proxi: regulator-proxi { 1599*01950c46SEmmanuel Vadot compatible = "regulator-fixed"; 1600*01950c46SEmmanuel Vadot regulator-name = "vdd_3v0_proxi"; 1601*01950c46SEmmanuel Vadot regulator-min-microvolt = <3000000>; 1602*01950c46SEmmanuel Vadot regulator-max-microvolt = <3000000>; 1603*01950c46SEmmanuel Vadot regulator-boot-on; 1604*01950c46SEmmanuel Vadot gpio = <&gpio TEGRA_GPIO(X, 1) GPIO_ACTIVE_HIGH>; 1605*01950c46SEmmanuel Vadot enable-active-high; 1606*01950c46SEmmanuel Vadot vin-supply = <&vdd_3v3_vbat>; 1607*01950c46SEmmanuel Vadot }; 1608*01950c46SEmmanuel Vadot 1609*01950c46SEmmanuel Vadot vdd_1v8_sen: regulator-sen1v8 { 1610*01950c46SEmmanuel Vadot compatible = "regulator-fixed"; 1611*01950c46SEmmanuel Vadot regulator-name = "vdd_1v8_sensor"; 1612*01950c46SEmmanuel Vadot regulator-min-microvolt = <1800000>; 1613*01950c46SEmmanuel Vadot regulator-max-microvolt = <1800000>; 1614*01950c46SEmmanuel Vadot regulator-boot-on; 1615*01950c46SEmmanuel Vadot gpio = <&gpio TEGRA_GPIO(D, 2) GPIO_ACTIVE_HIGH>; 1616*01950c46SEmmanuel Vadot enable-active-high; 1617*01950c46SEmmanuel Vadot vin-supply = <&vdd_3v3_vbat>; 1618*01950c46SEmmanuel Vadot }; 1619*01950c46SEmmanuel Vadot 1620*01950c46SEmmanuel Vadot vcc_3v0_lcd: regulator-lcd3v { 1621*01950c46SEmmanuel Vadot compatible = "regulator-fixed"; 1622*01950c46SEmmanuel Vadot regulator-name = "vcc_3v0_lcd"; 1623*01950c46SEmmanuel Vadot regulator-min-microvolt = <3000000>; 1624*01950c46SEmmanuel Vadot regulator-max-microvolt = <3000000>; 1625*01950c46SEmmanuel Vadot regulator-boot-on; 1626*01950c46SEmmanuel Vadot vin-supply = <&vdd_3v3_vbat>; 1627*01950c46SEmmanuel Vadot }; 1628*01950c46SEmmanuel Vadot 1629*01950c46SEmmanuel Vadot iovcc_1v8_lcd: regulator-lcd1v8 { 1630*01950c46SEmmanuel Vadot compatible = "regulator-fixed"; 1631*01950c46SEmmanuel Vadot regulator-name = "iovcc_1v8_lcd"; 1632*01950c46SEmmanuel Vadot regulator-min-microvolt = <1800000>; 1633*01950c46SEmmanuel Vadot regulator-max-microvolt = <1800000>; 1634*01950c46SEmmanuel Vadot regulator-boot-on; 1635*01950c46SEmmanuel Vadot gpio = <&gpio TEGRA_GPIO(Y, 0) GPIO_ACTIVE_HIGH>; 1636*01950c46SEmmanuel Vadot enable-active-high; 1637*01950c46SEmmanuel Vadot vin-supply = <&vdd_3v3_vbat>; 1638*01950c46SEmmanuel Vadot }; 1639*01950c46SEmmanuel Vadot 1640*01950c46SEmmanuel Vadot vio_1v8_mhl: regulator-mhl1v8 { 1641*01950c46SEmmanuel Vadot compatible = "regulator-fixed"; 1642*01950c46SEmmanuel Vadot regulator-name = "vio_1v8_mhl"; 1643*01950c46SEmmanuel Vadot regulator-min-microvolt = <1800000>; 1644*01950c46SEmmanuel Vadot regulator-max-microvolt = <1800000>; 1645*01950c46SEmmanuel Vadot regulator-boot-on; 1646*01950c46SEmmanuel Vadot gpio = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>; 1647*01950c46SEmmanuel Vadot enable-active-high; 1648*01950c46SEmmanuel Vadot vin-supply = <&vdd_3v3_vbat>; 1649*01950c46SEmmanuel Vadot }; 1650*01950c46SEmmanuel Vadot 1651*01950c46SEmmanuel Vadot vdd_3v0_touch: regulator-touchpwr { 1652*01950c46SEmmanuel Vadot compatible = "regulator-fixed"; 1653*01950c46SEmmanuel Vadot regulator-name = "vdd_3v0_touch"; 1654*01950c46SEmmanuel Vadot regulator-min-microvolt = <3000000>; 1655*01950c46SEmmanuel Vadot regulator-max-microvolt = <3000000>; 1656*01950c46SEmmanuel Vadot regulator-boot-on; 1657*01950c46SEmmanuel Vadot gpio = <&gpio TEGRA_GPIO(Q, 1) GPIO_ACTIVE_HIGH>; 1658*01950c46SEmmanuel Vadot enable-active-high; 1659*01950c46SEmmanuel Vadot vin-supply = <&vdd_3v3_vbat>; 1660*01950c46SEmmanuel Vadot }; 1661*01950c46SEmmanuel Vadot 1662*01950c46SEmmanuel Vadot vdd_1v8_touch: regulator-touchvio { 1663*01950c46SEmmanuel Vadot compatible = "regulator-fixed"; 1664*01950c46SEmmanuel Vadot regulator-name = "vdd_1v8_touch"; 1665*01950c46SEmmanuel Vadot regulator-min-microvolt = <1800000>; 1666*01950c46SEmmanuel Vadot regulator-max-microvolt = <1800000>; 1667*01950c46SEmmanuel Vadot regulator-boot-on; 1668*01950c46SEmmanuel Vadot gpio = <&gpio TEGRA_GPIO(X, 4) GPIO_ACTIVE_HIGH>; 1669*01950c46SEmmanuel Vadot enable-active-high; 1670*01950c46SEmmanuel Vadot vin-supply = <&vdd_3v3_vbat>; 1671*01950c46SEmmanuel Vadot }; 1672*01950c46SEmmanuel Vadot 1673*01950c46SEmmanuel Vadot vcc_1v8_gps: regulator-gps { 1674*01950c46SEmmanuel Vadot compatible = "regulator-fixed"; 1675*01950c46SEmmanuel Vadot regulator-name = "vcc_1v8_gps"; 1676*01950c46SEmmanuel Vadot regulator-min-microvolt = <1800000>; 1677*01950c46SEmmanuel Vadot regulator-max-microvolt = <1800000>; 1678*01950c46SEmmanuel Vadot regulator-boot-on; 1679*01950c46SEmmanuel Vadot gpio = <&gpio TEGRA_GPIO(Y, 1) GPIO_ACTIVE_HIGH>; 1680*01950c46SEmmanuel Vadot enable-active-high; 1681*01950c46SEmmanuel Vadot vin-supply = <&vdd_3v3_vbat>; 1682*01950c46SEmmanuel Vadot }; 1683*01950c46SEmmanuel Vadot 1684*01950c46SEmmanuel Vadot vio_1v8_front: regulator-frontvio { 1685*01950c46SEmmanuel Vadot compatible = "regulator-fixed"; 1686*01950c46SEmmanuel Vadot regulator-name = "vt_1v8_cam_vio"; 1687*01950c46SEmmanuel Vadot regulator-min-microvolt = <1800000>; 1688*01950c46SEmmanuel Vadot regulator-max-microvolt = <1800000>; 1689*01950c46SEmmanuel Vadot gpio = <&gpio TEGRA_GPIO(Y, 2) GPIO_ACTIVE_HIGH>; 1690*01950c46SEmmanuel Vadot enable-active-high; 1691*01950c46SEmmanuel Vadot vin-supply = <&vdd_3v3_vbat>; 1692*01950c46SEmmanuel Vadot }; 1693*01950c46SEmmanuel Vadot 1694*01950c46SEmmanuel Vadot sound { 1695*01950c46SEmmanuel Vadot nvidia,audio-routing = 1696*01950c46SEmmanuel Vadot "Headphone Jack", "HPL", 1697*01950c46SEmmanuel Vadot "Headphone Jack", "HPR", 1698*01950c46SEmmanuel Vadot "Int Spk", "SPKL", 1699*01950c46SEmmanuel Vadot "Int Spk", "SPKR", 1700*01950c46SEmmanuel Vadot "Earpiece", "RECL", 1701*01950c46SEmmanuel Vadot "Earpiece", "RECR", 1702*01950c46SEmmanuel Vadot "INA1", "Mic Jack", 1703*01950c46SEmmanuel Vadot "MIC1", "MICBIAS", 1704*01950c46SEmmanuel Vadot "MICBIAS", "Internal Mic 1", 1705*01950c46SEmmanuel Vadot "MIC2", "Internal Mic 2"; 1706*01950c46SEmmanuel Vadot 1707*01950c46SEmmanuel Vadot nvidia,i2s-controller = <&tegra_i2s0>; 1708*01950c46SEmmanuel Vadot nvidia,audio-codec = <&max98089>; 1709*01950c46SEmmanuel Vadot 1710*01950c46SEmmanuel Vadot nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(BB, 6) GPIO_ACTIVE_LOW>; 1711*01950c46SEmmanuel Vadot nvidia,mic-det-gpios = <&gpio TEGRA_GPIO(O, 5) GPIO_ACTIVE_HIGH>; 1712*01950c46SEmmanuel Vadot nvidia,ext-mic-en-gpios = <&gpio TEGRA_GPIO(X, 0) GPIO_ACTIVE_HIGH>; 1713*01950c46SEmmanuel Vadot nvidia,coupled-mic-hp-det; 1714*01950c46SEmmanuel Vadot 1715*01950c46SEmmanuel Vadot clocks = <&tegra_car TEGRA30_CLK_PLL_A>, 1716*01950c46SEmmanuel Vadot <&tegra_car TEGRA30_CLK_PLL_A_OUT0>, 1717*01950c46SEmmanuel Vadot <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; 1718*01950c46SEmmanuel Vadot clock-names = "pll_a", "pll_a_out0", "mclk"; 1719*01950c46SEmmanuel Vadot 1720*01950c46SEmmanuel Vadot assigned-clocks = <&tegra_car TEGRA30_CLK_EXTERN1>, 1721*01950c46SEmmanuel Vadot <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; 1722*01950c46SEmmanuel Vadot 1723*01950c46SEmmanuel Vadot assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_A_OUT0>, 1724*01950c46SEmmanuel Vadot <&tegra_car TEGRA30_CLK_EXTERN1>; 1725*01950c46SEmmanuel Vadot }; 1726*01950c46SEmmanuel Vadot 1727*01950c46SEmmanuel Vadot thermal-zones { 1728*01950c46SEmmanuel Vadot /* 1729*01950c46SEmmanuel Vadot * NCT72 has two sensors: 1730*01950c46SEmmanuel Vadot * 1731*01950c46SEmmanuel Vadot * 0: internal that monitors ambient/skin temperature 1732*01950c46SEmmanuel Vadot * 1: external that is connected to the CPU's diode 1733*01950c46SEmmanuel Vadot * 1734*01950c46SEmmanuel Vadot * Ideally we should use userspace thermal governor, 1735*01950c46SEmmanuel Vadot * but it's a much more complex solution. The "skin" 1736*01950c46SEmmanuel Vadot * zone exists as a simpler solution which prevents 1737*01950c46SEmmanuel Vadot * this device from getting too hot from a user's 1738*01950c46SEmmanuel Vadot * tactile perspective. The CPU zone is intended to 1739*01950c46SEmmanuel Vadot * protect silicon from damage. 1740*01950c46SEmmanuel Vadot */ 1741*01950c46SEmmanuel Vadot 1742*01950c46SEmmanuel Vadot skin-thermal { 1743*01950c46SEmmanuel Vadot polling-delay-passive = <1000>; /* milliseconds */ 1744*01950c46SEmmanuel Vadot polling-delay = <5000>; /* milliseconds */ 1745*01950c46SEmmanuel Vadot 1746*01950c46SEmmanuel Vadot thermal-sensors = <&nct72 0>; 1747*01950c46SEmmanuel Vadot 1748*01950c46SEmmanuel Vadot trips { 1749*01950c46SEmmanuel Vadot trip0: skin-alert { 1750*01950c46SEmmanuel Vadot /* throttle at 50C until temperature drops to 49.8C */ 1751*01950c46SEmmanuel Vadot temperature = <50000>; 1752*01950c46SEmmanuel Vadot hysteresis = <200>; 1753*01950c46SEmmanuel Vadot type = "passive"; 1754*01950c46SEmmanuel Vadot }; 1755*01950c46SEmmanuel Vadot 1756*01950c46SEmmanuel Vadot trip1: skin-crit { 1757*01950c46SEmmanuel Vadot /* shut down at 60C */ 1758*01950c46SEmmanuel Vadot temperature = <60000>; 1759*01950c46SEmmanuel Vadot hysteresis = <2000>; 1760*01950c46SEmmanuel Vadot type = "critical"; 1761*01950c46SEmmanuel Vadot }; 1762*01950c46SEmmanuel Vadot }; 1763*01950c46SEmmanuel Vadot 1764*01950c46SEmmanuel Vadot cooling-maps { 1765*01950c46SEmmanuel Vadot map0 { 1766*01950c46SEmmanuel Vadot trip = <&trip0>; 1767*01950c46SEmmanuel Vadot cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1768*01950c46SEmmanuel Vadot <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1769*01950c46SEmmanuel Vadot <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1770*01950c46SEmmanuel Vadot <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1771*01950c46SEmmanuel Vadot <&actmon THERMAL_NO_LIMIT 1772*01950c46SEmmanuel Vadot THERMAL_NO_LIMIT>; 1773*01950c46SEmmanuel Vadot }; 1774*01950c46SEmmanuel Vadot }; 1775*01950c46SEmmanuel Vadot }; 1776*01950c46SEmmanuel Vadot 1777*01950c46SEmmanuel Vadot cpu-thermal { 1778*01950c46SEmmanuel Vadot polling-delay-passive = <1000>; /* milliseconds */ 1779*01950c46SEmmanuel Vadot polling-delay = <5000>; /* milliseconds */ 1780*01950c46SEmmanuel Vadot 1781*01950c46SEmmanuel Vadot thermal-sensors = <&nct72 1>; 1782*01950c46SEmmanuel Vadot 1783*01950c46SEmmanuel Vadot trips { 1784*01950c46SEmmanuel Vadot trip2: cpu-alert { 1785*01950c46SEmmanuel Vadot /* throttle at 75C until temperature drops to 74.8C */ 1786*01950c46SEmmanuel Vadot temperature = <75000>; 1787*01950c46SEmmanuel Vadot hysteresis = <200>; 1788*01950c46SEmmanuel Vadot type = "passive"; 1789*01950c46SEmmanuel Vadot }; 1790*01950c46SEmmanuel Vadot 1791*01950c46SEmmanuel Vadot trip3: cpu-crit { 1792*01950c46SEmmanuel Vadot /* shut down at 90C */ 1793*01950c46SEmmanuel Vadot temperature = <90000>; 1794*01950c46SEmmanuel Vadot hysteresis = <2000>; 1795*01950c46SEmmanuel Vadot type = "critical"; 1796*01950c46SEmmanuel Vadot }; 1797*01950c46SEmmanuel Vadot }; 1798*01950c46SEmmanuel Vadot 1799*01950c46SEmmanuel Vadot cooling-maps { 1800*01950c46SEmmanuel Vadot map1 { 1801*01950c46SEmmanuel Vadot trip = <&trip2>; 1802*01950c46SEmmanuel Vadot cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1803*01950c46SEmmanuel Vadot <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1804*01950c46SEmmanuel Vadot <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1805*01950c46SEmmanuel Vadot <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1806*01950c46SEmmanuel Vadot <&actmon THERMAL_NO_LIMIT 1807*01950c46SEmmanuel Vadot THERMAL_NO_LIMIT>; 1808*01950c46SEmmanuel Vadot }; 1809*01950c46SEmmanuel Vadot }; 1810*01950c46SEmmanuel Vadot }; 1811*01950c46SEmmanuel Vadot }; 1812*01950c46SEmmanuel Vadot}; 1813