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/linux/arch/arm64/boot/dts/hisilicon/
H A Dhi6220-coresight.dtsi3 * dtsi file for Hisilicon Hi6220 coresight
14 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
39 compatible = "arm,coresight-tmc", "arm,primecell";
64 compatible = "arm,coresight-static-replicator";
100 compatible = "arm,coresight-tmc", "arm,primecell";
116 compatible = "arm,coresight-tpiu", "arm,primecell";
132 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
217 compatible = "arm,coresight-etm4x", "arm,primecell";
236 compatible = "arm,coresight-etm4x", "arm,primecell";
255 compatible = "arm,coresight-etm4x", "arm,primecell";
[all …]
H A Dhi3660-coresight.dtsi4 * dtsi for Hisilicon Hi3660 Coresight
15 compatible = "arm,coresight-etm4x", "arm,primecell";
20 arm,coresight-loses-context-with-cpu;
33 compatible = "arm,coresight-etm4x", "arm,primecell";
38 arm,coresight-loses-context-with-cpu;
51 compatible = "arm,coresight-etm4x", "arm,primecell";
56 arm,coresight-loses-context-with-cpu;
69 compatible = "arm,coresight-etm4x", "arm,primecell";
74 arm,coresight-loses-context-with-cpu;
87 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
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/linux/Documentation/trace/coresight/
H A Dcoresight-perf.rst4 CoreSight - Perf
10 Perf is able to locally access CoreSight trace data and store it to the
18 a perf.data trace file. That file would have AUX sections if CoreSight
28 . ... CoreSight ETM Trace data: size 73168 bytes
40 If you see these above, then your system is tracing CoreSight data
43 To compile perf with CoreSight support in the tools/perf directory do::
45 make CORESIGHT=1
53 For complete information on building perf with CoreSight support and
59 Kernel CoreSight Support
62 You will also want CoreSight support enabled in your kernel config.
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H A Dcoresight-tpda.rst22 Root: ``/sys/bus/coresight/devices/tpda<N>``
27 The tpdm and tpda nodes should be observed at the coresight path
28 "/sys/bus/coresight/devices".
30 /sys/bus/coresight/devices # ls -l | grep tpd
35 Enable coresight sink first. The port of tpda which is connected to
38 echo 1 > /sys/bus/coresight/devices/tmc_etf0/enable_sink
39 echo 1 > /sys/bus/coresight/devices/tpdm0/enable_source
40 echo 1 > /sys/bus/coresight/devices/tpdm0/integration_test
41 echo 2 > /sys/bus/coresight/devices/tpdm0/integration_test
43 The test data will be collected in the coresight sink which is enabled.
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H A Dcoresight-dummy.rst4 Coresight Dummy Trace Module
13 The Coresight dummy trace module is for the specific devices that kernel don't
14 have permission to access or configure, e.g., CoreSight TPDMs on Qualcomm
16 Coresight devices. The module may also be used to define components that may
18 It provides Coresight API for operations on dummy devices, such as enabling and
19 disabling them. It also provides the Coresight dummy sink/source paths for
26 are available at ``/sys/bus/coresight/devices``.
30 $ ls -l /sys/bus/coresight/devices | grep dummy
H A Dcoresight-trbe.rst15 gets plugged in as a coresight sink device because the corresponding trace
18 The TRBE is not compliant to CoreSight architecture specifications, but is
19 driven via the CoreSight driver framework to support the ETE (which is
20 CoreSight compliant) integration.
25 The TRBE devices appear on the existing coresight bus alongside the other
26 coresight devices::
28 >$ ls /sys/bus/coresight/devices
33 >$ ls /sys/bus/coresight/devices/trbe0/
H A Dpanic.rst2 Using Coresight for Kernel panic and Watchdog reset
7 This documentation is about using Linux coresight trace support to
10 Coresight trace during Kernel panic
12 From the coresight driver point of view, addressing the kernel panic
17 relevant coresight nodes.
19 b. Support for stopping coresight blocks at the time of panic
28 Coresight TMC device nodes, that would give the base address and size of trace
43 Disabling coresight blocks at the time of panic
46 kernel panic, it would be desirable to stop the coresight blocks at the
57 Coresight metadata involves all additional data that are required for a
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H A Dcoresight-cpu-debug.rst2 Coresight CPU Debug Module
11 Coresight CPU debug module is defined in ARMv8-a architecture reference manual
107 power down in the way that the CoreSight / Debug designers anticipated.
120 See Documentation/devicetree/bindings/arm/arm,coresight-cpu-debug.yaml for
184 coresight-cpu-debug 850000.debug: CPU[0]:
185 coresight-cpu-debug 850000.debug: EDPRSR: 00000001 (Power:On DLK:Unlock)
186 coresight-cpu-debug 850000.debug: EDPCSR: handle_IPI+0x174/0x1d8
187 coresight-cpu-debug 850000.debug: EDCIDSR: 00000000
188 …coresight-cpu-debug 850000.debug: EDVIDSR: 90000000 (State:Non-secure Mode:EL1/0 Width:64bits VMI…
189 coresight-cpu-debug 852000.debug: CPU[1]:
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H A Dcoresight-ect.rst4 CoreSight Embedded Cross Trigger (CTI & CTM).
13 The CoreSight Cross Trigger Interface (CTI) is a hardware device that takes
41 CoreSight devices on the trace data path. When these devices are enabled the
50 The hardware trigger signals can also be connected to non-CoreSight devices
62 The CTI devices appear on the existing CoreSight bus alongside the other
63 CoreSight devices::
65 >$ ls /sys/bus/coresight/devices
71 can be associated with other CoreSight devices, or other system hardware
74 >$ ls /sys/bus/coresight/devices/etm0/cti_cpu0
91 * ``mgmt``: the standard CoreSight management registers.
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H A Dcoresight-config.rst4 CoreSight System Configuration Manager
13 The CoreSight System Configuration manager is an API that allows the
14 programming of the CoreSight system with pre-defined configurations that
17 Many CoreSight components can be programmed in complex ways - especially ETMs.
18 In addition, components can interact across the CoreSight system, often via
26 This section introduces the basic concepts of a CoreSight system configuration.
32 A feature is a named set of programming for a CoreSight device. The programming
38 CoreSight device is registered with the configuration manager.
66 Users can update parameter values using the configfs API for the CoreSight
113 associated feature 'strobing' that works on ETMv4 CoreSight Devices.
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H A Dultrasoc-smb.rst14 memory. The device acts as a coresight sink device and the
20 The SMB devices appear on the existing coresight bus alongside other
23 $# ls /sys/bus/coresight/devices/
28 $# ls /sys/bus/coresight/devices/ultra_smb0
30 $# ls /sys/bus/coresight/devices/ultra_smb0/mgmt
64 /* Use CoreSight Graph ACPI bindings to describe connections topology */
/linux/drivers/perf/arm_cspmu/
H A DKconfig6 tristate "ARM Coresight Architecture PMU"
10 based on ARM CoreSight PMU architecture. Note that this PMU
11 architecture does not have relationship with the ARM CoreSight
15 tristate "NVIDIA Coresight Architecture PMU"
19 (PMU) devices based on ARM CoreSight PMU architecture.
22 tristate "Ampere Coresight Architecture PMU"
26 (PMU) devices based on ARM CoreSight PMU architecture.
/linux/Documentation/devicetree/bindings/arm/
H A Darm,coresight-stm.yaml4 $id: http://devicetree.org/schemas/arm/arm,coresight-stm.yaml#
7 title: Arm CoreSight System Trace MacroCell
16 CoreSight components are compliant with the ARM CoreSight architecture
23 The STM is a trace source that is integrated into a CoreSight system, designed
33 const: arm,coresight-stm
43 - const: arm,coresight-stm
73 description: Output connection to the CoreSight Trace bus.
89 compatible = "arm,coresight-stm", "arm,primecell";
H A Darm,coresight-catu.yaml4 $id: http://devicetree.org/schemas/arm/arm,coresight-catu.yaml#
7 title: Arm Coresight Address Translation Unit (CATU)
16 CoreSight components are compliant with the ARM CoreSight architecture
23 The CoreSight Address Translation Unit (CATU) translates addresses between an
34 const: arm,coresight-catu
44 - const: arm,coresight-catu
73 description: AXI Slave connected to another Coresight component
89 compatible = "arm,coresight-catu", "arm,primecell";
H A Darm,coresight-cpu-debug.yaml4 $id: http://devicetree.org/schemas/arm/arm,coresight-cpu-debug.yaml#
7 title: CoreSight CPU Debug Component
16 CoreSight CPU debug component are compliant with the ARMv8 architecture
19 external debug, and it can be accessed from mmio region from Coresight and
29 const: arm,coresight-cpu-debug
39 - const: arm,coresight-cpu-debug
75 compatible = "arm,coresight-cpu-debug", "arm,primecell";
/linux/arch/arm/boot/dts/hisilicon/
H A Dhip04.dtsi272 compatible = "arm,coresight-etb10", "arm,primecell";
287 compatible = "arm,coresight-etb10", "arm,primecell";
302 compatible = "arm,coresight-etb10", "arm,primecell";
317 compatible = "arm,coresight-etb10", "arm,primecell";
332 compatible = "arm,coresight-tpiu", "arm,primecell";
350 compatible = "arm,coresight-static-replicator";
385 compatible = "arm,coresight-static-replicator";
420 compatible = "arm,coresight-static-replicator";
454 compatible = "arm,coresight-static-replicator";
485 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
[all …]
/linux/arch/arm64/boot/dts/arm/
H A Djuno-base.dtsi116 * Juno TRMs specify the size for these coresight components as 64K.
121 compatible = "arm,coresight-tmc", "arm,primecell";
145 compatible = "arm,coresight-tpiu", "arm,primecell";
162 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
198 compatible = "arm,coresight-tmc", "arm,primecell";
216 compatible = "arm,coresight-stm", "arm,primecell";
233 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
268 compatible = "arm,coresight-cpu-debug", "arm,primecell";
277 compatible = "arm,coresight-etm4x", "arm,primecell";
293 compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
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/linux/drivers/hwtracing/coresight/
H A Dcoresight-syscfg.h3 * Coresight system configuration driver.
10 #include <linux/coresight.h>
13 #include "coresight-config.h"
29 * Contains lists of the loaded configurations and features, plus a list of CoreSight devices
32 * Need a device to 'own' some coresight system wide sysfs entries in
36 * @csdev_desc_list: List of coresight devices registered with the configuration manager.
42 * @sysfs_active_config:Active config hash used if CoreSight controlled from sysfs.
43 * @sysfs_active_preset:Active preset index used if CoreSight controlled from sysfs.
63 * List entry for Coresight devices that are registered as supporting complex
H A Dcoresight-config.h10 #include <linux/coresight.h>
13 /* CoreSight Configuration Management - component and system wide configuration */
40 * See PMU_FORMAT_ATTR(preset, "config:0-3") in coresight-etm-perf.c
186 * Feature instance loaded into a CoreSight device.
197 * @csdev: parent CoreSight device instance.
217 * Configuration instance when loaded into a CoreSight device.
223 * @csdev: parent coresight device for this configuration instance.
225 * @node: list entry within the coresight device
240 * Coresight device operations.
242 * Registered coresight devices provide these operations to manage feature
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H A Dcoresight-priv.h12 #include <linux/coresight.h>
19 * Coresight management registers (0xf00-0xfcc)
35 * Coresight device CLAIM protocol.
177 * Macros and inline functions to handle CoreSight UCI data and driver
181 /* coresight AMBA ID, no UCI, no driver data: id table entry */
188 /* coresight AMBA ID, UCI with driver data only: id table entry. */
199 /* coresight AMBA ID, full UCI structure: id table entry. */
210 * as a match value for blanket matching all devices in the given CoreSight
216 * Match all PIDs in a given CoreSight device type and architecture, defined
/linux/Documentation/ABI/testing/
H A Dsysfs-bus-coresight-devices-ultra_smb1 What: /sys/bus/coresight/devices/ultra_smb<N>/enable_sink
8 What: /sys/bus/coresight/devices/ultra_smb<N>/mgmt/buf_size
14 What: /sys/bus/coresight/devices/ultra_smb<N>/mgmt/buf_status
21 What: /sys/bus/coresight/devices/ultra_smb<N>/mgmt/read_pos
27 What: /sys/bus/coresight/devices/ultra_smb<N>/mgmt/write_pos
/linux/arch/arm64/boot/dts/sprd/
H A Dsc9860.dtsi302 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
337 compatible = "arm,coresight-tmc", "arm,primecell";
352 compatible = "arm,coresight-stm", "arm,primecell";
369 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
417 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
465 compatible = "arm,coresight-tmc", "arm,primecell";
490 compatible = "arm,coresight-tmc", "arm,primecell";
515 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
552 compatible = "arm,coresight-etm4x", "arm,primecell";
569 compatible = "arm,coresight-etm4x", "arm,primecell";
[all …]
H A Dsc9836.dtsi48 compatible = "arm,coresight-tmc", "arm,primecell";
62 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
118 compatible = "arm,coresight-etm4x", "arm,primecell";
134 compatible = "arm,coresight-etm4x", "arm,primecell";
150 compatible = "arm,coresight-etm4x", "arm,primecell";
166 compatible = "arm,coresight-etm4x", "arm,primecell";
182 compatible = "arm,coresight-stm", "arm,primecell";
/linux/tools/perf/tests/shell/
H A Dtest_arm_coresight.sh2 # Check Arm CoreSight trace data recording and synthesized samples (exclusive)
4 # Uses the 'perf record' to record trace data with Arm CoreSight sinks;
6 # are generated by CoreSight with 'perf script' and 'perf report'
130 arm_cs_report "CoreSight path testing (CPU$2 -> $device_name)" $err
162 arm_cs_report "CoreSight system wide testing" $err
186 arm_cs_report "CoreSight snapshot testing" $err
198 arm_cs_report "CoreSight basic testing with '$*'" $err
/linux/tools/perf/Documentation/
H A Darm-coresight.txt1 Arm CoreSight Support
4 For full documentation, see Documentation/trace/coresight/coresight-perf.rst

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