Home
last modified time | relevance | path

Searched +full:controller +full:- +full:number (Results 1 – 25 of 1069) sorted by relevance

12345678910>>...43

/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dvia,vt8500-intc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/via,vt8500-intc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: VIA and WonderMedia SoCs Interrupt Controller
10 This is the interrupt controller used in single-core ARM SoCs made by
16 - Alexey Charkov <alchark@gmail.com>
19 - $ref: /schemas/interrupt-controller.yaml#
23 const: via,vt8500-intc
30 - description:
[all …]
H A Dcdns,xtensa-pic.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
5 ---
6 $id: http://devicetree.org/schemas/interrupt-controller/cdns,xtensa-pic.yaml#
7 $schema: http://devicetree.org/meta-schemas/core.yaml#
12 - Max Filippov <jcmvbkbc@gmail.com>
15 Xtensa Interrupt Distributor and Programmable Interrupt Controller (MX) and
16 Xtensa built-in Programmable Interrupt Controller (PIC)
21 - cdns,xtensa-mx
22 - cdns,xtensa-pic
24 '#interrupt-cells':
[all …]
H A Dsamsung,exynos4210-combiner.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/samsung,exynos4210-combiner.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung Exynos SoC Interrupt Combiner Controller
10 - Krzysztof Kozlowski <krzk@kernel.org>
13 Samsung's Exynos4 architecture includes a interrupt combiner controller which
16 a parent interrupt controller, such as GIC in case of Exynos4210.
18 The interrupt combiner controller consists of multiple combiners. Up to eight
21 usually connected to a parent interrupt controller.
[all …]
H A Deconet,en751221-intc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/econet,en751221-intc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: EcoNet EN751221 Interrupt Controller
10 - Caleb James DeLisle <cjd@cjdns.fr>
13 The EcoNet EN751221 Interrupt Controller is a simple interrupt controller
15 be routed to either VPE but not both, so to support per-CPU interrupts, a
16 secondary IRQ number is allocated to control masking/unmasking on VPE#1. For
22 - $ref: /schemas/interrupt-controller.yaml#
[all …]
H A Dimg,pdc-intc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/img,pdc-intc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ImgTec Powerdown Controller (PDC) Interrupt Controller
10 - James Hogan <jhogan@kernel.org>
13 ImgTec Powerdown Controller (PDC) Interrupt Controller has a number of input
19 const: img,pdc-intc
24 interrupt-controller: true
26 '#interrupt-cells':
[all …]
H A Darm,nvic.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/arm,nvic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARM Nested Vector Interrupt Controller (NVIC)
10 - Rob Herring <robh@kernel.org>
13 The NVIC provides an interrupt controller that is tightly coupled to Cortex-M
15 number of interrupts and priority bits per interrupt.
20 - arm,armv7m-nvic # deprecated
21 - arm,v6m-nvic
[all …]
/linux/Documentation/core-api/irq/
H A Dirq-domain.rst2 The irq_domain Interrupt Number Mapping Library
5 The current design of the Linux kernel uses a single large number
6 space where each separate IRQ source is assigned a unique number.
7 This is simple when there is only one interrupt controller. But in
9 that each one gets assigned non-overlapping allocations of Linux
12 The number of interrupt controllers registered as unique irqchips
19 hardware IRQ line into the root interrupt controller (i.e. the
21 this number is just a number and the number loose all kind of
24 For this reason, we need a mechanism to separate controller-local
29 the controller-local IRQ (hwirq) number into the Linux IRQ number
[all …]
/linux/Documentation/devicetree/bindings/pinctrl/
H A Dmicrochip,sparx5-sgpio.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/microchip,sparx5-sgpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Microsemi/Microchip Serial GPIO controller
10 - Lars Povlsen <lars.povlsen@microchip.com>
13 By using a serial interface, the SIO controller significantly extend
14 the number of available GPIOs with a minimum number of additional
17 controller.
21 pattern: "^gpio@[0-9a-f]+$"
[all …]
H A Dpinctrl-st.txt1 *ST pin controller.
3 Each multi-function pin is controlled, driven and routed through the
5 and multiple alternate functions(ALT1 - ALTx) that directly connect
14 GPIO bank can have one of the two possible types of interrupt-wirings.
17 reduces number of overall interrupts numbers required. All these banks belong to
20 | |----> [gpio-bank (n) ]
21 | |----> [gpio-bank (n + 1)]
22 [irqN]-- | irq-mux |----> [gpio-bank (n + 2)]
23 | |----> [gpio-bank (... )]
24 |_________|----> [gpio-bank (n + 7)]
[all …]
H A Dactions,s700-pinctrl.txt1 Actions Semi S700 Pin Controller
3 This binding describes the pin controller found in the S700 SoC.
7 - compatible: Should be "actions,s700-pinctrl"
8 - reg: Should contain the register base address and size of
9 the pin controller.
10 - clocks: phandle of the clock feeding the pin controller
11 - gpio-controller: Marks the device node as a GPIO controller.
12 - gpio-ranges: Specifies the mapping between gpio controller and
13 pin-controller pins.
14 - #gpio-cells: Should be two. The first cell is the gpio pin number
[all …]
/linux/Documentation/devicetree/bindings/gpio/
H A Dnvidia,tegra186-gpio.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/nvidia,tegra186-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra GPIO Controller (Tegra186 and later)
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
14 Tegra186 contains two GPIO controllers; a main controller and an "AON"
15 controller. This binding document applies to both controllers. The register
20 The Tegra186 GPIO controller allows software to set the IO direction of,
[all …]
H A Dgpio.txt5 -----------------
7 GPIO properties should be named "[<name>-]gpios", with <name> being the purpose
8 of this GPIO for the device. While a non-existent <name> is considered valid
10 for new bindings. Also, GPIO properties named "[<name>-]gpio" are valid and old
24 and bit-banged data signals:
27 gpio-controller;
28 #gpio-cells = <2>;
32 data-gpios = <&gpio1 12 0>,
42 The exact meaning of each specifier cell is controller specific, and must be
44 recommended to use the two-cell approach.
[all …]
/linux/drivers/pinctrl/samsung/
H A Dpinctrl-samsung.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * pin-controller/pin-mux/pin-config/gpio-driver for Samsung's SoC's.
25 * enum pincfg_type - possible pin configuration types supported.
46 * packed together into a 16-bits. The upper 8-bits represent the configuration
47 * type and the lower 8-bits hold the value of the configuration type.
70 * enum pud_index - Possible index values to access the pud_val array.
84 * enum eint_type - possible external interrupt types.
90 * Samsung GPIO controller groups all the available pins into banks. The pins
104 /* maximum length of a pin in pin descriptor (example: "gpa0-0") */
135 * struct samsung_pin_bank_data: represent a controller pin-bank (init data).
[all …]
H A Dpinctrl-exynos-arm.c1 // SPDX-License-Identifier: GPL-2.0+
20 #include <linux/soc/samsung/exynos-regs-pmu.h>
22 #include "pinctrl-samsung.h"
23 #include "pinctrl-exynos.h"
35 /* Retention control for S5PV210 are located at the end of clock controller */
49 unsigned int *pud_val = drvdata->pud_val; in s5pv210_pud_value_init()
58 void __iomem *clk_base = (void __iomem *)drvdata->retention_ctrl->priv; in s5pv210_retention_disable()
75 ctrl = devm_kzalloc(drvdata->dev, sizeof(*ctrl), GFP_KERNEL); in s5pv210_retention_init()
77 return ERR_PTR(-ENOMEM); in s5pv210_retention_init()
79 np = of_find_compatible_node(NULL, NULL, "samsung,s5pv210-clock"); in s5pv210_retention_init()
[all …]
H A Dpinctrl-exynos-arm64.c1 // SPDX-License-Identifier: GPL-2.0+
17 #include <linux/soc/samsung/exynos-regs-pmu.h>
19 #include "pinctrl-samsung.h"
20 #include "pinctrl-exynos.h"
53 * Bank type for non-alive type. Bit fields:
71 * Bank type for non-alive type. Bit fields:
82 /* pin banks of exynos2200 pin-controller - ALIVE */
94 /* pin banks of exynos2200 pin-controller - CMGP */
121 /* pin banks of exynos2200 pin-controller - HSI1 */
126 /* pin banks of exynos2200 pin-controller - UFS */
[all …]
/linux/Documentation/nvme/
H A Dnvme-pci-endpoint-target.rst1 .. SPDX-License-Identifier: GPL-2.0
9 The NVMe PCI endpoint function target driver implements an NVMe PCIe controller
10 using an NVMe fabrics target controller configured with the PCI transport type.
16 controller over a PCIe link, thus implementing an NVMe PCIe device similar to a
17 regular M.2 SSD. The target controller is created in the same manner as when
18 using NVMe over fabrics: the controller represents the interface to an NVMe
22 existing physical NVMe device or an NVMe fabrics host controller (e.g. a NVMe
23 TCP host controller).
56 Controller Capabilities
57 -----------------------
[all …]
/linux/tools/perf/pmu-events/arch/x86/snowridgex/
H A Duncore-memory.json3 "BriefDescription": "read requests to memory controller. Derived from unc_m_cas_count.rd",
8 …"PublicDescription": "Counts the total number of DRAM Read CAS commands, w/ and w/o auto-pre, issu…
14 "BriefDescription": "write requests to memory controller. Derived from unc_m_cas_count.wr",
19 …"PublicDescription": "Counts the total number of DRAM Write CAS commands issued, w/ and w/o auto-p…
30 …number of DRAM Activate commands sent on this channel. Activate commands are issued to open up a …
41 …number of DRAM Activate commands sent on this channel. Activate commands are issued to open up a …
51 "PublicDescription": "Counts the total number of DRAM CAS commands issued on this channel.",
61 …"PublicDescription": "Counts the total number of DRAM Read CAS commands, w/ and w/o auto-pre, issu…
66 "BriefDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM RD_CAS commands w/auto-pre",
72 …_CAS Commands. : DRAM RD_CAS commands w/auto-pre : DRAM RD_CAS and WR_CAS Commands : Counts the to…
[all …]
/linux/Documentation/devicetree/bindings/pci/
H A Dralink,rt3883-pci.txt1 * Mediatek/Ralink RT3883 PCI controller
7 - compatible: must be "ralink,rt3883-pci"
9 - reg: specifies the physical base address of the controller and
12 - #address-cells: specifies the number of cells needed to encode an
15 - #size-cells: specifies the number of cells used to represent the size
18 - ranges: specifies the translation between child address space and parent
23 - status: indicates the operational status of the device.
28 The main node must have two child nodes which describes the built-in
29 interrupt controller and the PCI host bridge.
31 a) Interrupt controller:
[all …]
/linux/Documentation/devicetree/bindings/powerpc/fsl/
H A Dmpic.txt2 Freescale MPIC Interrupt Controller Node
6 The Freescale MPIC interrupt controller is found on all PowerQUICC
14 - compatible
22 - reg
24 Value type: <prop-encoded-array>
29 - interrupt-controller
33 controller
35 - #interrupt-cells
39 specifiers do not contain the interrupt-type or type-specific
42 - #address-cells
[all …]
/linux/Documentation/devicetree/bindings/firmware/
H A Dcznic,turris-omnia-mcu.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/firmware/cznic,turris-omnia-mcu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marek Behún <kabel@kernel.org>
13 The MCU on Turris Omnia acts as a system controller providing additional
18 const: cznic,turris-omnia-mcu
27 interrupt-controller: true
29 '#interrupt-cells':
32 The first cell specifies the interrupt number (0 to 63), the second cell
[all …]
/linux/Documentation/devicetree/bindings/i2c/
H A Di2c-pxa-pci-ce4100.txt2 ----------
4 CE4100 has one PCI device which is described as the I2C-Controller. This
5 PCI device has three PCI-bars, each bar contains a complete I2C
6 controller. So we have a total of three independent I2C-Controllers
8 The driver is probed via the PCI-ID and is gathering the information of
10 Grant Likely recommended to use the ranges property to map the PCI-Bar
11 number to its physical address and to use this to find the child nodes
12 of the specific I2C controller. This were his exact words:
22 non-zero if you had 2 or more devices mapped off
30 ------------------------------------------------
[all …]
/linux/drivers/usb/usbip/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
17 be called usbip-core.
25 This enables the USB/IP virtual host controller driver,
29 module will be called vhci-hcd.
32 int "Number of ports per USB/IP virtual host controller"
37 To increase number of ports available for USB/IP virtual
38 host controller driver, this defines number of ports per
39 USB/IP virtual host controller.
42 int "Number of USB/IP virtual host controllers"
47 To increase number of ports available for USB/IP virtual
[all …]
/linux/include/linux/pinctrl/
H A Dpinctrl.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2011 ST-Ericsson SA
6 * Written on behalf of Linaro for ST-Ericsson
30 * struct pingroup - provides information on pingroup
33 * @npins: number of pins in the pingroup
50 * struct pinctrl_pin_desc - boards/machines provide information on their
52 * @number: unique pin number from the global pin number space
54 * @drv_data: driver-defined per-pin data. pinctrl core does not touch this
57 unsigned int number; member
63 #define PINCTRL_PIN(a, b) { .number = a, .name = b }
[all …]
/linux/tools/perf/pmu-events/arch/x86/jaketown/
H A Duncore-cache.json15 …ed in Counter 0. The filtering available is found in the control register - threshold, invert an…
31 …number of times the LLC was accessed - this includes code, data, prefetches and hints coming from …
41 …number of times the LLC was accessed - this includes code, data, prefetches and hints coming from …
51 …number of times the LLC was accessed - this includes code, data, prefetches and hints coming from …
61 …number of times the LLC was accessed - this includes code, data, prefetches and hints coming from …
71 …"PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filt…
81 …"PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filt…
91 …"PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filt…
101 …"PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filt…
111 …"PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filt…
[all …]
/linux/Documentation/devicetree/bindings/mfd/
H A Dtps65912.txt4 - compatible : Should be "ti,tps65912".
5 - reg : Slave address or chip select number (I2C / SPI).
6 - interrupts : The interrupt line the device is connected to.
7 - interrupt-controller : Marks the device node as an interrupt controller.
8 - #interrupt-cells : The number of cells to describe an IRQ, should be 2.
9 The first cell is the IRQ number.
11 masks from ../interrupt-controller/interrupts.txt.
12 - gpio-controller : Marks the device node as a GPIO Controller.
13 - #gpio-cells : Should be two. The first cell is the pin number and
16 - regulators: : List of child nodes that specify the regulator
[all …]

12345678910>>...43