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/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dvia,vt8500-intc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/via,vt8500-intc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: VIA and WonderMedia SoCs Interrupt Controller
10 This is the interrupt controller used in single-core ARM SoCs made by
16 - Alexey Charkov <alchark@gmail.com>
19 - $ref: /schemas/interrupt-controller.yaml#
23 const: via,vt8500-intc
30 - description:
[all …]
H A Dcdns,xtensa-pic.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
5 ---
6 $id: http://devicetree.org/schemas/interrupt-controller/cdns,xtensa-pic.yaml#
7 $schema: http://devicetree.org/meta-schemas/core.yaml#
12 - Max Filippov <jcmvbkbc@gmail.com>
15 Xtensa Interrupt Distributor and Programmable Interrupt Controller (MX) and
16 Xtensa built-in Programmable Interrupt Controller (PIC)
21 - cdns,xtensa-mx
22 - cdns,xtensa-pic
24 '#interrupt-cells':
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H A Dsamsung,exynos4210-combiner.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/samsung,exynos4210-combiner.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung Exynos SoC Interrupt Combiner Controller
10 - Krzysztof Kozlowski <krzk@kernel.org>
13 Samsung's Exynos4 architecture includes a interrupt combiner controller which
16 a parent interrupt controller, such as GIC in case of Exynos4210.
18 The interrupt combiner controller consists of multiple combiners. Up to eight
21 usually connected to a parent interrupt controller.
[all …]
H A Dimg,pdc-intc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/img,pdc-intc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ImgTec Powerdown Controller (PDC) Interrupt Controller
10 - James Hogan <jhogan@kernel.org>
13 ImgTec Powerdown Controller (PDC) Interrupt Controller has a number of input
19 const: img,pdc-intc
24 interrupt-controller: true
26 '#interrupt-cells':
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H A Darm,nvic.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/arm,nvic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARM Nested Vector Interrupt Controller (NVIC)
10 - Rob Herring <robh@kernel.org>
13 The NVIC provides an interrupt controller that is tightly coupled to Cortex-M
15 number of interrupts and priority bits per interrupt.
20 - arm,armv7m-nvic # deprecated
21 - arm,v6m-nvic
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H A Dti,cp-intc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/ti,cp-intc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: TI Common Platform Interrupt Controller
10 - Bartosz Golaszewski <brgl@bgdev.pl>
13 Common Platform Interrupt Controller (cp_intc) is used on OMAP-L1x SoCs and
14 can support several configurable number of interrupts.
18 const: ti,cp-intc
23 interrupt-controller: true
[all …]
/linux/Documentation/nvme/
H A Dnvme-pci-endpoint-target.rst1 .. SPDX-License-Identifier: GPL-2.0
9 The NVMe PCI endpoint function target driver implements an NVMe PCIe controller
10 using an NVMe fabrics target controller configured with the PCI transport type.
16 controller over a PCIe link, thus implementing an NVMe PCIe device similar to a
17 regular M.2 SSD. The target controller is created in the same manner as when
18 using NVMe over fabrics: the controller represents the interface to an NVMe
22 existing physical NVMe device or an NVMe fabrics host controller (e.g. a NVMe
23 TCP host controller).
56 Controller Capabilities
57 -----------------------
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/linux/tools/perf/pmu-events/arch/x86/snowridgex/
H A Duncore-memory.json3 "BriefDescription": "read requests to memory controller. Derived from unc_m_cas_count.rd",
8 …"PublicDescription": "Counts the total number of DRAM Read CAS commands, w/ and w/o auto-pre, issu…
14 "BriefDescription": "write requests to memory controller. Derived from unc_m_cas_count.wr",
19 …"PublicDescription": "Counts the total number of DRAM Write CAS commands issued, w/ and w/o auto-p…
30 …number of DRAM Activate commands sent on this channel. Activate commands are issued to open up a …
41 …number of DRAM Activate commands sent on this channel. Activate commands are issued to open up a …
51 "PublicDescription": "Counts the total number of DRAM CAS commands issued on this channel.",
61 …"PublicDescription": "Counts the total number of DRAM Read CAS commands, w/ and w/o auto-pre, issu…
66 "BriefDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM RD_CAS commands w/auto-pre",
72 …_CAS Commands. : DRAM RD_CAS commands w/auto-pre : DRAM RD_CAS and WR_CAS Commands : Counts the to…
[all …]
/linux/Documentation/devicetree/bindings/firmware/
H A Dcznic,turris-omnia-mcu.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/firmware/cznic,turris-omnia-mcu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marek Behún <kabel@kernel.org>
13 The MCU on Turris Omnia acts as a system controller providing additional
18 const: cznic,turris-omnia-mcu
27 interrupt-controller: true
29 '#interrupt-cells':
32 The first cell specifies the interrupt number (0 to 63), the second cell
[all …]
/linux/Documentation/devicetree/bindings/pci/
H A Dralink,rt3883-pci.txt1 * Mediatek/Ralink RT3883 PCI controller
7 - compatible: must be "ralink,rt3883-pci"
9 - reg: specifies the physical base address of the controller and
12 - #address-cells: specifies the number of cells needed to encode an
15 - #size-cells: specifies the number of cells used to represent the size
18 - ranges: specifies the translation between child address space and parent
23 - status: indicates the operational status of the device.
28 The main node must have two child nodes which describes the built-in
29 interrupt controller and the PCI host bridge.
31 a) Interrupt controller:
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/linux/drivers/pinctrl/samsung/
H A Dpinctrl-samsung.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * pin-controller/pin-mux/pin-config/gpio-driver for Samsung's SoC's.
25 * enum pincfg_type - possible pin configuration types supported.
46 * packed together into a 16-bits. The upper 8-bits represent the configuration
47 * type and the lower 8-bits hold the value of the configuration type.
70 * enum pud_index - Possible index values to access the pud_val array.
84 * enum eint_type - possible external interrupt types.
90 * Samsung GPIO controller groups all the available pins into banks. The pins
104 /* maximum length of a pin in pin descriptor (example: "gpa0-0") */
135 * struct samsung_pin_bank_data: represent a controller pin-bank (init data).
[all …]
H A Dpinctrl-exynos-arm.c1 // SPDX-License-Identifier: GPL-2.0+
20 #include <linux/soc/samsung/exynos-regs-pmu.h>
22 #include "pinctrl-samsung.h"
23 #include "pinctrl-exynos.h"
35 /* Retention control for S5PV210 are located at the end of clock controller */
49 unsigned int *pud_val = drvdata->pud_val; in s5pv210_pud_value_init()
58 void __iomem *clk_base = (void __iomem *)drvdata->retention_ctrl->priv; in s5pv210_retention_disable()
75 ctrl = devm_kzalloc(drvdata->dev, sizeof(*ctrl), GFP_KERNEL); in s5pv210_retention_init()
77 return ERR_PTR(-ENOMEM); in s5pv210_retention_init()
79 np = of_find_compatible_node(NULL, NULL, "samsung,s5pv210-clock"); in s5pv210_retention_init()
[all …]
H A Dpinctrl-exynos-arm64.c1 // SPDX-License-Identifier: GPL-2.0+
17 #include <linux/soc/samsung/exynos-regs-pmu.h>
19 #include "pinctrl-samsung.h"
20 #include "pinctrl-exynos.h"
53 * Bank type for non-alive type. Bit fields:
71 * Bank type for non-alive type. Bit fields:
80 * Bank type for non-alive type. Bit fields:
91 /* pin banks of exynos2200 pin-controller - ALIVE */
103 /* pin banks of exynos2200 pin-controller - CMGP */
130 /* pin banks of exynos2200 pin-controller - HSI1 */
[all …]
/linux/Documentation/devicetree/bindings/i2c/
H A Di2c-pxa-pci-ce4100.txt2 ----------
4 CE4100 has one PCI device which is described as the I2C-Controller. This
5 PCI device has three PCI-bars, each bar contains a complete I2C
6 controller. So we have a total of three independent I2C-Controllers
8 The driver is probed via the PCI-ID and is gathering the information of
10 Grant Likely recommended to use the ranges property to map the PCI-Bar
11 number to its physical address and to use this to find the child nodes
12 of the specific I2C controller. This were his exact words:
22 non-zero if you had 2 or more devices mapped off
30 ------------------------------------------------
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/linux/Documentation/devicetree/bindings/pinctrl/
H A Dpinctrl-st.txt1 *ST pin controller.
3 Each multi-function pin is controlled, driven and routed through the
5 and multiple alternate functions(ALT1 - ALTx) that directly connect
14 GPIO bank can have one of the two possible types of interrupt-wirings.
17 reduces number of overall interrupts numbers required. All these banks belong to
20 | |----> [gpio-bank (n) ]
21 | |----> [gpio-bank (n + 1)]
22 [irqN]-- | irq-mux |----> [gpio-bank (n + 2)]
23 | |----> [gpio-bank (... )]
24 |_________|----> [gpio-bank (n + 7)]
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H A Dapple,pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Apple GPIO controller
10 - Mark Kettenis <kettenis@openbsd.org>
13 The Apple GPIO controller is a simple combined pin and GPIO
14 controller present on Apple ARM SoC platforms, including various
20 - items:
21 - enum:
22 - apple,t6020-pinctrl
[all …]
H A Dbrcm,nsp-gpio.txt1 Broadcom Northstar plus (NSP) GPIO/PINCONF Controller
4 - compatible:
5 Must be "brcm,nsp-gpio-a"
7 - reg:
11 - #gpio-cells:
12 Must be two. The first cell is the GPIO pin number (within the
13 controller's pin space) and the second cell is used for the following:
16 - gpio-controller:
17 Specifies that the node is a GPIO controller
19 - ngpios:
[all …]
/linux/include/linux/
H A Dmhi.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
10 #include <linux/dma-direction.h>
17 #include <linux/device-id/mhi.h>
28 * enum mhi_callback - MHI callback
52 * enum mhi_flags - Transfer flags
64 * enum mhi_device_type - Device types
74 * enum mhi_ch_type - Channel types
90 * struct mhi_buf - MHI Buffer description
93 * ECA - Event context array data
[all …]
/linux/Documentation/devicetree/bindings/mfd/
H A Dtps65912.txt4 - compatible : Should be "ti,tps65912".
5 - reg : Slave address or chip select number (I2C / SPI).
6 - interrupts : The interrupt line the device is connected to.
7 - interrupt-controller : Marks the device node as an interrupt controller.
8 - #interrupt-cells : The number of cells to describe an IRQ, should be 2.
9 The first cell is the IRQ number.
11 masks from ../interrupt-controller/interrupts.txt.
12 - gpio-controller : Marks the device node as a GPIO Controller.
13 - #gpio-cells : Should be two. The first cell is the pin number and
16 - regulators: : List of child nodes that specify the regulator
[all …]
H A Daltera-a10sr.txt4 - compatible : "altr,a10sr"
5 - spi-max-frequency : Maximum SPI frequency.
6 - reg : The SPI Chip Select address for the Arria10
8 - interrupts : The interrupt line the device is connected to.
9 - interrupt-controller : Marks the device node as an interrupt controller.
10 - #interrupt-cells : The number of cells to describe an IRQ, should be 2.
11 The first cell is the IRQ number.
13 masks from ../interrupt-controller/interrupts.txt.
15 The A10SR consists of these sub-devices:
18 ------ ----------
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/linux/drivers/cdx/
H A Dcdx.h1 /* SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2022-2023, Advanced Micro Devices, Inc.
14 * struct cdx_dev_params - CDX device parameters
15 * @cdx: CDX controller associated with the device
21 * @bus_num: Bus number for this CDX device
22 * @dev_num: Device number for this device
24 * @res_count: number of valid MMIO regions
29 * @num_msi: Number of MSI's supported by the device
50 * cdx_register_controller - Register a CDX controller and its ports
52 * @cdx: The CDX controller to register
[all …]
/linux/tools/perf/pmu-events/arch/x86/jaketown/
H A Duncore-cache.json15 …ed in Counter 0. The filtering available is found in the control register - threshold, invert an…
31 …number of times the LLC was accessed - this includes code, data, prefetches and hints coming from …
41 …number of times the LLC was accessed - this includes code, data, prefetches and hints coming from …
51 …number of times the LLC was accessed - this includes code, data, prefetches and hints coming from …
61 …number of times the LLC was accessed - this includes code, data, prefetches and hints coming from …
71 …"PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filt…
81 …"PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filt…
91 …"PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filt…
101 …"PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filt…
111 …"PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filt…
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/linux/tools/perf/pmu-events/arch/x86/skylake/
H A Duncore-interconnect.json3 …"BriefDescription": "Number of entries allocated. Account for Any type: e.g. Snoop, Core aperture,…
12 …Number of all Core entries outstanding for the memory controller. The outstanding interval starts …
21 …uest outstanding is waiting for data return from memory controller. Account for coherent and non-c…
31 …"BriefDescription": "Number of Core Data Read entries outstanding for the memory controller. The o…
49 …"BriefDescription": "Number of Core coherent Data Read requests sent to memory controller whose da…
58 …"BriefDescription": "Number of Core coherent Data Read requests sent to memory controller whose da…
67 …"BriefDescription": "Number of Writes allocated - any write transactions: full/partials writes and…
/linux/Documentation/devicetree/bindings/input/
H A Dsamsung,s3c6410-keypad.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/input/samsung,s3c6410-keypad.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung SoC series Keypad Controller
10 Samsung SoC Keypad controller is used to interface a SoC with a matrix-type
11 keypad device. The keypad controller supports multiple row and column lines.
13 The keypad controller can sense a key-press and key-release and report the
17 - Krzysztof Kozlowski <krzk@kernel.org>
22 - samsung,s3c6410-keypad
[all …]
/linux/Documentation/devicetree/bindings/dma/
H A Dfsl-qdma.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/fsl-qdma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP Layerscape SoC qDMA Controller
10 - Frank Li <Frank.Li@nxp.com>
15 - const: fsl,ls1021a-qdma
16 - items:
17 - enum:
18 - fsl,ls1028a-qdma
[all …]

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