| /linux/drivers/scsi/ |
| H A D | script_asm.pl | 1 #!/usr/bin/perl -s
2 # SPDX-License-Identifier: GPL-2.0-or-later
12 # +1 (303) 786-7975
14 # Support for 53c710 (via -ncr7x0_family switch) added by Richard
15 # Hirst <richard@sleepie.demon.co.uk> - 15th March 1997
38 # XXX - set these with command line options
43 #$prefix; # (set by perl -s)
58 # XXX - replace references to the *_810 constants with general constants
62 # XXX - NCR53c710 only implements
141 $identifier = '[A-Za-z_][A-Za-z_0-9]*';
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| /linux/arch/xtensa/variants/dc232b/include/variant/ |
| H A D | tie-asm.h | 2 * This header file contains assembly-language definitions (assembly
10 * Copyright (C) 1999-2007 Tensilica Inc.
16 /* Selection parameter values for save-area save/restore macros: */
24 #define XTHAL_SAS_CALR 0x0010 /* caller-saved */
25 #define XTHAL_SAS_CALE 0x0020 /* callee-saved */
32 /* Macro to save all non-coprocessor (extra) custom TIE and optional state
33 * (not including zero-overhead loop registers).
37 .macro xchal_ncp_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL
39 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~\select
40 xchal_sa_align \ptr, 0, 1024-8, 4, 4
[all …]
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| /linux/arch/xtensa/variants/test_mmuhifi_c3/include/variant/ |
| H A D | tie-asm.h | 2 * This header file contains assembly-language definitions (assembly
9 * Copyright (C) 1999-2009 Tensilica Inc.
15 /* Selection parameter values for save-area save/restore macros: */
23 #define XTHAL_SAS_CALR 0x0010 /* caller-saved */
24 #define XTHAL_SAS_CALE 0x0020 /* callee-saved */
31 /* Macro to save all non-coprocessor (extra) custom TIE and optional state
32 * (not including zero-overhead loop registers).
36 .macro xchal_ncp_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL
38 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~\select
39 xchal_sa_align \ptr, 0, 1024-4, 4, 4
[all …]
|
| /linux/arch/xtensa/variants/de212/include/variant/ |
| H A D | tie-asm.h | 2 * tie-asm.h -- compile-time HAL assembler definitions dependent on CORE & TIE
7 /* This header file contains assembly-language definitions (assembly
11 Copyright (c) 1999-2015 Cadence Design Systems Inc.
35 /* Selection parameter values for save-area save/restore macros: */
45 #define XTHAL_SAS_CALR 0x0010 /* caller-saved */
46 #define XTHAL_SAS_CALE 0x0020 /* callee-saved */
57 * Macro to store all non-coprocessor (extra) custom TIE and optional state
58 * (not including zero-overhead loop registers).
70 * select Select what category(ies) of registers to store, as a bitmask
72 * alloc Select what category(ies) of registers to allocate; if any
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|
| /linux/arch/xtensa/variants/csp/include/variant/ |
| H A D | tie-asm.h | 2 * tie-asm.h -- compile-time HAL assembler definitions dependent on CORE & TIE
7 /* This header file contains assembly-language definitions (assembly
11 Copyright (c) 1999-2015 Cadence Design Systems Inc.
35 /* Selection parameter values for save-area save/restore macros: */
45 #define XTHAL_SAS_CALR 0x0010 /* caller-saved */
46 #define XTHAL_SAS_CALE 0x0020 /* callee-saved */
57 * Macro to store all non-coprocessor (extra) custom TIE and optional state
58 * (not including zero-overhead loop registers).
70 * select Select what category(ies) of registers to store, as a bitmask
72 * alloc Select what category(ies) of registers to allocate; if any
[all …]
|
| /linux/arch/xtensa/variants/dc233c/include/variant/ |
| H A D | tie-asm.h | 2 * tie-asm.h -- compile-time HAL assembler definitions dependent on CORE & TIE
7 /* This header file contains assembly-language definitions (assembly
11 Copyright (c) 1999-2010 Tensilica Inc.
35 /* Selection parameter values for save-area save/restore macros: */
45 #define XTHAL_SAS_CALR 0x0010 /* caller-saved */
46 #define XTHAL_SAS_CALE 0x0020 /* callee-saved */
58 * Macro to save all non-coprocessor (extra) custom TIE and optional state
59 * (not including zero-overhead loop registers).
71 * select Select what category(ies) of registers to store, as a bitmask
73 * alloc Select what category(ies) of registers to allocate; if any
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|
| /linux/Documentation/arch/sparc/oradax/ |
| H A D | dax-hv-api.txt | 3 Publication date 2017-09-25 08:21
5 Extracted via "pdftotext -f 547 -l 572 -layout sun4v_20170925.pdf"
16 live-migration and other system management activities.
20 …high speed processoring of database-centric operations. The coprocessors may support one or more of
28 …e Completion Area and, unless execution order is specifically restricted through the use of serial-
29 …conditional flags, the execution order of submitted CCBs is arbitrary. Likewise, the time to compl…
45 …device node in the guest MD (Section 8.24.17, “Database Analytics Accelerators (DAX) virtual-device
51 36.1.1.1. "ORCL,sun4v-dax" Device Compatibility
54 • No-op/Sync
75 • Select
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| /linux/arch/powerpc/platforms/8xx/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
4 select CPM
16 select CPM1
24 select CPM1
25 select OF_DYNAMIC
33 bool "Embedded Planet EP88xC (a.k.a. CWH-PPC-885XN-VE)"
34 select CPM1
39 MPC885 Evaluation System and/or the CWH-PPC-885XN-VE.
43 select CPM1
50 select CPM1
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|
| /linux/lib/vdso/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
36 Select to add multiplication overflow protection to the VDSO
37 time getter functions for the price of an extra conditional
|
| /linux/arch/xtensa/variants/test_kc705_hifi/include/variant/ |
| H A D | tie-asm.h | 2 * tie-asm.h -- compile-time HAL assembler definitions dependent on CORE & TIE
7 /* This header file contains assembly-language definitions (assembly
11 Copyright (c) 1999-2014 Tensilica Inc.
35 /* Selection parameter values for save-area save/restore macros: */
45 #define XTHAL_SAS_CALR 0x0010 /* caller-saved */
46 #define XTHAL_SAS_CALE 0x0020 /* callee-saved */
58 * Macro to save all non-coprocessor (extra) custom TIE and optional state
59 * (not including zero-overhead loop registers).
71 * select Select what category(ies) of registers to store, as a bitmask
73 * alloc Select what category(ies) of registers to allocate; if any
[all …]
|
| /linux/arch/xtensa/variants/test_kc705_be/include/variant/ |
| H A D | tie-asm.h | 2 * tie-asm.h -- compile-time HAL assembler definitions dependent on CORE & TIE
7 /* This header file contains assembly-language definitions (assembly
11 Copyright (c) 1999-2015 Cadence Design Systems Inc.
35 /* Selection parameter values for save-area save/restore macros: */
45 #define XTHAL_SAS_CALR 0x0010 /* caller-saved */
46 #define XTHAL_SAS_CALE 0x0020 /* callee-saved */
57 * Macro to store all non-coprocessor (extra) custom TIE and optional state
58 * (not including zero-overhead loop registers).
70 * select Select what category(ies) of registers to store, as a bitmask
72 * alloc Select what category(ies) of registers to allocate; if any
[all …]
|
| /linux/arch/sh/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
4 select ARCH_32BIT_OFF_T
5 select ARCH_HAS_CPU_CACHE_ALIASING
6 select ARCH_HAVE_NMI_SAFE_CMPXCHG if (GUSA_RB || CPU_SH4A)
7 select ARCH_HAS_BINFMT_FLAT if !MMU
8 select ARCH_HAS_CPU_FINALIZE_INIT
9 select ARCH_HAS_CURRENT_STACK_POINTER
10 select ARCH_HAS_GIGANTIC_PAGE
11 select ARCH_HAS_GCOV_PROFILE_ALL
12 select ARCH_HAS_PTE_SPECIAL
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|
| /linux/arch/arc/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
3 # Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
8 select ARC_TIMERS
9 select ARCH_HAS_CPU_CACHE_ALIASING
10 select ARCH_HAS_CACHE_LINE_SIZE
11 select ARCH_HAS_DEBUG_VM_PGTABLE
12 select ARCH_HAS_DMA_PREP_COHERENT
13 select ARCH_HAS_PTE_SPECIAL
14 select ARCH_HAS_SETUP_DMA_OPS
15 select ARCH_HAS_SYNC_DMA_FOR_CPU
[all …]
|
| /linux/arch/x86/kernel/cpu/ |
| H A D | bugs.c | 1 // SPDX-License-Identifier: GPL-2.0
6 * - Rafael R. Reilova (moved everything from head.S),
8 * - Channing Corn (tests & fixes),
9 * - Andrew D. Balsa (code cleanup).
20 #include <asm/spec-ctrl.h>
24 #include <asm/processor-flags.h>
53 /* The base value of the SPEC_CTRL MSR without task-specific bits set */
57 /* The current value of the SPEC_CTRL MSR with task-specific bits set */
89 * When KERNEL_IBRS this MSR is written on return-to-user, unless in update_spec_ctrl_cond()
109 /* Control conditional STIBP in switch_to() */
[all …]
|
| /linux/Documentation/admin-guide/media/ |
| H A D | bt8xx.rst | 1 .. SPDX-License-Identifier: GPL-2.0
16 -------------------
21 Please see Documentation/admin-guide/media/bttv-cardlist.rst for a complete
28 ./scripts/config -e PCI
29 ./scripts/config -e INPUT
30 ./scripts/config -m I2C
31 ./scripts/config -m MEDIA_SUPPORT
32 ./scripts/config -e MEDIA_PCI_SUPPORT
33 ./scripts/config -e MEDIA_ANALOG_TV_SUPPORT
34 ./scripts/config -e MEDIA_DIGITAL_TV_SUPPORT
[all …]
|
| /linux/Documentation/ABI/testing/ |
| H A D | sysfs-bus-coresight-devices-etm4x | 76 Description: (Read) Indicates the number of single-shot comparator controls that
155 Description: (RW) In non-secure state, each bit controls whether instruction
162 Description: (RW) Select which address comparator or pair (of comparators) to
187 Description: (RW) Select which sequensor.
212 Description: (RW) Select which counter unit to work with.
238 Description: (RW) Select which resource selection unit to work with.
250 Description: (RW) Select which context ID comparator to work with.
269 Description: (RW) Select which virtual machine ID comparator to work with.
290 non-secure exception levels.
310 Description: (RW) Select the single shot control register to access.
[all …]
|
| /linux/Documentation/userspace-api/media/v4l/ |
| H A D | vidioc-enuminput.rst | 1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
13 VIDIOC_ENUMINPUT - Enumerate video inputs
45 .. flat-table:: struct v4l2_input
46 :header-rows: 0
47 :stub-columns: 0
50 * - __u32
51 - ``index``
52 - Identifies the input, set by the application.
53 * - __u8
54 - ``name``\ [32]
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|
| /linux/arch/arm/include/asm/ |
| H A D | assembler.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 1996-2000 Russell King
10 * Do not include any C declarations in this file - it is included by
21 #include <asm/opcodes-virt.h>
22 #include <asm/asm-offsets.h>
26 #include <asm/uaccess-asm.h>
57 /* Select code for any configuration running in BE8 mode */
77 * set to write-allocate (this would need further testing on XScale when WA
128 stmdb sp!, {r0-r3, ip, lr}
132 ldmia sp!, {r0-r3, ip, lr}
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| /linux/Documentation/staging/ |
| H A D | static-keys.rst | 30 performance-sensitive fast-path kernel code, via a GCC feature and a code
56 Currently, tracepoints are implemented using a conditional branch. The
57 conditional check requires checking a global variable for each tracepoint.
74 https://gcc.gnu.org/ml/gcc-patches/2009-07/msg01556.html
77 by default, without the need to check memory. Then, at run-time, we can patch
86 consist of a single atomic 'no-op' instruction (5 bytes on x86), in the
87 straight-line code path. When the branch is 'flipped', we will patch the
88 'no-op' in the straight-line codepath with a 'jump' instruction to the
89 out-of-line true branch. Thus, changing branch direction is expensive but
110 allocated at run-time.
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|
| /linux/lib/zstd/common/ |
| H A D | error_private.h | 5 * This source code is licensed under both the BSD-style license (found in the
8 * You may select, at your option, one of the above-listed licenses.
28 * Compiler-specific
33 /*-****************************************
40 /*-****************************************
45 #define ZSTD_ERROR(name) ((size_t)-PREFIX(name))
49 …tErrorCode(size_t code) { if (!ERR_isError(code)) return (ERR_enum)0; return (ERR_enum) (0-code); } in ERR_getErrorCode()
56 /*-****************************************
70 * This is a helper function to help force C99-correctness during compilation.
98 * In order to do that (particularly, printing the conditional that failed),
|
| /linux/arch/arm64/lib/ |
| H A D | strlen.S | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (c) 2013-2021, Arm Limited.
6 * https://github.com/ARM-software/optimized-routines/blob/98e4d6a5c13c8e54/string/aarch64/strlen.S
11 #include <asm/mte-def.h>
15 * ARMv8-a, AArch64, unaligned accesses, min page size 4k.
36 /* NUL detection works on the principle that (X - 1) & (~X) & 0x80
37 (=> (X - 1) & ~(X | 0x7f)) is non-zero iff a byte is zero, and
39 (X - 1) & 0x80 is zero for non-NUL ASCII characters, but gives
48 * (16-byte) granularity, and we must ensure that no access straddles this
60 byte we calculate the length from the 2 8-byte words using
[all …]
|
| /linux/scripts/kconfig/ |
| H A D | expr.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 2002 Roman Zippel <zippel@linux-m68k.org>
38 * struct expr - expression
57 #define EXPR_NOT(dep) (2-(dep))
149 #define SYMBOL_WRITTEN 0x0800 /* track info to avoid double-write to .config */
168 * select BAR
182 P_SELECT, /* select BAR */
188 struct property *next; /* next property - null if last */
190 const char *text; /* the prompt value - P_PROMPT, P_MENU, P_COMMENT */
192 struct expr *expr; /* the optional conditional part of the property */
[all …]
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| /linux/include/uapi/drm/ |
| H A D | etnaviv_drm.h | 1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
28 * subject to backwards-compatibility constraints:
40 /* timeouts are specified in clock-monotonic absolute times (to simplify
133 * relocbuf->gpuaddr + reloc_offset
147 * one) entry in the submit->bos[] table.
183 * one or more cmdstream buffers. This allows for conditional execution
184 * (context-restore), and IB buffers needed for per tile/bin draw cmds.
236 __u32 handle; /* out, non-zero handle */
253 __u8 iter; /* in/out, select pm domain at index iter */
263 __u16 iter; /* in/out, select pm source at index iter */
|
| /linux/Documentation/trace/coresight/ |
| H A D | coresight-etm4x-reference.rst | 11 ---------------------------
20 ----
25 Bit select trace features. See ‘mode’ section below. Bits
37 ----
47 ----
52 - > 0 : Programs up the hardware with the current values held in the driver
55 - = 0 : disable trace hardware.
60 ----
72 ----
77 When FEAT_TRF is implemented, value of TRFCR_ELx.TS used for trace session. Otherwise -1
[all …]
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| /linux/Documentation/devicetree/bindings/riscv/ |
| H A D | extensions.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V ISA extensions
10 - Paul Walmsley <paul.walmsley@sifive.com>
11 - Palmer Dabbelt <palmer@sifive.com>
12 - Conor Dooley <conor@kernel.org>
15 RISC-V has a large number of extensions, some of which are "standard"
16 extensions, meaning they are ratified by RISC-V International, and others
27 select:
[all …]
|