1 // SPDX-License-Identifier: GPL-2.0
6  *	- Rafael R. Reilova (moved everything from head.S),
8  *	- Channing Corn (tests & fixes),
9  *	- Andrew D. Balsa (code cleanup).
20 #include <asm/spec-ctrl.h>
24 #include <asm/processor-flags.h>
53 /* The base value of the SPEC_CTRL MSR without task-specific bits set */
57 /* The current value of the SPEC_CTRL MSR with task-specific bits set */
88 	 * When KERNEL_IBRS this MSR is written on return-to-user, unless  in update_spec_ctrl_cond()
108 /* Control conditional STIBP in switch_to() */
110 /* Control conditional IBPB in switch_mm() */
154 	/* Select the proper CPU mitigations before patching alternatives: */  in cpu_select_mitigations()
209 		hostval = ssbd_tif_to_spec_ctrl(ti->flags);  in x86_virt_spec_ctrl()
238 /* Default mitigation for MDS-affected CPUs */
257 /* Default mitigation for TAA-affected CPUs */
311 		return -EINVAL;  in mds_cmdline()
383 	 * TSX is enabled, select alternate mitigation for TAA which is  in taa_select_mitigation()
401 		return -EINVAL;  in tsx_async_abort_parse_cmdline()
449 	 * mitigations, disable KVM-only mitigation in that case.  in mmio_select_mitigation()
457 	 * If Processor-MMIO-Stale-Data bug is present and Fill Buffer data can  in mmio_select_mitigation()
489 		return -EINVAL;  in mmio_stale_data_parse_cmdline()
534 		return -EINVAL;  in rfds_parse_cmdline()
607 	 * As these mitigations are inter-related and rely on VERW instruction  in md_clear_select_mitigation()
702 		return -EINVAL;  in srbds_parse_cmdline()
728 	pr_info("Conditional flush on switch_mm() enabled\n");  in l1d_flush_select_mitigation()
866 		return -EINVAL;  in gds_parse_cmdline()
909 	 * Consider SMAP to be non-functional as a mitigation on these  in smap_works_speculatively()
928 		 * path of a conditional swapgs with a user-controlled GS  in spectre_v1_select_mitigation()
953 			 * Enable lfences in the kernel entry (non-swapgs)  in spectre_v1_select_mitigation()
1012 		return -EINVAL;  in retbleed_parse_cmdline()
1137 		 * software-based untraining so clear those in case some  in retbleed_select_mitigation()
1213 	return spectre_v2_bad_module ? " - vulnerable module loaded" : "";  in spectre_v2_module_string()
1280 	[SPECTRE_V2_USER_STRICT_PREFERRED]	= "User space: Mitigation: STIBP always-on protection",
1401 			"always-on" : "conditional");  in spectre_v2_user_select_mitigation()
1408 	 * Intel's Enhanced IBRS also protects against cross-thread branch target  in spectre_v2_user_select_mitigation()
1409 	 * injection in user-mode as the IBRS bit remains always set which  in spectre_v2_user_select_mitigation()
1410 	 * implicitly enables cross-thread protections.  However, in legacy IBRS  in spectre_v2_user_select_mitigation()
1413 	 * These modes therefore disable the implicit cross-thread protection,  in spectre_v2_user_select_mitigation()
1424 	 * If STIBP support is not being forced, check if STIBP always-on  in spectre_v2_user_select_mitigation()
1435 			pr_info("Selecting STIBP always-on mode to complement retbleed mitigation\n");  in spectre_v2_user_select_mitigation()
1512 		pr_err("%s selected but not compiled in. Switching to AUTO select\n",  in spectre_v2_parse_cmdline()
1521 		pr_err("%s selected but CPU doesn't have Enhanced or Automatic IBRS. Switching to AUTO select\n",  in spectre_v2_parse_cmdline()
1529 		pr_err("%s selected, but CPU doesn't have a serializing LFENCE. Switching to AUTO select\n",  in spectre_v2_parse_cmdline()
1535 		pr_err("%s selected but not compiled in. Switching to AUTO select\n",  in spectre_v2_parse_cmdline()
1541 		pr_err("%s selected but not Intel CPU. Switching to AUTO select\n",  in spectre_v2_parse_cmdline()
1547 		pr_err("%s selected but CPU doesn't have IBRS. Switching to AUTO select\n",  in spectre_v2_parse_cmdline()
1553 		pr_err("%s selected but running as XenPV guest. Switching to AUTO select\n",  in spectre_v2_parse_cmdline()
1575 /* Disable in-kernel use of non-RSB RET predictors */
1598 	 * code related to RSB-related mitigations.  Before doing so, carefully  in spectre_v2_select_rsb_mitigation()
1601 	 *   Documentation/admin-guide/hw-vuln/rsb.rst  in spectre_v2_select_rsb_mitigation()
1605 	 *   - User->user RSB attacks are conditionally mitigated during  in spectre_v2_select_rsb_mitigation()
1606 	 *     context switches by cond_mitigation -> write_ibpb().  in spectre_v2_select_rsb_mitigation()
1608 	 *   - User->kernel and guest->host attacks are mitigated by eIBRS or  in spectre_v2_select_rsb_mitigation()
1624 			pr_info("Spectre v2 / PBRSB-eIBRS: Retire a single CALL on VMEXIT\n");  in spectre_v2_select_rsb_mitigation()
1672 		return -EINVAL;  in spectre_bhi_parse_cmdline()
1821 	 * JMPs gets protection against BHI and Intramode-BTI, but RET  in spectre_v2_select_mitigation()
1822 	 * prediction from a non-RSB predictor is still a risk.  in spectre_v2_select_mitigation()
1844 	 * the user might select retpoline on the kernel command line and if  in spectre_v2_select_mitigation()
1845 	 * the CPU supports Enhanced IBRS, kernel might un-intentionally not  in spectre_v2_select_mitigation()
1885 		mask & SPEC_CTRL_STIBP ? "always-on" : "off");  in update_stibp_strict()
1924 …n, data leak possible. See https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/mds.html for…
1925 …n, data leak possible. See https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/tsx_async_ab…
1926 …n, data leak possible. See https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/processor_mm…
2091 	 *  - X86_BUG_SPEC_STORE_BYPASS - CPU is susceptible.  in __ssb_select_mitigation()
2092 	 *  - X86_FEATURE_SSBD - CPU is able to turn off speculative store bypass  in __ssb_select_mitigation()
2093 	 *  - X86_FEATURE_SPEC_STORE_BYPASS_DISABLE - engage the mitigation  in __ssb_select_mitigation()
2131 	 * task, but for a non-current task delay setting the CPU  in task_update_spec_tif()
2145 		return -EPERM;  in l1d_flush_prctl_set()
2149 		set_ti_thread_flag(&task->thread_info, TIF_SPEC_L1D_FLUSH);  in l1d_flush_prctl_set()
2152 		clear_ti_thread_flag(&task->thread_info, TIF_SPEC_L1D_FLUSH);  in l1d_flush_prctl_set()
2155 		return -ERANGE;  in l1d_flush_prctl_set()
2163 		return -ENXIO;  in ssb_prctl_set()
2169 			return -EPERM;  in ssb_prctl_set()
2187 			return -EPERM;  in ssb_prctl_set()
2193 		return -ERANGE;  in ssb_prctl_set()
2221 		 * If either is set to conditional, allow the task flag to be  in ib_prctl_set()
2222 		 * updated, unless it was force-disabled by a previous prctl  in ib_prctl_set()
2231 			return -EPERM;  in ib_prctl_set()
2244 			return -EPERM;  in ib_prctl_set()
2257 		return -ERANGE;  in ib_prctl_set()
2273 		return -ENODEV;  in arch_prctl_spec_ctrl_set()
2293 	if (test_ti_thread_flag(&task->thread_info, TIF_SPEC_L1D_FLUSH))  in l1d_flush_prctl_get()
2353 		return -ENODEV;  in arch_prctl_spec_ctrl_get()
2372 /* Default mitigation for L1TF-affected CPUs */
2397 	if (c->x86 != 6)  in override_cache_bits()
2400 	switch (c->x86_vfm) {  in override_cache_bits()
2414 		if (c->x86_cache_bits < 44)  in override_cache_bits()
2415 			c->x86_cache_bits = 44;  in override_cache_bits()
2455 			e820__mapped_any(half_pa, ULLONG_MAX - half_pa, E820_TYPE_RAM)) {  in l1tf_select_mitigation()
2460 …pr_info("Reading https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html might help y…  in l1tf_select_mitigation()
2473 		return -EINVAL;  in l1tf_cmdline()
2531 		return -EINVAL;  in srso_parse_cmdline()
2537 	else if (!strcmp(str, "safe-ret"))  in srso_parse_cmdline()
2541 	else if (!strcmp(str, "ibpb-vmexit"))  in srso_parse_cmdline()
2550 #define SRSO_NOTICE "WARNING: See https://kernel.org/doc/html/latest/admin-guide/hw-vuln/srso.html …
2581 		pr_warn("IBPB-extending microcode not applied!\n");  in srso_select_mitigation()
2633 				 * software-based untraining so clear those in case some  in srso_select_mitigation()
2702 	[VMENTER_L1D_FLUSH_COND]		= "conditional cache flushes",
2815 		return "; STIBP: always-on";  in stibp_state()
2819 			return "; STIBP: conditional";  in stibp_state()
2828 			return "; IBPB: always-on";  in ibpb_state()
2830 			return "; IBPB: conditional";  in ibpb_state()
2841 			return "; PBRSB-eIBRS: SW sequence";  in pbrsb_eibrs_state()
2843 			return "; PBRSB-eIBRS: Vulnerable";  in pbrsb_eibrs_state()
2845 		return "; PBRSB-eIBRS: Not affected";  in pbrsb_eibrs_state()
2902 			return sysfs_emit(buf, "Vulnerable: untrained return thunk / IBPB on non-AMD based uarch\n");  in retbleed_show_state()