Home
last modified time | relevance | path

Searched full:cmu_top (Results 1 – 25 of 26) sorted by relevance

12

/linux/Documentation/devicetree/bindings/clock/
H A Dsamsung,exynos8895-clock.yaml21 CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and
23 derived from CMU_TOP.
73 - description: CMU_FSYS0 BUS clock (from CMU_TOP)
74 - description: CMU_FSYS0 DPGTC clock (from CMU_TOP)
75 - description: CMU_FSYS0 MMC_EMBD clock (from CMU_TOP)
76 - description: CMU_FSYS0 UFS_EMBD clock (from CMU_TOP)
77 - description: CMU_FSYS0 USBDRD30 clock (from CMU_TOP)
99 - description: CMU_FSYS1 BUS clock (from CMU_TOP)
100 - description: CMU_FSYS1 PCIE clock (from CMU_TOP)
101 - description: CMU_FSYS1 UFS_CARD clock (from CMU_TOP)
[all …]
H A Dsamsung,exynos7885-clock.yaml23 CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and
24 dividers; all other leaf clocks (other CMUs) are usually derived from CMU_TOP.
81 - description: CMU_CORE bus clock (from CMU_TOP)
82 - description: CCI clock (from CMU_TOP)
83 - description: G3D clock (from CMU_TOP)
103 - description: CMU_FSYS bus clock (from CMU_TOP)
104 - description: MMC_CARD clock (from CMU_TOP)
105 - description: MMC_EMBD clock (from CMU_TOP)
106 - description: MMC_SDIO clock (from CMU_TOP)
107 - description: USB30DRD clock (from CMU_TOP)
[all …]
H A Dsamsung,exynos850-clock.yaml23 CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and
24 dividers; all other leaf clocks (other CMUs) are usually derived from CMU_TOP.
90 - description: CMU_APM bus clock (from CMU_TOP)
108 - description: AUD clock (from CMU_TOP)
144 - description: CMU_CORE bus clock (from CMU_TOP)
145 - description: CCI clock (from CMU_TOP)
146 - description: eMMC clock (from CMU_TOP)
147 - description: SSS clock (from CMU_TOP)
168 - description: CPUCL0 switch clock (from CMU_TOP)
169 - description: CPUCL0 debug clock (from CMU_TOP)
[all …]
H A Dsamsung,exynosautov9-clock.yaml23 CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and
25 derived from CMU_TOP.
88 - description: CMU_BUSMC bus clock (from CMU_TOP)
106 - description: CMU_CORE bus clock (from CMU_TOP)
124 - description: DPU Main bus clock (from CMU_TOP)
142 - description: CMU_FSYS0 bus clock (from CMU_TOP)
143 - description: CMU_FSYS0 pcie clock (from CMU_TOP)
162 - description: CMU_FSYS1 bus clock (from CMU_TOP)
163 - description: CMU_FSYS1 mmc card clock (from CMU_TOP)
164 - description: CMU_FSYS1 usb clock (from CMU_TOP)
[all …]
H A Dgoogle,gs101-clock.yaml19 CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and
20 dividers; all other leaf clocks (other CMUs) are usually derived from CMU_TOP.
88 - description: HSI0 bus clock (from CMU_TOP)
89 - description: DPGTC (from CMU_TOP)
90 - description: USB DRD controller clock (from CMU_TOP)
91 - description: USB Display Port debug clock (from CMU_TOP)
113 - description: High Speed Interface bus clock (from CMU_TOP)
114 - description: High Speed Interface pcie clock (from CMU_TOP)
115 - description: High Speed Interface ufs clock (from CMU_TOP)
116 - description: High Speed Interface mmc clock (from CMU_TOP)
[all …]
H A Dsamsung,exynos990-clock.yaml21 CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and
23 derived from CMU_TOP.
74 - description: Connectivity Peripheral 0/1 bus clock (from CMU_TOP)
75 - description: Connectivity Peripheral 0/1 IP clock (from CMU_TOP)
94 - description: CMU_HSI0 BUS clock (from CMU_TOP)
95 - description: CMU_HSI0 USB31DRD clock (from CMU_TOP)
96 - description: CMU_HSI0 USBDP_DEBUG clock (from CMU_TOP)
97 - description: CMU_HSI0 DPGTC clock (from CMU_TOP)
118 - description: CMU_PERIS BUS clock (from CMU_TOP)
153 <&cmu_top CLK_DOUT_CMU_HSI0_BUS>,
[all …]
H A Dsamsung,exynos5433-clock.yaml26 # CMU_TOP which generates clocks for
/linux/arch/arm64/boot/dts/exynos/
H A Dexynos7885.dtsi199 <&cmu_top CLK_DOUT_PERI_BUS>,
200 <&cmu_top CLK_DOUT_PERI_SPI0>,
201 <&cmu_top CLK_DOUT_PERI_SPI1>,
202 <&cmu_top CLK_DOUT_PERI_UART0>,
203 <&cmu_top CLK_DOUT_PERI_UART1>,
204 <&cmu_top CLK_DOUT_PERI_UART2>,
205 <&cmu_top CLK_DOUT_PERI_USI0>,
206 <&cmu_top CLK_DOUT_PERI_USI1>,
207 <&cmu_top CLK_DOUT_PERI_USI2>;
226 <&cmu_top CLK_DOUT_CORE_BUS>,
[all …]
H A Dexynos5433-bus.dtsi12 clocks = <&cmu_top CLK_ACLK_G2D_400>;
20 clocks = <&cmu_top CLK_ACLK_G2D_266>;
28 clocks = <&cmu_top CLK_ACLK_GSCL_333>;
36 clocks = <&cmu_top CLK_ACLK_HEVC_400>;
44 clocks = <&cmu_top CLK_SCLK_JPEG_MSCL>;
52 clocks = <&cmu_top CLK_ACLK_MFC_400>;
60 clocks = <&cmu_top CLK_ACLK_MSCL_400>;
68 clocks = <&cmu_top CLK_ACLK_BUS0_400>;
76 clocks = <&cmu_top CLK_ACLK_BUS1_400>;
H A Dexynos5433-tm2-common.dtsi228 <&cmu_top CLK_MOUT_AUD_PLL>,
229 <&cmu_top CLK_MOUT_AUD_PLL_USER_T>,
230 <&cmu_top CLK_MOUT_SCLK_AUDIO0>,
231 <&cmu_top CLK_MOUT_SCLK_AUDIO1>,
232 <&cmu_top CLK_MOUT_SCLK_SPDIF>,
241 <&cmu_top CLK_DIV_SCLK_AUDIO0>,
242 <&cmu_top CLK_DIV_SCLK_AUDIO1>,
243 <&cmu_top CLK_DIV_SCLK_PCM1>,
244 <&cmu_top CLK_DIV_SCLK_I2S1>;
246 assigned-clock-parents = <&cmu_top CLK_FOUT_AUD_PLL>,
[all …]
H A Dexynos850.dtsi254 clocks = <&oscclk>, <&cmu_top CLK_DOUT_PERI_BUS>,
255 <&cmu_top CLK_DOUT_PERI_UART>,
256 <&cmu_top CLK_DOUT_PERI_IP>;
266 clocks = <&oscclk>, <&cmu_top CLK_DOUT_CPUCL1_SWITCH>,
267 <&cmu_top CLK_DOUT_CPUCL1_DBG>;
277 clocks = <&oscclk>, <&cmu_top CLK_DOUT_CPUCL0_SWITCH>,
278 <&cmu_top CLK_DOUT_CPUCL0_DBG>;
288 clocks = <&oscclk>, <&cmu_top CLK_DOUT_G3D_SWITCH>;
297 clocks = <&oscclk>, <&cmu_top CLK_DOUT_CLKCMU_APM_BUS>;
315 clocks = <&oscclk>, <&cmu_top CLK_DOUT_CORE_BUS>,
[all …]
H A Dexynos8895.dtsi178 <&cmu_top CLK_DOUT_CMU_PERIS_BUS>;
221 <&cmu_top CLK_DOUT_CMU_PERIC0_BUS>,
222 <&cmu_top CLK_DOUT_CMU_PERIC0_UART_DBG>,
223 <&cmu_top CLK_DOUT_CMU_PERIC0_USI00>,
224 <&cmu_top CLK_DOUT_CMU_PERIC0_USI01>,
225 <&cmu_top CLK_DOUT_CMU_PERIC0_USI02>,
226 <&cmu_top CLK_DOUT_CMU_PERIC0_USI03>;
509 <&cmu_top CLK_DOUT_CMU_PERIC1_BUS>,
510 <&cmu_top CLK_DOUT_CMU_PERIC1_SPEEDY2>,
511 <&cmu_top CLK_DOUT_CMU_PERIC1_SPI_CAM0>,
[all …]
H A Dexynos2200-g0s.dts98 <&cmu_top CLK_DOUT_CMU_HSI0_NOC>,
99 <&cmu_top CLK_DOUT_CMU_HSI0_DPGTC>,
100 <&cmu_top CLK_DOUT_CMU_HSI0_DPOSC>,
101 <&cmu_top CLK_DOUT_CMU_HSI0_USB32DRD>;
H A Dexynosautov920.dtsi308 <&cmu_top DOUT_CLKCMU_MISC_NOC>;
412 <&cmu_top DOUT_CLKCMU_PERIC0_NOC>,
413 <&cmu_top DOUT_CLKCMU_PERIC0_IP>;
890 <&cmu_top DOUT_CLKCMU_PERIC1_NOC>,
891 <&cmu_top DOUT_CLKCMU_PERIC1_IP>;
1350 cmu_top: clock-controller@11000000 { label
1380 <&cmu_top DOUT_CLKCMU_HSI0_NOC>;
1397 <&cmu_top DOUT_CLKCMU_HSI1_NOC>,
1398 <&cmu_top DOUT_CLKCMU_HSI1_USBDRD>,
1399 <&cmu_top DOUT_CLKCMU_HSI1_MMC_CARD>;
[all …]
H A Dexynosautov9.dtsi180 <&cmu_top DOUT_CLKCMU_PERIS_BUS>;
191 <&cmu_top DOUT_CLKCMU_PERIC0_BUS>,
192 <&cmu_top DOUT_CLKCMU_PERIC0_IP>;
204 <&cmu_top DOUT_CLKCMU_PERIC1_BUS>,
205 <&cmu_top DOUT_CLKCMU_PERIC1_IP>;
217 <&cmu_top DOUT_CLKCMU_FSYS1_BUS>,
218 <&cmu_top GOUT_CLKCMU_FSYS1_MMC_CARD>,
219 <&cmu_top DOUT_CLKCMU_FSYS1_USBDRD>;
232 <&cmu_top DOUT_CLKCMU_FSYS0_BUS>,
233 <&cmu_top DOUT_CLKCMU_FSYS0_PCIE>;
[all …]
/linux/include/dt-bindings/clock/
H A Dsamsung,exynosautov9.h12 /* CMU_TOP */
19 /* MUX in CMU_TOP */
68 /* DIV in CMU_TOP */
120 /* GAT in CMU_TOP */
H A Dgoogle,gs101.h12 /* CMU_TOP PLL */
19 /* CMU_TOP MUX */
93 /* CMU_TOP Dividers */
168 /* CMU_TOP Gates */
H A Dexynos7885.h11 /* CMU_TOP */
H A Dexynos850.h12 /* CMU_TOP */
H A Dexynos5260-clk.h14 /* List Of Clocks For CMU_TOP */
H A Dsamsung,exynos990.h11 /* CMU_TOP */
H A Dsamsung,exynos8895.h12 /* CMU_TOP */
/linux/drivers/clk/samsung/
H A Dclk-cpu.c432 * doesn't affect CPU speed). So CPUCLx_SWITCH divider from CMU_TOP is used
445 /* Divider from CMU_TOP */ in exynos850_alt_parent_set_max_rate()
449 /* Divider's parent from CMU_TOP */ in exynos850_alt_parent_set_max_rate()
H A Dclk-exynos5260.h364 *Registers for CMU_TOP
H A Dclk-exynos990.c26 /* ---- CMU_TOP ------------------------------------------------------------- */
28 /* Register Offset definitions for CMU_TOP (0x1a330000) */
470 /* Parent clock list for CMU_TOP muxes */
1181 /* Register CMU_TOP early, as it's a dependency for other early domains */

12