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/linux/Documentation/devicetree/bindings/cpufreq/
H A Dapple,cluster-cpufreq.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/cpufreq/apple,cluster-cpufreq.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Apple SoC cluster cpufreq device
10 - Hector Martin <marcan@marcan.st>
13 Apple SoCs (e.g. M1) have a per-cpu-cluster DVFS controller that is part of
14 the cluster management register block. This binding uses the standard
15 operating-points-v2 table to define the CPU performance states, with the
16 opp-level property specifying the hardware p-state index for that level.
[all …]
H A Dcpufreq-mediatek.txt1 Binding for MediaTek's CPUFreq driver
5 - clocks: A list of phandle + clock-specifier pairs for the clocks listed in clock names.
6 - clock-names: Should contain the following:
7 "cpu" - The multiplexer for clock input of CPU cluster.
8 "intermediate" - A parent of "cpu" clock which is used as "intermediate" clock
11 Please refer to Documentation/devicetree/bindings/clock/clock-bindings.txt for
13 - operating-points-v2: Please refer to Documentation/devicetree/bindings/opp/opp-v2.yaml
15 - proc-supply: Regulator for Vproc of CPU cluster.
18 - sram-supply: Regulator for Vsram of CPU cluster. When present, the cpufreq driver
23 - mediatek,cci:
[all …]
/linux/arch/arm64/boot/dts/apple/
H A Dt600x-dieX.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
9 DIE_NODE(cpufreq_e): cpufreq@210e20000 {
10 …compatible = "apple,t6000-cluster-cpufreq", "apple,t8103-cluster-cpufreq", "apple,cluster-cpufreq";
12 #performance-domain-cells = <0>;
15 DIE_NODE(cpufreq_p0): cpufreq@211e20000 {
16 …compatible = "apple,t6000-cluster-cpufreq", "apple,t8103-cluster-cpufreq", "apple,cluster-cpufreq";
18 #performance-domain-cells = <0>;
21 DIE_NODE(cpufreq_p1): cpufreq@212e20000 {
22 …compatible = "apple,t6000-cluster-cpufreq", "apple,t8103-cluster-cpufreq", "apple,cluster-cpufreq";
24 #performance-domain-cells = <0>;
[all …]
H A Dt8112.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/interrupt-controller/apple-aic.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/pinctrl/apple.h>
14 #include <dt-bindings/spmi/spmi.h>
17 compatible = "apple,t8112", "apple,arm-platform";
19 #address-cells = <2>;
20 #size-cells = <2>;
23 #address-cells = <2>;
[all …]
H A Dt8103.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/interrupt-controller/apple-aic.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/pinctrl/apple.h>
16 compatible = "apple,t8103", "apple,arm-platform";
18 #address-cells = <2>;
19 #size-cells = <2>;
22 #address-cells = <2>;
23 #size-cells = <0>;
[all …]
/linux/drivers/cpufreq/
H A Dapple-soc-cpufreq.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Apple SoC CPU cluster performance state driver
7 * Based on scpi-cpufreq.c
13 #include <linux/cpufreq.h>
90 .compatible = "apple,t8103-cluster-cpufreq",
94 .compatible = "apple,t8112-cluster-cpufreq",
98 .compatible = "apple,cluster-cpufreq",
107 struct apple_cpu_priv *priv = policy->driver_data; in apple_soc_cpufreq_get_rate()
111 if (priv->info->cur_pstate_mask) { in apple_soc_cpufreq_get_rate()
112 u64 reg = readq_relaxed(priv->reg_base + APPLE_DVFS_STATUS); in apple_soc_cpufreq_get_rate()
[all …]
H A Darmada-8k-cpufreq.c1 // SPDX-License-Identifier: GPL-2.0+
3 * CPUFreq support for Armada 8K
25 { .compatible = "marvell,ap806-cpu-clock" },
26 { .compatible = "marvell,ap807-cpu-clock" },
44 /* If the CPUs share the same clock, then they are in the same cluster. */
84 return -EINVAL; in armada_8k_add_opp()
141 return -ENODEV; in armada_8k_cpufreq_init()
148 return -ENOMEM; in armada_8k_cpufreq_init()
190 armada_8k_pdev = platform_device_register_simple("cpufreq-dt", -1, in armada_8k_cpufreq_init()
216 MODULE_DESCRIPTION("Armada 8K cpufreq driver");
H A Dmediatek-cpufreq.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Author: Pi-Cheng Chen <pi-cheng.chen@linaro.org>
9 #include <linux/cpufreq.h>
30 * on each CPU power/clock domain of Mediatek SoCs. Each CPU cluster in
33 * 100mV < Vsram - Vproc < 200mV
71 if (cpumask_test_cpu(cpu, &info->cpus)) in mtk_cpu_dvfs_info_lookup()
81 const struct mtk_cpufreq_platform_data *soc_data = info->soc_data; in mtk_cpufreq_voltage_tracking()
82 struct regulator *proc_reg = info->proc_reg; in mtk_cpufreq_voltage_tracking()
83 struct regulator *sram_reg = info->sram_reg; in mtk_cpufreq_voltage_tracking()
85 int retry = info->vtrack_max; in mtk_cpufreq_voltage_tracking()
[all …]
/linux/Documentation/driver-api/thermal/
H A Dcpu-cooling-api.rst21 1.1 cpufreq registration/unregistration APIs
22 --------------------------------------------
29 This interface function registers the cpufreq cooling device with the name
30 "thermal-cpufreq-%x". This api can support multiple instances of cpufreq
41 This interface function registers the cpufreq cooling device with
42 the name "thermal-cpufreq-%x" linking it with a device tree node, in
44 instances of cpufreq cooling devices.
47 CPUFreq policy.
54 This interface function unregisters the "thermal-cpufreq-%x" cooling device.
63 supported currently). This power model requires that the operating-points of
[all …]
H A Dcpu-idle-cooling.rst1 .. SPDX-License-Identifier: GPL-2.0
8 ----------
26 budget lower than the requested one and under-utilize the CPU, thus
27 losing performance. In other words, one OPP under-utilizes the CPU
33 ----------
42 the control precision of cpufreq, however different vendors have a
48 belong to the same cluster, with a duration greater than the cluster
58 ---------------
63 cpufreq. Ideally, if all CPUs belonging to the same cluster, inject
64 their idle cycles synchronously, the cluster can reach its power down
[all …]
/linux/Documentation/admin-guide/pm/
H A Dintel_uncore_frequency_scaling.rst1 .. SPDX-License-Identifier: GPL-2.0
8 :Copyright: |copy| 2022-2023 Intel Corporation
13 ------------
22 the scaling min/max frequencies via cpufreq sysfs to improve CPU performance.
26 use both cpufreq and the uncore scaling interface to distribute power and
30 ---------------
45 This is a read-only attribute. If users adjust max_freq_khz,
50 This is a read-only attribute. If users adjust min_freq_khz,
63 -----------------------------------------------------------------
66 of mesh partitions. This partition is called fabric cluster.
[all …]
H A Dcpuidle.rst1 .. SPDX-License-Identifier: GPL-2.0
5 .. |cpufreq| replace:: :doc:`CPU Performance Scaling <cpufreq>` substdef
27 CPU idle time management is an energy-efficiency feature concerned about using
31 ------------
37 software as individual single-core processors. In other words, a CPU is an
46 Second, if the processor is multi-core, each core in it is able to follow at
53 place, but it also may apply to a larger unit (say a "package" or a "cluster")
61 Finally, each core in a multi-core processor may be able to follow more than one
66 multiple individual single-core "processors", referred to as *hardware threads*
67 (or hyper-threads specifically on Intel hardware), that each can follow one
[all …]
/linux/drivers/base/
H A Darch_topology.c1 // SPDX-License-Identifier: GPL-2.0
13 #include <linux/cpufreq.h>
52 * either cpufreq or counter driven. If the support status changes as in update_scale_freq_invariant()
70 * supported by cpufreq. in topology_set_scale_freq_source()
81 if (!sfd || sfd->source != SCALE_FREQ_SOURCE_ARCH) { in topology_set_scale_freq_source()
104 if (sfd && sfd->source == source) { in topology_clear_scale_freq_source()
114 * use-after-free races. in topology_clear_scale_freq_source()
127 sfd->set_freq_scale(); in topology_scale_freq_tick()
144 * want to update the scale factor with information from CPUFREQ. in topology_set_freq_scale()
167 * topology_update_hw_pressure() - Update HW pressure for CPUs
[all …]
/linux/drivers/devfreq/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
15 Like some CPUs with CPUfreq, a device may have multiple clocks.
20 to a device by 1-to-1. The device registering devfreq takes the
38 similar as ONDEMAND governor of CPUFREQ does. A device with
39 Simple-Ondemand should be able to provide busy/total counter
89 PPMU counters of memory controllers by using DEVFREQ-event device
128 which is shared the same regulators with the cpu cluster. It can track
/linux/arch/arm/mach-versatile/
H A Dspc.c1 // SPDX-License-Identifier: GPL-2.0-only
12 #include <linux/clk-provider.h>
28 #define SPCLOG "vexpress-spc: "
39 /* SPC wake-up IRQs status and mask */
46 /* SPC per-CPU mailboxes */
50 /* SPC CPU/cluster reset statue */
68 /* wake-up interrupt masks */
71 /* TC2 static dual-cluster configuration */
75 * Even though the SPC takes max 3-5 ms to complete any OPP/COMMS
97 * A15s cluster identifier
[all …]
/linux/arch/arm64/boot/dts/qcom/
H A Dsm4450.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/clock/qcom,rpmh.h>
7 #include <dt-bindings/clock/qcom,sm4450-camcc.h>
8 #include <dt-bindings/clock/qcom,sm4450-dispcc.h>
9 #include <dt-bindings/clock/qcom,sm4450-gcc.h>
10 #include <dt-bindings/clock/qcom,sm4450-gpucc.h>
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
16 interrupt-parent = <&intc>;
[all …]
H A Dsdx75.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
9 #include <dt-bindings/clock/qcom,rpmh.h>
10 #include <dt-bindings/clock/qcom,sdx75-gcc.h>
11 #include <dt-bindings/dma/qcom-gpi.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/interconnect/qcom,icc.h>
14 #include <dt-bindings/interconnect/qcom,sdx75.h>
15 #include <dt-bindings/interrupt-controller/arm-gic.h>
16 #include <dt-bindings/mailbox/qcom-ipcc.h>
17 #include <dt-bindings/power/qcom,rpmhpd.h>
[all …]
H A Dsm6115.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
6 #include <dt-bindings/clock/qcom,gcc-sm6115.h>
7 #include <dt-bindings/clock/qcom,sm6115-dispcc.h>
8 #include <dt-bindings/clock/qcom,sm6115-gpucc.h>
9 #include <dt-bindings/clock/qcom,rpmcc.h>
10 #include <dt-bindings/dma/qcom-gpi.h>
11 #include <dt-bindings/firmware/qcom,scm.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/interconnect/qcom,rpm-icc.h>
14 #include <dt-bindings/interconnect/qcom,sm6115.h>
[all …]
H A Dqcm2290.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
8 #include <dt-bindings/clock/qcom,dispcc-qcm2290.h>
9 #include <dt-bindings/clock/qcom,gcc-qcm2290.h>
10 #include <dt-bindings/clock/qcom,qcm2290-gpucc.h>
11 #include <dt-bindings/clock/qcom,rpmcc.h>
12 #include <dt-bindings/dma/qcom-gpi.h>
13 #include <dt-bindings/firmware/qcom,scm.h>
14 #include <dt-bindings/gpio/gpio.h>
15 #include <dt-bindings/interrupt-controller/arm-gic.h>
16 #include <dt-bindings/interconnect/qcom,qcm2290.h>
[all …]
/linux/Documentation/devicetree/bindings/cpu/
H A Dcpu-capacity.txt6 1 - Introduction
15 2 - CPU capacity definition
19 heterogeneity. Such heterogeneity can come from micro-architectural differences
23 capture a first-order approximation of the relative performance of CPUs.
29 * A "single-threaded" or CPU affine benchmark
43 3 - capacity-dmips-mhz
46 capacity-dmips-mhz is an optional cpu node [1] property: u32 value
51 capacity-dmips-mhz property is all-or-nothing: if it is specified for a cpu
53 fall back to the default capacity value for every CPU. If cpufreq is not
54 available, final capacities are calculated by directly using capacity-dmips-
[all …]
/linux/drivers/watchdog/
H A Ds3c2410_wdt.c1 // SPDX-License-Identifier: GPL-2.0-or-later
23 #include <linux/cpufreq.h>
84 * DOC: Quirk flags for different Samsung watchdog IP-cores
89 * differences in both watchdog and PMU IP-cores should be accounted for. Quirk
96 * write-only, writing any values to this register clears the interrupt, but
153 * struct s3c2410_wdt_variant - Per-variant config data
337 { .compatible = "google,gs101-wdt",
339 { .compatible = "samsung,s3c2410-wdt",
341 { .compatible = "samsung,s3c6410-wdt",
343 { .compatible = "samsung,exynos5250-wdt",
[all …]
/linux/arch/arm/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
159 The ARM series is a line of low-power-consumption RISC chip designs
161 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
162 manufactured, but legacy ARM-based PC hardware remains popular in
173 supported in LLD until version 14. The combined range is -/+ 256 MiB,
266 Patch phys-to-virt and virt-to-phys translation functions at
270 This can only be used with non-XIP MMU kernels where the base
316 bool "MMU-based Paged Memory Management Support"
319 Select if you want MMU-based virtualised addressing space
354 # This is sorted alphabetically by mach-* pathname. However, plat-*
[all …]
/linux/arch/arm/mach-tegra/
H A Dsleep-tegra30.S1 /* SPDX-License-Identifier: GPL-2.0-only */
11 #include <asm/asm-offsets.h>
81 .arch armv7-a
192 * Puts the current CPU in wait-for-event mode on the flow controller
193 * and powergates it -- flags (in R0) indicate the request type.
196 * corrupts r0-r4, r10-r12
293 * CPU power-gating process, to avoid loading from SDRAM which
294 * are not supported once SDRAM is put into self-refresh.
296 * disabled before putting SDRAM into self-refresh to avoid
356 * self-refresh, PLLC, PLLM and PLLP reenabled, CPU running on PLLX,
[all …]
/linux/arch/arm64/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
275 ARM 64-bit (AArch64) Linux support.
283 # required due to use of the -Zfixed-x18 flag.
286 # -Zsanitizer=shadow-call-stack flag.
296 depends on $(cc-option,-fpatchable-function-entry=2)
322 # VA_BITS - PAGE_SHIFT - 3
400 def_bool !$(as-instr,1:\n.inst 0\n.rept . - 1b\n\nnop\n.endr\n)
405 # https://github.com/llvm/llvm-project/commit/2a96f47c5ffca84cd774ad402cacd137f4bf45e2
455 at stage-2.
463 …bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is acce…
[all …]
/linux/drivers/pmdomain/qcom/
H A Dcpr.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
27 #include <linux/nvmem-consumer.h>
29 /* Register Offsets for RB-CPR and Bit Definitions */
125 #define FUSE_REVISION_UNKNOWN (-1)
254 return !drv->loop_disabled; in cpr_is_allowed()
259 writel_relaxed(value, drv->base + offset); in cpr_write()
264 return readl_relaxed(drv->base + offset); in cpr_read()
272 val = readl_relaxed(drv->base + offset); in cpr_masked_write()
275 writel_relaxed(val, drv->base + offset); in cpr_masked_write()
[all …]

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