Lines Matching +full:cluster +full:- +full:cpufreq
1 # SPDX-License-Identifier: GPL-2.0-only
282 ARM 64-bit (AArch64) Linux support.
290 # required due to use of the -Zfixed-x18 flag.
293 # -Zsanitizer=shadow-call-stack flag.
303 depends on $(cc-option,-fpatchable-function-entry=2)
329 # VA_BITS - PTDESC_TABLE_SHIFT
407 def_bool !$(as-instr,1:\n.inst 0\n.rept . - 1b\n\nnop\n.endr\n)
412 # https://github.com/llvm/llvm-project/commit/2a96f47c5ffca84cd774ad402cacd137f4bf45e2
462 at stage-2.
470 …bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is acce…
475 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
478 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
484 data cache clean-and-invalidate.
492 …bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to th…
497 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
506 data cache clean-and-invalidate.
514 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
519 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
522 If a Cortex-A53 processor is executing a store or prefetch for
524 cluster is executing a cache maintenance operation to the same
529 data cache clean-and-invalidate.
537 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
542 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
546 the same time as a processor in another cluster is executing a cache
551 data cache clean-and-invalidate.
559 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
563 erratum 832075 on Cortex-A57 parts up to r1p2.
565 Affected Cortex-A57 parts might deadlock when exclusive load/store
566 instructions to Write-Back memory are mixed with Device loads.
568 The workaround is to promote device loads to use Load-Acquire
577 …bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a…
581 erratum 834220 on Cortex-A57 parts up to r1p2.
583 Affected Cortex-A57 parts might report a Stage 2 translation
597 …bool "Cortex-A57/A72: 1742098: ELR recorded incorrectly on interrupt taken between cryptographic i…
601 This option removes the AES hwcap for aarch32 user-space to
602 workaround erratum 1742098 on Cortex-A57 and Cortex-A72.
613 bool "Cortex-A53: 845719: a load might read incorrect data"
618 erratum 845719 on Cortex-A53 parts up to r0p4.
620 When running a compat (AArch32) userspace on an affected Cortex-A53
626 return to a 32-bit task.
634 bool "Cortex-A53: 843419: A load or store might access an incorrect address"
637 This option links the kernel with '--fix-cortex-a53-843419' and
640 Cortex-A53 parts up to r0p4.
645 def_bool $(ld-option,--fix-cortex-a53-843419)
648 …bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorre…
651 This option adds a workaround for ARM Cortex-A55 Erratum 1024718.
653 Affected Cortex-A55 cores (all revisions) could cause incorrect
655 without a break-before-make. The workaround is to disable the usage
662 …bool "Cortex-A76/Neoverse-N1: MRC read following MRRC read of specific Generic Timer in AArch32 mi…
666 This option adds a workaround for ARM Cortex-A76/Neoverse-N1
669 Affected Cortex-A76/Neoverse-N1 cores (r0p0 to r3p1) could
679 …bool "Cortex-A76: 1165522: Speculative AT instruction using out-of-context translation regime coul…
683 This option adds a workaround for ARM Cortex-A76 erratum 1165522.
685 Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could end-up with
692 …bool "Cortex-A57/A72: 1319537: Speculative AT instruction using out-of-context translation regime …
696 This option adds work arounds for ARM Cortex-A57 erratum 1319537
699 Cortex-A57 and A72 cores could end-up with corrupted TLBs by
705 …bool "Cortex-A55: 1530923: Speculative AT instruction using out-of-context translation regime coul…
709 This option adds a workaround for ARM Cortex-A55 erratum 1530923.
711 Affected Cortex-A55 cores (r0p0, r0p1, r1p0, r2p0) could end-up with
721 …bool "Cortex-A55: Completion of affected memory accesses might not be guaranteed by completion of …
724 This option adds a workaround for ARM Cortex-A55 erratum #2441007.
726 Under very rare circumstances, affected Cortex-A55 CPUs
727 may not handle a race between a break-before-make sequence on one
737 …bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-a…
740 This option adds a workaround for ARM Cortex-A76 erratum 1286807.
742 On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual
746 break-before-make sequence, then under very rare circumstances
754 bool "Cortex-A76: Software Step might prevent interrupt recognition"
757 This option adds a workaround for Arm Cortex-A76 erratum 1463225.
759 On the affected Cortex-A76 cores (r0p0 to r3p1), software stepping
772 bool "Neoverse-N1: workaround mis-ordering of instruction fetches (rare)"
774 This option adds a workaround for ARM Neoverse-N1 erratum
777 Affected Neoverse-N1 cores could execute a stale instruction when
782 forces user-space to perform cache maintenance.
787 …bool "Cortex-A77: 1508412: workaround deadlock on sequence of NC/Device load and store exclusive o…
790 This option adds a workaround for Arm Cortex-A77 erratum 1508412.
792 Affected Cortex-A77 cores (r0p0, r1p0) could deadlock on a sequence
793 of a store-exclusive or read of PAR_EL1 and a load with device or
794 non-cacheable memory attributes. The workaround depends on a firmware
810 bool "Cortex-A510: 2051678: disable Hardware Update of the page table dirty bit"
813 This options adds the workaround for ARM Cortex-A510 erratum ARM64_ERRATUM_2051678.
814 Affected Cortex-A510 might not respect the ordering rules for
821 bool "Cortex-A510: 2077057: workaround software-step corrupting SPSR_EL2"
824 This option adds the workaround for ARM Cortex-A510 erratum 2077057.
825 Affected Cortex-A510 may corrupt SPSR_EL2 when the a step exception is
833 previous guest entry, and can be restored from the in-memory copy.
838 bool "Cortex-A510: 2658417: remove BF16 support due to incorrect result"
841 This option adds the workaround for ARM Cortex-A510 erratum 2658417.
842 Affected Cortex-A510 (r0p0 to r1p1) may produce the wrong result for
846 user-space should not be using these instructions.
851 bool "Cortex-A710/X2: 2119858: workaround TRBE overwriting trace data in FILL mode"
856 This option adds the workaround for ARM Cortex-A710/X2 erratum 2119858.
858 Affected Cortex-A710/X2 cores could overwrite up to 3 cache lines of trace
869 bool "Neoverse-N2: 2139208: workaround TRBE overwriting trace data in FILL mode"
874 This option adds the workaround for ARM Neoverse-N2 erratum 2139208.
876 Affected Neoverse-N2 cores could overwrite up to 3 cache lines of trace
890 bool "Cortex-A710: 2054223: workaround TSB instruction failing to flush trace"
894 Enable workaround for ARM Cortex-A710 erratum 2054223
905 bool "Neoverse-N2: 2067961: workaround TSB instruction failing to flush trace"
909 Enable workaround for ARM Neoverse-N2 erratum 2067961
923 bool "Neoverse-N2: 2253138: workaround TRBE writing to address out-of-range"
928 This option adds the workaround for ARM Neoverse-N2 erratum 2253138.
930 Affected Neoverse-N2 cores might write to an out-of-range address, not reserved
941 bool "Cortex-A710/X2: 2224489: workaround TRBE writing to address out-of-range"
946 This option adds the workaround for ARM Cortex-A710/X2 erratum 2224489.
948 Affected Cortex-A710/X2 cores might write to an out-of-range address, not reserved
959 …bool "Cortex-A510: Completion of affected memory accesses might not be guaranteed by completion of…
962 This option adds a workaround for ARM Cortex-A510 erratum #2441009.
964 Under very rare circumstances, affected Cortex-A510 CPUs
965 may not handle a race between a break-before-make sequence on one
975 bool "Cortex-A510: 2064142: workaround TRBE register writes while disabled"
979 This option adds the workaround for ARM Cortex-A510 erratum 2064142.
981 Affected Cortex-A510 core might fail to write into system registers after the
993 bool "Cortex-A510: 2038923: workaround TRBE corruption with enable"
997 This option adds the workaround for ARM Cortex-A510 erratum 2038923.
999 Affected Cortex-A510 core might cause an inconsistent view on whether trace is
1016 bool "Cortex-A510: 1902691: workaround TRBE trace corruption"
1020 This option adds the workaround for ARM Cortex-A510 erratum 1902691.
1022 Affected Cortex-A510 core might cause trace data corruption, when being written
1034 bool "Cortex-A510: 2457168: workaround for AMEVCNTR01 incrementing incorrectly"
1038 This option adds the workaround for ARM Cortex-A510 erratum 2457168.
1041 as the system counter. On affected Cortex-A510 cores AMEVCNTR01 increments
1051 bool "Cortex-A715: 2645198: Workaround possible [ESR|FAR]_ELx corruption"
1054 This option adds the workaround for ARM Cortex-A715 erratum 2645198.
1056 If a Cortex-A715 cpu sees a page mapping permissions change from executable
1057 to non-executable, it may corrupt the ESR_ELx and FAR_ELx registers on the
1060 Only user-space does executable to non-executable permission transition via
1061 mprotect() system call. Workaround the problem by doing a break-before-make
1070 bool "Cortex-A520: 2966298: workaround for speculatively executed unprivileged load"
1074 This option adds the workaround for ARM Cortex-A520 erratum 2966298.
1076 On an affected Cortex-A520 core, a speculatively executed unprivileged
1084 bool "Cortex-A510: 3117295: workaround for speculatively executed unprivileged load"
1088 This option adds the workaround for ARM Cortex-A510 erratum 3117295.
1090 On an affected Cortex-A510 core, a speculatively executed unprivileged
1098 bool "Cortex-*/Neoverse-*: workaround for MSR SSBS not self-synchronizing"
1103 * ARM Cortex-A76 erratum 3324349
1104 * ARM Cortex-A77 erratum 3324348
1105 * ARM Cortex-A78 erratum 3324344
1106 * ARM Cortex-A78C erratum 3324346
1107 * ARM Cortex-A78C erratum 3324347
1108 * ARM Cortex-A710 erratam 3324338
1109 * ARM Cortex-A715 errartum 3456084
1110 * ARM Cortex-A720 erratum 3456091
1111 * ARM Cortex-A725 erratum 3456106
1112 * ARM Cortex-X1 erratum 3324344
1113 * ARM Cortex-X1C erratum 3324346
1114 * ARM Cortex-X2 erratum 3324338
1115 * ARM Cortex-X3 erratum 3324335
1116 * ARM Cortex-X4 erratum 3194386
1117 * ARM Cortex-X925 erratum 3324334
1118 * ARM Neoverse-N1 erratum 3324349
1120 * ARM Neoverse-N3 erratum 3456111
1121 * ARM Neoverse-V1 erratum 3324341
1123 * ARM Neoverse-V3 erratum 3312417
1131 SSBS. The presence of the SSBS special-purpose register is hidden
1143 This implements two gicv3-its errata workarounds for ThunderX. Both
1183 contains data for a non-current ASID. The fix is to
1194 interrupts in host. Trapping both GICv3 group-0 and group-1
1217 bool "Fujitsu-A64FX erratum E#010001: Undefined fault may occur wrongly"
1220 This option adds a workaround for Fujitsu-A64FX erratum E#010001.
1221 On some variants of the Fujitsu-A64FX cores ver(1.0, 1.1), memory
1225 case-1 TTBR0_EL1 with TCR_EL1.NFD0 == 1.
1226 case-2 TTBR0_EL2 with TCR_EL2.NFD0 == 1.
1227 case-3 TTBR1_EL1 with TCR_EL1.NFD1 == 1.
1228 case-4 TTBR1_EL2 with TCR_EL2.NFD1 == 1.
1231 The workaround only affects the Fujitsu-A64FX.
1302 If CNP is enabled on Carmel cores, non-sharable TLBIs on a core will not
1321 The Rockchip RK3588 GIC600 SoC integration does not support ACE/ACE-lite.
1328 bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"
1332 MSI doorbell writes with non-zero values for the device ID.
1364 look-up. AArch32 emulation requires applications compiled
1378 bool "36-bit" if EXPERT
1382 bool "39-bit"
1386 bool "42-bit"
1390 bool "47-bit"
1394 bool "48-bit"
1397 bool "52-bit"
1399 Enable 52-bit virtual addressing for userspace when explicitly
1400 requested via a hint to mmap(). The kernel will also use 52-bit
1402 this feature is available, otherwise it reverts to 48-bit).
1404 NOTE: Enabling 52-bit virtual addressing in conjunction with
1407 impact on its susceptibility to brute-force attacks.
1409 If unsure, select 48-bit virtual addressing instead.
1414 bool "Force 52-bit virtual addresses for userspace"
1417 For systems with 52-bit userspace VAs enabled, the kernel will attempt
1418 to maintain compatibility with older software by providing 48-bit VAs
1421 This configuration option disables the 48-bit compatibility logic, and
1422 forces all userspace addresses to be 52-bit on HW that supports it. One
1443 bool "48-bit"
1447 bool "52-bit"
1450 Enable support for a 52-bit physical address space, introduced as
1451 part of the ARMv8.2-LPA extension.
1454 do not support ARMv8.2-LPA, but with some added memory overhead (and
1477 bool "Build big-endian kernel"
1478 # https://github.com/llvm/llvm-project/commit/1379b150991f70a5782e9a143c2ba5308da1161c
1481 Say Y if you plan on running a kernel with a big-endian userspace.
1484 bool "Build little-endian kernel"
1486 Say Y if you plan on running a kernel with a little-endian userspace.
1492 bool "Multi-core scheduler support"
1494 Multi-core scheduler support improves the CPU scheduler's decision
1495 making when dealing with multi-core CPU chips at a cost of slightly
1499 bool "Cluster scheduler support"
1501 Cluster scheduler support improves the CPU scheduler's decision
1503 Cluster usually means a couple of CPUs which are placed closely
1504 by sharing mid-level caches, last-level cache tags or internal
1515 int "Maximum number of CPUs (2-4096)"
1520 bool "Support for hot-pluggable CPUs"
1536 Enable NUMA (Non-Uniform Memory Access) support.
1564 def_bool $(cc-option, -fsanitize=shadow-call-stack -ffixed-x18)
1633 # so the maximum value of MAX_PAGE_ORDER is SECTION_SIZE_BITS - PAGE_SHIFT:
1636 # ----+-------------------+--------------+----------------------+-------------------------+
1664 Speculation attacks against some high-performance processors can
1676 Speculation attacks against some high-performance processors can
1678 When taking an exception from user-space, a sequence of branches
1685 Apply read-only attributes of VM areas to the linear alias of
1686 the backing pages as well. This prevents code or read-only data
1701 user-space memory directly by pointing TTBR0_EL1 to a reserved
1712 Documentation/arch/arm64/tagged-address-abi.rst.
1715 bool "Kernel support for 32-bit EL0"
1721 This option enables support for a 32-bit EL0 running under a 64-bit
1722 kernel at EL1. AArch32-specific components such as system calls,
1730 If you want to execute 32-bit userspace applications, say Y.
1735 bool "Enable kuser helpers page for 32-bit applications"
1738 Warning: disabling this option may break 32-bit user programs.
1762 bool "Enable vDSO for 32-bit applications"
1768 Place in the process address space of 32-bit applications an
1772 You must have a 32-bit build of glibc 2.22 or later for programs
1776 bool "Compile the 32-bit vDSO for Thumb-2 mode" if EXPERT
1780 Compile the compat vDSO with '-mthumb -fomit-frame-pointer' if y,
1781 otherwise with '-marm'.
1784 bool "Fix up misaligned multi-word loads and stores in user space"
1826 The CP15 barrier instructions - CP15ISB, CP15DSB, and
1827 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
1842 The SETEND instruction alters the data-endianness of the
1850 for this feature to be enabled. If a new CPU - which doesn't support mixed
1851 endian - is hotplugged in after this feature has been enabled, there could
1870 Similarly, writes to read-only pages with the DBM bit set will
1871 clear the read-only bit (AP[2]) instead of raising a
1875 to work on pre-ARMv8.1 hardware and the performance impact is
1883 prevents the kernel or hypervisor from accessing user-space (EL0)
1893 def_bool $(as-instr,.arch_extension lse)
1908 Say Y here to make use of these instructions for the in-kernel
1919 def_bool $(cc-option,-Wa$(comma)-march=armv8.2-a)
1922 def_bool $(as-instr,.arch armv8.2-a+sha3)
1981 context-switched along with the process.
2004 If the compiler supports the -mbranch-protection or
2005 -msign-return-address flag (e.g. GCC 7 or later), then this option
2016 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf)
2020 def_bool $(cc-option,-msign-return-address=all)
2023 def_bool $(cc-option,-Wa$(comma)-march=armv8.3-a)
2026 def_bool $(as-instr,.cfi_startproc\n.cfi_negate_ra_state\n.cfi_endproc\n)
2029 def_bool $(as-instr,.arch_extension rcpc)
2059 def_bool $(cc-option,-Wa$(comma)-march=armv8.4-a)
2066 ARMv8.4-TLBI provides TLBI invalidation instruction that apply to a
2077 def_bool $(cc-option,-Wa$(comma)-march=armv8.5-a)
2120 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf+bti)
2136 # ".arch armv8.5-a+memtag" below. However, this was incomplete
2140 def_bool $(as-instr,.arch armv8.5-a+memtag\nstgm xzr$(comma)[x0])
2156 architectural support for run-time, always-on detection of
2158 to eliminate vulnerabilities arising from memory-unsafe
2166 not be allowed a late bring-up.
2172 Documentation/arch/arm64/memory-tagging-extension.rst.
2184 Access Never to be used with Execute-only mappings.
2191 def_bool $(as-instr,.arch_extension mops)
2203 enforcing page-based protections, but without requiring modification
2206 For details, see Documentation/core-api/protection-keys.rst
2277 If you need the kernel to boot on SVE-capable hardware with broken
2296 bool "Support for NMI-like interrupts"
2299 Adds support for mimicking Non-Maskable Interrupts through the use of
2342 random u64 value in /chosen/kaslr-seed at kernel entry.
2369 …def_bool $(cc-option,-mstack-protector-guard=sysreg -mstack-protector-guard-reg=sp_el0 -mstack-pro…
2377 …# needs Clang with https://github.com/llvm/llvm-project/commit/de07cde67b5d205d58690be012106022aea…
2410 Provide a set of default command-line options at build time by
2425 Uses the command-line options passed by the boot loader. If
2435 command-line options your boot loader passes to the kernel.
2457 by UEFI firmware (such as non-volatile variables, realtime
2482 continue to boot on existing non-UEFI platforms.
2507 source "drivers/cpufreq/Kconfig"