| /linux/Documentation/devicetree/bindings/clock/ |
| H A D | qcom,glymur-gcc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,glymur-gcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Global Clock & Reset Controller on Glymur SoC
10 - Taniya Das <taniya.das@oss.qualcomm.com>
13 Qualcomm global clock control module provides the clocks, resets and power
16 See also: include/dt-bindings/clock/qcom,glymur-gcc.h
20 const: qcom,glymur-gcc
24 - description: Board XO source
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| H A D | silabs,si5351.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/silabs,si5351.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Silicon Labs Si5351A/B/C programmable I2C clock generators
10 The Silicon Labs Si5351A/B/C are programmable I2C clock generators with up to
11 8 outputs. Si5351A also has a reduced pin-count package (10-MSOP) where only 3
12 output clocks are accessible. The internal structure of the clock generators
16 https://www.skyworksinc.com/-/media/Skyworks/SL/documents/public/data-sheets/Si5351-B.pdf
19 - Alvin Šipraga <alsi@bang-olufsen.dk>
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| H A D | qcom,ipq9574-nsscc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,ipq9574-nsscc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Networking Sub System Clock & Reset Controller on IPQ9574
10 - Bjorn Andersson <andersson@kernel.org>
11 - Anusha Rao <quic_anusha@quicinc.com>
14 Qualcomm networking sub system clock control module provides the clocks,
18 include/dt-bindings/clock/qcom,ipq9574-nsscc.h
19 include/dt-bindings/reset/qcom,ipq9574-nsscc.h
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| H A D | qcom,qcs8300-gcc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,qcs8300-gcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Technologies, Inc. Global Clock & Reset Controller on QCS8300
10 - Taniya Das <quic_tdas@quicinc.com>
11 - Imran Shaik <quic_imrashai@quicinc.com>
14 Qualcomm Technologies, Inc. Global clock control module provides the clocks, resets and
17 See also: include/dt-bindings/clock/qcom,qcs8300-gcc.h
21 const: qcom,qcs8300-gcc
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| H A D | qcom,ipq5018-gcc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,ipq5018-gcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Global Clock & Reset Controller on IPQ5018
10 - Sricharan Ramabadhran <quic_srichara@quicinc.com>
13 Qualcomm global clock control module provides the clocks, resets and power
17 include/dt-bindings/clock/qcom,ipq5018-gcc.h
18 include/dt-bindings/reset/qcom,ipq5018-gcc.h
22 const: qcom,gcc-ipq5018
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| H A D | qcom,ipq9574-gcc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,ipq9574-gcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Global Clock & Reset Controller on IPQ9574
10 - Bjorn Andersson <andersson@kernel.org>
11 - Anusha Rao <quic_anusha@quicinc.com>
14 Qualcomm global clock control module provides the clocks, resets and power
18 include/dt-bindings/clock/qcom,ipq9574-gcc.h
19 include/dt-bindings/reset/qcom,ipq9574-gcc.h
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| H A D | qcom,videocc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,videocc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Video Clock & Reset Controller
10 - Taniya Das <quic_tdas@quicinc.com>
13 Qualcomm video clock control module provides the clocks, resets and power
17 include/dt-bindings/clock/qcom,sm6350-videocc.h
18 include/dt-bindings/clock/qcom,videocc-sc7180.h
19 include/dt-bindings/clock/qcom,videocc-sc7280.h
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| H A D | qcom,ipq5332-gcc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,ipq5332-gcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Global Clock & Reset Controller on IPQ5332 and IPQ5424
10 - Bjorn Andersson <andersson@kernel.org>
13 Qualcomm global clock control module provides the clocks, resets and power
17 include/dt-bindings/clock/qcom,gcc-ipq5332.h
18 include/dt-bindings/clock/qcom,gcc-ipq5424.h
23 - qcom,ipq5332-gcc
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| H A D | qcom,qca8k-nsscc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,qca8k-nsscc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm NSS Clock & Reset Controller on QCA8386/QCA8084
10 - Bjorn Andersson <andersson@kernel.org>
11 - Luo Jie <quic_luoj@quicinc.com>
14 Qualcomm NSS clock control module provides the clocks and resets
18 include/dt-bindings/clock/qcom,qca8k-nsscc.h
19 include/dt-bindings/reset/qcom,qca8k-nsscc.h
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| /linux/drivers/clk/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
6 The <linux/clk.h> calls support software clock gating and
16 Select this option when the clock API in <linux/clk.h> is implemented
22 bool "Common Clock Framework"
28 The common clock framework is a single definition of struct
30 implementation of the clock API in include/linux/clk.h.
37 tristate "Clock driver for WM831x/2x PMICs"
43 source "drivers/clk/versatile/Kconfig"
54 tristate "Ti LMK04832 JESD204B Compliant Clock Jitter Cleaner"
59 Low-Noise JESD204B Compliant Clock Jitter Cleaner With Dual Loop PLLs
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| /linux/arch/powerpc/include/asm/ |
| H A D | cpm2.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
27 /* Device sub-block and page codes.
72 /* CPM2-specific opcodes (see cpm.h for common opcodes)
109 * oversampled clock.
153 * get some microcode patches :-).
154 * The parameter ram space for the SMCs is fifty-some bytes, and
353 uint sen_tbuf0data0; /* Save area 0 - current frame */
354 uint sen_tbuf0data1; /* Save area 1 - current frame */
365 uint sen_tbuf1data0; /* Save area 0 - current frame */
366 uint sen_tbuf1data1; /* Save area 1 - current frame */
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| /linux/Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe/ |
| H A D | ucc.txt | 4 - device_type : should be "network", "hldc", "uart", "transparent"
6 - compatible : could be "ucc_geth" or "fsl_atm" and so on.
7 - cell-index : the ucc number(1-8), corresponding to UCCx in UM.
8 - reg : Offset and length of the register set for the device
9 - interrupts : <a b> where a is the interrupt number and b is a
14 - pio-handle : The phandle for the Parallel I/O port configuration.
15 - port-number : for UART drivers, the port number to use, between 0 and 3.
18 CPM UART driver, the port-number is required for the QE UART driver.
19 - soft-uart : for UART drivers, if specified this means the QE UART device
20 driver should use "Soft-UART" mode, which is needed on some SOCs that have
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| H A D | usb.txt | 4 - compatible : should be "fsl,<chip>-qe-usb", "fsl,mpc8323-qe-usb".
5 - reg : the first two cells should contain usb registers location and
8 - interrupts : should contain USB interrupt.
9 - fsl,fullspeed-clock : specifies the full speed USB clock source:
10 "none": clock source is disabled
11 "brg1" through "brg16": clock source is BRG1-BRG16, respectively
12 "clk1" through "clk24": clock source is CLK1-CLK24, respectively
13 - fsl,lowspeed-clock : specifies the low speed USB clock source:
14 "none": clock source is disabled
15 "brg1" through "brg16": clock source is BRG1-BRG16, respectively
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| /linux/include/linux/platform_data/ |
| H A D | si5351.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Si5351A/B/C programmable clock generator platform_data.
10 * enum si5351_pll_src - Si5351 pll clock source
12 * @SI5351_PLL_SRC_XTAL: pll source clock is XTAL input
13 * @SI5351_PLL_SRC_CLKIN: pll source clock is CLKIN input (Si5351C only)
22 * enum si5351_multisynth_src - Si5351 multisynth clock source
24 * @SI5351_MULTISYNTH_SRC_VCO0: multisynth source clock is VCO0
25 * @SI5351_MULTISYNTH_SRC_VCO1: multisynth source clock is VCO1/VXCO
34 * enum si5351_clkout_src - Si5351 clock output clock source
36 * @SI5351_CLKOUT_SRC_MSYNTH_N: clkout N source clock is multisynth N
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| /linux/Documentation/timers/ |
| H A D | timekeeping.rst | 2 Clock sources, Clock events, sched_clock() and delay timers
10 If you grep through the kernel source you will find a number of architecture-
11 specific implementations of clock sources, clockevents and several likewise
12 architecture-specific overrides of the sched_clock() function and some
15 To provide timekeeping for your platform, the clock source provides
16 the basic timeline, whereas clock events shoot interrupts on certain points
17 on this timeline, providing facilities such as high-resolution timers.
19 provide an accurate delay source using hardware counters.
22 Clock sources
23 -------------
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| /linux/Documentation/devicetree/bindings/mmc/ |
| H A D | mtk-sd.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mmc/mtk-sd.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chaotian Jing <chaotian.jing@mediatek.com>
11 - Wenbin Mei <wenbin.mei@mediatek.com>
16 - enum:
17 - mediatek,mt2701-mmc
18 - mediatek,mt2712-mmc
19 - mediatek,mt6779-mmc
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| /linux/Documentation/devicetree/bindings/net/can/ |
| H A D | mpc5xxx-mscan.txt | 2 ------------------------
4 (c) 2006-2009 Secret Lab Technologies Ltd
7 fsl,mpc5200-mscan nodes
8 -----------------------
9 In addition to the required compatible-, reg- and interrupt-properties, you can
10 also specify which clock source shall be used for the controller:
12 - fsl,mscan-clock-source : a string describing the clock source. Valid values
13 are: "ip" for ip bus clock
14 "ref" for reference clock (XTAL)
18 fsl,mpc5121-mscan nodes
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| /linux/drivers/soc/fsl/qe/ |
| H A D | ucc.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * QE UCC API Set - UCC specific routines implementations.
33 if (ucc_num > UCC_MAX_NUM - 1) in ucc_set_qe_mux_mii_mng()
34 return -EINVAL; in ucc_set_qe_mux_mii_mng()
37 qe_clrsetbits_be32(&qe_immr->qmx.cmxgcr, QE_CMXGCR_MII_ENET_MNG, in ucc_set_qe_mux_mii_mng()
50 * 'ucc_num' is the UCC number, from 0 - 7.
62 case 0: guemr = &qe_immr->ucc1.slow.guemr; in ucc_set_type()
64 case 1: guemr = &qe_immr->ucc2.slow.guemr; in ucc_set_type()
66 case 2: guemr = &qe_immr->ucc3.slow.guemr; in ucc_set_type()
68 case 3: guemr = &qe_immr->ucc4.slow.guemr; in ucc_set_type()
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| /linux/Documentation/devicetree/bindings/sound/ |
| H A D | mediatek,mt2701-audio.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/mediatek,mt2701-audio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
13 - Eugen Hristev <eugen.hristev@collabora.com>
18 - mediatek,mt2701-audio
19 - mediatek,mt7622-audio
23 - description: AFE interrupt
24 - description: ASYS interrupt
26 interrupt-names:
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| H A D | mediatek,mt8188-afe.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/mediatek,mt8188-afe.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Trevor Wu <trevor.wu@mediatek.com>
14 const: mediatek,mt8188-afe
25 reset-names:
28 memory-region:
31 Shared memory region for AFE memif. A "shared-dma-pool".
32 See dtschema reserved-memory/shared-dma-pool.yaml for details.
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| /linux/drivers/isdn/mISDN/ |
| H A D | clock.c | 1 // SPDX-License-Identifier: GPL-2.0-only
7 * A clock source registers using mISDN_register_clock:
8 * name = text string to name clock source
9 * priority = value to priorize clock sources (0 = default)
10 * ctl = callback function to enable/disable clock source
11 * priv = private pointer of clock source
12 * return = pointer to clock source structure;
17 * A clock source calls mISDN_clock_update with given samples elapsed, if
21 * A clock source unregisters using mISDN_unregister_clock.
23 * To get current clock, call mISDN_clock_get. The signed short value
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| /linux/sound/firewire/fireworks/ |
| H A D | fireworks_command.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * fireworks_command.c - a part of driver for Fireworks based devices
5 * Copyright (c) 2013-2014 Takashi Sakamoto
27 /* for clock source and sampling rate */
29 u32 source; member
90 [EFR_STATUS_BAD_CLOCK] = "bad clock",
274 command_get_clock(struct snd_efw * efw,struct efc_clock * clock) command_get_clock() argument
294 command_set_clock(struct snd_efw * efw,unsigned int source,unsigned int rate) command_set_clock() argument
296 struct efc_clock clock = {0}; command_set_clock() local
343 snd_efw_command_get_clock_source(struct snd_efw * efw,enum snd_efw_clock_source * source) snd_efw_command_get_clock_source() argument
346 struct efc_clock clock = {0}; snd_efw_command_get_clock_source() local
358 struct efc_clock clock = {0}; snd_efw_command_get_sampling_rate() local
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| /linux/drivers/net/can/mscan/ |
| H A D | mpc5xxx_can.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2004-2005 Andrey Volkov <avolkov@varma-el.com>,
7 * Copyright (C) 2008-2009 Wolfgang Grandegger <wg@grandegger.com>
40 { .compatible = "fsl,mpc5200-cdm", },
56 * Either the oscillator clock (SYS_XTAL_IN) or the IP bus clock in mpc52xx_can_get_clock()
57 * (IP_CLK) can be selected as MSCAN clock source. According to in mpc52xx_can_get_clock()
58 * the MPC5200 user's manual, the oscillator clock is the better in mpc52xx_can_get_clock()
68 freq = mpc5xxx_get_bus_frequency(&ofdev->dev); in mpc52xx_can_get_clock()
75 /* Determine SYS_XTAL_IN frequency from the clock domain settings */ in mpc52xx_can_get_clock()
78 dev_err(&ofdev->dev, "can't get clock node!\n"); in mpc52xx_can_get_clock()
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| /linux/drivers/video/fbdev/via/ |
| H A D | via_clock.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
4 * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
8 * clock and PLL management functions
12 #include <linux/via-core.h>
30 return ((pll.divisor - 2) << 16) in k800_encode_pll()
32 | (pll.multiplier - 2); in k800_encode_pll()
215 static inline u8 set_clock_source_common(enum via_clksrc source, bool use_pll) in set_clock_source_common() argument
219 switch (source) { in set_clock_source_common()
246 static void set_primary_clock_source(enum via_clksrc source, bool use_pll) in set_primary_clock_source() argument
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| /linux/include/dt-bindings/clock/ |
| H A D | tegra234-clock.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved. */
9 * @defgroup bpmp_clock_ids Clock ID's
58 /** @brief clock recovered from EAVB input */
73 * @brief controls the EMC clock frequency.
74 * @details Doing a clk_set_rate on this clock will select the
75 * appropriate clock source, program the source rate and execute a
76 * specific sequence to switch to the new clock source for both memory
126 /** @brief clock recovered from I2S1 input */
130 /** @brief clock recovered from I2S2 input */
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