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/linux/arch/arm64/boot/dts/freescale/
H A Dfsl-lx2160a-tqmlx2160a-mblx2160a.dts1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
3 * Copyright (c) 2020-2023 TQ-Systems GmbH <linux@ew.tq-group.com>,
4 * D-82229 Seefeld, Germany.
8 /dts-v1/;
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/leds/common.h>
12 #include <dt-bindings/net/ti-dp83867.h>
14 #include "fsl-lx2160a-tqmlx2160a.dtsi"
18 compatible = "tq,lx2160a-tqmlx2160a-mblx2160a", "tq,lx2160a-tqmlx2160a",
31 stdout-path = &uart0;
[all …]
/linux/drivers/media/i2c/
H A Dtw9910.c1 // SPDX-License-Identifier: GPL-2.0
13 * Copyright 2006-7 Jonathan Corbet <corbet@lwn.net>
18 #include <linux/clk.h>
26 #include <linux/v4l2-mediabus.h>
30 #include <media/v4l2-subdev.h>
41 #define OPFORM 0x03 /* Output Format Control Register */
43 #define OUTCTR1 0x05 /* Output Control I */
64 #define OUTCTR2 0x1B /* Output Control 2 */
136 #define IFSEL_S 0x10 /* 01 : S-video decoding */
146 /* 1 : ITU-R-656 compatible data sequence format */
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H A Dmt9v032.c1 // SPDX-License-Identifier: GPL-2.0-only
12 #include <linux/clk.h>
24 #include <linux/v4l2-mediabus.h>
28 #include <media/v4l2-ctrls.h>
29 #include <media/v4l2-device.h>
30 #include <media/v4l2-fwnode.h>
31 #include <media/v4l2-subdev.h>
204 struct clk *clk; member
229 struct regmap *map = mt9v032->regmap; in mt9v032_update_aec_agc()
230 u16 value = mt9v032->aec_agc; in mt9v032_update_aec_agc()
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H A Dmt9t112.c1 // SPDX-License-Identifier: GPL-2.0
14 * Copyright 2006-7 Jonathan Corbet <corbet@lwn.net>
20 * v4l-utils compliance tools will report errors.
23 #include <linux/clk.h>
30 #include <linux/v4l2-mediabus.h>
34 #include <media/v4l2-common.h>
35 #include <media/v4l2-image-sizes.h>
36 #include <media/v4l2-subdev.h>
95 struct clk *clk; member
158 msg[0].addr = client->addr; in __mt9t112_reg_read()
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H A Dmt9p031.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * Copyright (C) 2011, Javier Martin <javier.martin@vista-silicon.com>
12 #include <linux/clk.h>
26 #include <media/v4l2-async.h>
27 #include <media/v4l2-ctrls.h>
28 #include <media/v4l2-device.h>
29 #include <media/v4l2-fwnode.h>
30 #include <media/v4l2-subdev.h>
32 #include "aptina-pll.h"
126 struct clk *clk; member
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H A Drj54n1cb0c.c1 // SPDX-License-Identifier: GPL-2.0
10 #include <linux/clk.h>
16 #include <linux/v4l2-mediabus.h>
20 #include <media/v4l2-device.h>
21 #include <media/v4l2-ctrls.h>
22 #include <media/v4l2-subdev.h>
154 struct clk *clk; member
162 unsigned short width; /* Output window */
164 unsigned short resize; /* Sensor * 1024 / resize = Output */
416 /* Clock dividers - these are default register values, divider = register + 1 */
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H A Dov6650.c1 // SPDX-License-Identifier: GPL-2.0-only
15 * Copyright 2006-7 Jonathan Corbet <corbet@lwn.net>
25 #include <linux/clk.h>
29 #include <linux/v4l2-mediabus.h>
32 #include <media/v4l2-ctrls.h>
33 #include <media/v4l2-device.h>
36 #define REG_GAIN 0x00 /* range 00 - 3F */
51 /* [5:0]: Internal Clock Pre-Scaler */
165 #define W_QCIF (DEF_HSTOP - DEF_HSTRT)
167 #define H_QCIF (DEF_VSTOP - DEF_VSTRT)
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H A Dov772x.c1 // SPDX-License-Identifier: GPL-2.0
12 * Copyright 2006-7 Jonathan Corbet <corbet@lwn.net>
17 #include <linux/clk.h>
26 #include <linux/v4l2-mediabus.h>
31 #include <media/v4l2-ctrls.h>
32 #include <media/v4l2-device.h>
33 #include <media/v4l2-event.h>
34 #include <media/v4l2-fwnode.h>
35 #include <media/v4l2-image-sizes.h>
36 #include <media/v4l2-subdev.h>
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H A Dmt9m114.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (c) 2020-2023 Laurent Pinchart <laurent.pinchart@ideasonboard.com>
12 #include <linux/clk.h>
26 #include <media/v4l2-async.h>
27 #include <media/v4l2-cci.h>
28 #include <media/v4l2-ctrls.h>
29 #include <media/v4l2-device.h>
30 #include <media/v4l2-fwnode.h>
31 #include <media/v4l2-mediabus.h>
32 #include <media/v4l2-subdev.h>
[all …]
H A Dov5693.c1 // SPDX-License-Identifier: GPL-2.0
5 * Adapted from the atomisp-ov5693 driver, with contributions from:
8 * Jean-Michel Hautbois
16 #include <linux/clk.h>
26 #include <media/v4l2-cci.h>
27 #include <media/v4l2-ctrls.h>
28 #include <media/v4l2-device.h>
29 #include <media/v4l2-fwnode.h>
145 struct clk *xvclk;
363 ret = cci_update_bits(ov5693->regmap, OV5693_FORMAT1_REG, bits, in ov5693_flip_vert_configure()
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H A Dimx274.c1 // SPDX-License-Identifier: GPL-2.0
3 * imx274.c - IMX274 CMOS Image Sensor driver
12 #include <linux/clk.h>
23 #include <linux/v4l2-mediabus.h>
26 #include <media/v4l2-ctrls.h>
27 #include <media/v4l2-device.h>
28 #include <media/v4l2-fwnode.h>
29 #include <media/v4l2-subdev.h>
49 #define IMX274_GAIN_SHIFT_MASK ((1 << IMX274_GAIN_SHIFT) - 1)
59 / (2048 - IMX274_GAIN_REG_MAX))
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/linux/sound/soc/renesas/rcar/
H A Dadg.c1 // SPDX-License-Identifier: GPL-2.0
3 // Helper routines for R-Car sound ADG.
6 #include <linux/clk-provider.h>
33 struct clk *clkin[CLKINMAX];
34 struct clk *clkout[CLKOUTMAX];
35 struct clk *null_clk;
50 (i < adg->clkin_size) && \
51 ((pos) = adg->clkin[i]); \
55 (i < adg->clkout_size) && \
56 ((pos) = adg->clkout[i]); \
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/linux/Documentation/devicetree/bindings/net/
H A Dti,dp83869.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - $ref: ethernet-phy.yaml#
14 - Andrew Davis <afd@ti.com>
17 The DP83869HM device is a robust, fully-featured Gigabit (PHY) transceiver
18 with integrated PMD sublayers that supports 10BASE-Te, 100BASE-TX and
19 1000BASE-T Ethernet protocols. The DP83869 also supports 1000BASE-X and
20 100BASE-FX Fiber protocols.
23 the DP83869HM can run 1000BASE-X-to-1000BASE-T and 100BASE-FX-to-100BASE-TX
[all …]
H A Dti,dp83867.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - $ref: ethernet-controller.yaml#
14 - Andrew Davis <afd@ti.com>
18 transceiver with integrated PMD sublayers to support 10BASE-Te, 100BASE-TX
19 and 1000BASE-T Ethernet protocols.
34 nvmem-cells:
40 nvmem-cell-names:
42 - const: io_impedance_ctrl
[all …]
/linux/sound/soc/meson/
H A Daxg-frddr.c1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
11 #include <linux/clk.h>
17 #include <sound/soc-dai.h>
19 #include "axg-fifo.h"
41 regmap_update_bits(fifo->map, FIFO_CTRL1, in g12a_frddr_dai_prepare()
43 regmap_update_bits(fifo->map, FIFO_CTRL1, in g12a_frddr_dai_prepare()
45 regmap_update_bits(fifo->map, FIFO_CTRL1, in g12a_frddr_dai_prepare()
61 depth = min(period, fifo->depth); in axg_frddr_dai_hw_params()
62 val = (depth / AXG_FIFO_BURST) - 1; in axg_frddr_dai_hw_params()
63 regmap_update_bits(fifo->map, FIFO_CTRL1, CTRL1_FRDDR_DEPTH, in axg_frddr_dai_hw_params()
[all …]
H A Dt9015.c1 // SPDX-License-Identifier: GPL-2.0
6 #include <linux/clk.h>
56 struct snd_soc_component *component = dai->component; in t9015_dai_set_fmt()
69 return -EINVAL; in t9015_dai_set_fmt()
76 return -EINVAL; in t9015_dai_set_fmt()
86 .name = "t9015-hifi",
100 static const DECLARE_TLV_DB_MINMAX_MUTE(dac_vol_tlv, -9525, 0);
137 SND_SOC_DAPM_MUX("Right DAC Sel", SND_SOC_NOPM, 0, 0,
139 SND_SOC_DAPM_MUX("Left DAC Sel", SND_SOC_NOPM, 0, 0,
143 SND_SOC_DAPM_OUT_DRV("Right- Driver", BLOCK_EN, LORN_EN, 0,
[all …]
H A Daxg-spdifout.c1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 #include <linux/clk.h>
11 #include <sound/soc-dai.h>
19 * applied when the related sel bits are cleared
61 struct clk *mclk;
62 struct clk *pclk;
97 axg_spdifout_enable(priv->map); in axg_spdifout_trigger()
103 axg_spdifout_disable(priv->map); in axg_spdifout_trigger()
107 return -EINVAL; in axg_spdifout_trigger()
116 regmap_update_bits(priv->map, SPDIFOUT_CTRL0, SPDIFOUT_CTRL0_VSET, in axg_spdifout_mute()
[all …]
H A Daxg-toddr.c1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
9 #include <linux/clk.h>
15 #include <sound/soc-dai.h>
17 #include "axg-fifo.h"
43 regmap_update_bits(fifo->map, FIFO_CTRL1, in g12a_toddr_dai_prepare()
45 regmap_update_bits(fifo->map, FIFO_CTRL1, in g12a_toddr_dai_prepare()
47 regmap_update_bits(fifo->map, FIFO_CTRL1, in g12a_toddr_dai_prepare()
65 type = 2; /* 4 samples of 16 bits - right justified */ in axg_toddr_dai_hw_params()
68 type = 4; /* 2 samples of 32 bits - right justified */ in axg_toddr_dai_hw_params()
71 return -EINVAL; in axg_toddr_dai_hw_params()
[all …]
/linux/drivers/mmc/host/
H A Dsdhci_am654.c1 // SPDX-License-Identifier: GPL-2.0
3 * sdhci_am654.c - SDHCI driver for TI's AM654 SOCs
5 * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com
8 #include <linux/clk.h>
18 #include "sdhci-cqhci.h"
19 #include "sdhci-pltfm.h"
88 #define SDHCI_AM654_AUTOSUSPEND_DELAY -1
108 [MMC_TIMING_LEGACY] = {"ti,otap-del-sel-legacy",
109 "ti,itap-del-sel-legacy",
111 [MMC_TIMING_MMC_HS] = {"ti,otap-del-sel-mmc-hs",
[all …]
/linux/arch/arm64/boot/dts/mediatek/
H A Dmt7981b.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
3 #include <dt-bindings/clock/mediatek,mt7981-clk.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/reset/mt7986-resets.h>
9 interrupt-parent = <&gic>;
10 #address-cells = <2>;
11 #size-cells = <2>;
14 #address-cells = <1>;
15 #size-cells = <0>;
18 compatible = "arm,cortex-a53";
[all …]
H A Dmt2712e.dtsi5 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 #include <dt-bindings/clock/mt2712-clk.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/memory/mt2712-larb-port.h>
12 #include <dt-bindings/phy/phy.h>
13 #include <dt-bindings/power/mt2712-power.h>
14 #include "mt2712-pinfunc.h"
18 interrupt-parent = <&sysirq>;
19 #address-cells = <2>;
[all …]
/linux/include/linux/mfd/
H A Dstm32-timers.h1 /* SPDX-License-Identifier: GPL-2.0 */
10 #include <linux/clk.h>
12 #include <linux/dma-mapping.h>
26 #define TIM_ARR 0x2c /* Auto-Reload Register */
27 #define TIM_CCRx(x) (0x34 + 4 * ((x) - 1)) /* Capt/Comp Register x (x ∈ {1, .. 4}) */
32 #define TIM_BDTR 0x44 /* Break and Dead-Time Reg */
39 #define TIM_CR1_ARPE BIT(7) /* Auto-reload Preload Ena */
45 #define TIM_DIER_CCxIE(x) BIT(1 + ((x) - 1)) /* CCx Interrupt Enable (x ∈ {1, .. 4}) */
51 #define TIM_DIER_CCxDE(x) BIT(9 + ((x) - 1)) /* CCx DMA request Enable (x ∈ {1, .. 4}) */
63 #define TIM_CCMR_CC1S (BIT(0) | BIT(1)) /* Capture/compare 1 sel */
[all …]
/linux/arch/arm/boot/dts/nxp/ls/
H A Dls1021a-tqmls1021a-mbls1021a.dts1 // SPDX-License-Identifier: (GPL-2.0-or-later OR X11)
3 * Copyright 2013-2014 Freescale Semiconductor, Inc.
4 * Copyright 2018-2023 TQ-Systems GmbH <linux@ew.tq-group.com>,
5 * D-82229 Seefeld, Germany.
9 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/input/linux-event-codes.h>
13 #include <dt-bindings/leds/common.h>
14 #include <dt-bindings/leds/leds-pca9532.h>
15 #include <dt-bindings/net/ti-dp83867.h>
[all …]
/linux/drivers/clk/imx/
H A Dclk-imx6q.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 2011-2013 Freescale Semiconductor, Inc.
10 #include <linux/clk.h>
12 #include <linux/clk-provider.h>
15 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
20 #include <dt-bindings/clock/imx6qdl-clock.h>
22 #include "clk.h"
154 return -ENOENT; in ldb_di_sel_by_clock_id()
165 return -ENOENT; in ldb_di_sel_by_clock_id()
175 int parent, child, sel; in of_assigned_ldb_sels() local
[all …]
/linux/drivers/clk/
H A Dclk-si5341.c1 // SPDX-License-Identifier: GPL-2.0
14 #include <linux/clk.h>
15 #include <linux/clk-provider.h>
59 /* The output stages can be connected to any synth (full mux) */
74 struct clk_si5341_output clk[SI5341_MAX_NUM_OUTPUTS]; member
75 struct clk *input_clk[SI5341_NUM_INPUTS];
127 /* Input dividers (48-bit) */
136 /* Output configuration */
137 #define SI5341_OUT_CONFIG(output) \ argument
138 ((output)->data->reg_output_offset[(output)->index])
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