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/linux/arch/arm64/boot/dts/freescale/
H A Dfsl-lx2160a-tqmlx2160a-mblx2160a.dts1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
3 * Copyright (c) 2020-2023 TQ-Systems GmbH <linux@ew.tq-group.com>,
4 * D-82229 Seefeld, Germany.
8 /dts-v1/;
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/leds/common.h>
12 #include <dt-bindings/net/ti-dp83867.h>
14 #include "fsl-lx2160a-tqmlx2160a.dtsi"
18 compatible = "tq,lx2160a-tqmlx2160a-mblx2160a", "tq,lx2160a-tqmlx2160a",
31 stdout-path = &uart0;
[all …]
H A Dimx8mn-tqma8mqnl-mba8mx.dts1 // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
3 * Copyright 2020-2021 TQ-Systems GmbH
6 /dts-v1/;
8 #include "imx8mn-tqma8mqnl.dtsi"
12 model = "TQ-Systems GmbH i.MX8MN TQMa8MxNL on MBa8Mx";
13 compatible = "tq,imx8mn-tqma8mqnl-mba8mx", "tq,imx8mn-tqma8mqnl", "fsl,imx8mn";
14 chassis-type = "embedded";
25 reg_usdhc2_vmmc: regulator-vmmc {
26 compatible = "regulator-fixed";
27 pinctrl-names = "default";
[all …]
H A Dimx8mp-tqma8mpql-mba8mpxl.dts1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
3 * Copyright 2021-2022 TQ-Systems GmbH
4 * Author: Alexander Stein <alexander.stein@tq-group.com>
7 /dts-v1/;
9 #include <dt-bindings/leds/common.h>
10 #include <dt-bindings/net/ti-dp83867.h>
11 #include <dt-bindings/phy/phy-imx8-pcie.h>
12 #include <dt-bindings/pwm/pwm.h>
13 #include "imx8mp-tqma8mpql.dtsi"
16 model = "TQ-Systems i.MX8MPlus TQMa8MPxL on MBa8MPxL";
[all …]
H A Dimx8mp-libra-rdk-fpsc.dts1 // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
6 /dts-v1/;
8 #include <dt-bindings/leds/leds-pca9532.h>
9 #include <dt-bindings/phy/phy-imx8-pcie.h>
10 #include <dt-bindings/pwm/pwm.h>
11 #include "imx8mp-phycore-fpsc.dtsi"
14 compatible = "phytec,imx8mp-libra-rdk-fpsc",
15 "phytec,imx8mp-phycore-fpsc", "fsl,imx8mp";
19 compatible = "pwm-backlight";
20 pinctrl-0 = <&pinctrl_lvds0>;
[all …]
H A Dimx8mp-phycore-som.dtsi1 // SPDX-License-Identifier: GPL-2.0
7 #include <dt-bindings/net/ti-dp83867.h>
11 model = "PHYTEC phyCORE-i.MX8MP";
12 compatible = "phytec,imx8mp-phycore-som", "fsl,imx8mp";
24 reg_vdd_io: regulator-vdd-io {
25 compatible = "regulator-fixed";
26 regulator-always-on;
27 regulator-boot-on;
28 regulator-max-microvolt = <3300000>;
29 regulator-min-microvolt = <3300000>;
[all …]
H A Dmba8xx.dtsi1 // SPDX-License-Identifier: (GPL-2.0-or-later OR X11)
3 * Copyright 2018-2023 TQ-Systems GmbH <linux@ew.tq-group.com>,
4 * D-82229 Seefeld, Germany.
8 #include <dt-bindings/input/input.h>
9 #include <dt-bindings/leds/common.h>
10 #include <dt-bindings/net/ti-dp83867.h>
14 compatible = "iio-hwmon";
15 io-channels = <&adc0 0>, <&adc0 1>, <&adc0 2>, <&adc0 3>;
23 backlight_lvds: backlight-lvds {
24 compatible = "pwm-backlight";
[all …]
H A Dimx8mp-tqma8mpql-mba8mp-ras314.dts1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
3 * Copyright (c) 2023-2024 TQ-Systems GmbH <linux@ew.tq-group.com>,
4 * D-82229 Seefeld, Germany.
9 /dts-v1/;
11 #include <dt-bindings/leds/common.h>
12 #include <dt-bindings/net/ti-dp83867.h>
13 #include <dt-bindings/phy/phy-imx8-pcie.h>
14 #include <dt-bindings/pwm/pwm.h>
15 #include "imx8mp-tqma8mpql.dtsi"
18 model = "TQ-Systems i.MX8MPlus TQMa8MPxL on MBa8MP-RAS314";
[all …]
/linux/sound/soc/renesas/rcar/
H A Dadg.c1 // SPDX-License-Identifier: GPL-2.0
3 // Helper routines for R-Car sound ADG.
6 #include <linux/clk-provider.h>
34 struct clk *adg;
35 struct clk *clkin[CLKINMAX];
36 struct clk *clkout[CLKOUTMAX];
37 struct clk *null_clk;
52 (i < adg->clkin_size) && \
53 ((pos) = adg->clkin[i]); \
57 (i < adg->clkout_size) && \
[all …]
/linux/drivers/media/i2c/
H A Dtw9910.c1 // SPDX-License-Identifier: GPL-2.0
13 * Copyright 2006-7 Jonathan Corbet <corbet@lwn.net>
18 #include <linux/clk.h>
26 #include <linux/v4l2-mediabus.h>
30 #include <media/v4l2-subdev.h>
41 #define OPFORM 0x03 /* Output Format Control Register */
43 #define OUTCTR1 0x05 /* Output Control I */
64 #define OUTCTR2 0x1B /* Output Control 2 */
136 #define IFSEL_S 0x10 /* 01 : S-video decoding */
146 /* 1 : ITU-R-656 compatible data sequence format */
[all …]
H A Dov772x.c1 // SPDX-License-Identifier: GPL-2.0
12 * Copyright 2006-7 Jonathan Corbet <corbet@lwn.net>
17 #include <linux/clk.h>
26 #include <linux/v4l2-mediabus.h>
31 #include <media/v4l2-ctrls.h>
32 #include <media/v4l2-device.h>
33 #include <media/v4l2-event.h>
34 #include <media/v4l2-fwnode.h>
35 #include <media/v4l2-image-sizes.h>
36 #include <media/v4l2-subdev.h>
[all …]
H A Dov2640.c1 // SPDX-License-Identifier: GPL-2.0-only
9 * Copyright 2005-2009 Freescale Semiconductor, Inc. All Rights Reserved.
16 #include <linux/clk.h>
20 #include <linux/v4l2-mediabus.h>
23 #include <media/v4l2-device.h>
24 #include <media/v4l2-event.h>
25 #include <media/v4l2-subdev.h>
26 #include <media/v4l2-ctrls.h>
27 #include <media/v4l2-image-sizes.h>
109 #define R_DVP_SP 0xD3 /* DVP output speed control */
[all …]
H A Dtvp7002_reg.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /* Texas Instruments Triple 8-/10-BIT 165-/110-MSPS Video and Graphics
6 * Author: Santiago Nunez-Corrales <santiago.nunez@ridgerun.com>
15 * ------------------
20 * SEL: Select
22 * OUT: Output
35 * CLK: Clocks
/linux/Documentation/devicetree/bindings/net/
H A Dti,dp83869.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - $ref: ethernet-phy.yaml#
14 - Andrew Davis <afd@ti.com>
17 The DP83869HM device is a robust, fully-featured Gigabit (PHY) transceiver
18 with integrated PMD sublayers that supports 10BASE-Te, 100BASE-TX and
19 1000BASE-T Ethernet protocols. The DP83869 also supports 1000BASE-X and
20 100BASE-FX Fiber protocols.
23 the DP83869HM can run 1000BASE-X-to-1000BASE-T and 100BASE-FX-to-100BASE-TX
[all …]
H A Dti,dp83867.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - $ref: ethernet-controller.yaml#
14 - Andrew Davis <afd@ti.com>
18 transceiver with integrated PMD sublayers to support 10BASE-Te, 100BASE-TX
19 and 1000BASE-T Ethernet protocols.
34 nvmem-cells:
40 nvmem-cell-names:
42 - const: io_impedance_ctrl
[all …]
/linux/sound/soc/meson/
H A Daxg-frddr.c1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
11 #include <linux/clk.h>
17 #include <sound/soc-dai.h>
19 #include "axg-fifo.h"
41 regmap_update_bits(fifo->map, FIFO_CTRL1, in g12a_frddr_dai_prepare()
43 regmap_update_bits(fifo->map, FIFO_CTRL1, in g12a_frddr_dai_prepare()
45 regmap_update_bits(fifo->map, FIFO_CTRL1, in g12a_frddr_dai_prepare()
61 depth = min(period, fifo->depth); in axg_frddr_dai_hw_params()
62 val = (depth / AXG_FIFO_BURST) - 1; in axg_frddr_dai_hw_params()
63 regmap_update_bits(fifo->map, FIFO_CTRL1, CTRL1_FRDDR_DEPTH, in axg_frddr_dai_hw_params()
[all …]
H A Daxg-spdifout.c1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 #include <linux/clk.h>
11 #include <sound/soc-dai.h>
19 * applied when the related sel bits are cleared
61 struct clk *mclk;
62 struct clk *pclk;
97 axg_spdifout_enable(priv->map); in axg_spdifout_trigger()
103 axg_spdifout_disable(priv->map); in axg_spdifout_trigger()
107 return -EINVAL; in axg_spdifout_trigger()
116 regmap_update_bits(priv->map, SPDIFOUT_CTRL0, SPDIFOUT_CTRL0_VSET, in axg_spdifout_mute()
[all …]
H A Daxg-toddr.c1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
9 #include <linux/clk.h>
15 #include <sound/soc-dai.h>
17 #include "axg-fifo.h"
43 regmap_update_bits(fifo->map, FIFO_CTRL1, in g12a_toddr_dai_prepare()
45 regmap_update_bits(fifo->map, FIFO_CTRL1, in g12a_toddr_dai_prepare()
47 regmap_update_bits(fifo->map, FIFO_CTRL1, in g12a_toddr_dai_prepare()
65 type = 2; /* 4 samples of 16 bits - right justified */ in axg_toddr_dai_hw_params()
68 type = 4; /* 2 samples of 32 bits - right justified */ in axg_toddr_dai_hw_params()
71 return -EINVAL; in axg_toddr_dai_hw_params()
[all …]
/linux/arch/arm/boot/dts/nxp/ls/
H A Dls1021a-tqmls1021a-mbls1021a.dts1 // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
3 * Copyright 2013-2014 Freescale Semiconductor, Inc.
4 * Copyright 2018-2023 TQ-Systems GmbH <linux@ew.tq-group.com>,
5 * D-82229 Seefeld, Germany.
9 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/input/linux-event-codes.h>
13 #include <dt-bindings/leds/common.h>
14 #include <dt-bindings/leds/leds-pca9532.h>
15 #include <dt-bindings/net/ti-dp83867.h>
[all …]
/linux/drivers/clk/imx/
H A Dclk-imx6q.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 2011-2013 Freescale Semiconductor, Inc.
10 #include <linux/clk.h>
12 #include <linux/clk-provider.h>
15 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
20 #include <dt-bindings/clock/imx6qdl-clock.h>
22 #include "clk.h"
154 return -ENOENT; in ldb_di_sel_by_clock_id()
165 return -ENOENT; in ldb_di_sel_by_clock_id()
175 int parent, child, sel; in of_assigned_ldb_sels() local
[all …]
/linux/arch/arm64/boot/dts/mediatek/
H A Dmt2712e.dtsi5 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 #include <dt-bindings/clock/mt2712-clk.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/memory/mt2712-larb-port.h>
12 #include <dt-bindings/phy/phy.h>
13 #include <dt-bindings/power/mt2712-power.h>
14 #include "mt2712-pinfunc.h"
18 interrupt-parent = <&sysirq>;
19 #address-cells = <2>;
[all …]
H A Dmt8192.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 /dts-v1/;
8 #include <dt-bindings/clock/mt8192-clk.h>
9 #include <dt-bindings/gce/mt8192-gce.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/memory/mt8192-larb-port.h>
13 #include <dt-bindings/pinctrl/mt8192-pinfunc.h>
14 #include <dt-bindings/phy/phy.h>
15 #include <dt-bindings/power/mt8192-power.h>
[all …]
/linux/drivers/clk/
H A Dclk-si5341.c1 // SPDX-License-Identifier: GPL-2.0
14 #include <linux/clk.h>
15 #include <linux/clk-provider.h>
59 /* The output stages can be connected to any synth (full mux) */
74 struct clk_si5341_output clk[SI5341_MAX_NUM_OUTPUTS]; member
75 struct clk *input_clk[SI5341_NUM_INPUTS];
127 /* Input dividers (48-bit) */
136 /* Output configuration */
137 #define SI5341_OUT_CONFIG(output) \ argument
138 ((output)->data->reg_output_offset[(output)->index])
[all …]
/linux/drivers/regulator/
H A Dstm32-vrefbuf.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/clk.h>
32 struct clk *clk; member
47 ret = pm_runtime_resume_and_get(priv->dev); in stm32_vrefbuf_enable()
51 val = readl_relaxed(priv->base + STM32_VREFBUF_CSR); in stm32_vrefbuf_enable()
53 writel_relaxed(val, priv->base + STM32_VREFBUF_CSR); in stm32_vrefbuf_enable()
57 * VRR to be set. That means output has reached expected value. in stm32_vrefbuf_enable()
61 ret = readl_poll_timeout(priv->base + STM32_VREFBUF_CSR, val, in stm32_vrefbuf_enable()
64 dev_err(&rdev->dev, "stm32 vrefbuf timed out!\n"); in stm32_vrefbuf_enable()
65 val = readl_relaxed(priv->base + STM32_VREFBUF_CSR); in stm32_vrefbuf_enable()
[all …]
/linux/arch/arm/boot/dts/mediatek/
H A Dmt2701.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/clock/mt2701-clk.h>
9 #include <dt-bindings/phy/phy.h>
10 #include <dt-bindings/power/mt2701-power.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/memory/mt2701-larb-port.h>
14 #include <dt-bindings/reset/mt2701-resets.h>
15 #include "mt2701-pinfunc.h"
18 #address-cells = <2>;
[all …]
/linux/arch/arm/boot/dts/st/
H A Dstm32mp157c-phycore-stm32mp15-som.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright (C) 2022-2023 Steffen Trumtrar <kernel@pengutronix.de>
4 * Copyright (C) Phytec GmbH 2019-2020 - All Rights Reserved
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/leds/common.h>
13 #include <dt-bindings/leds/leds-pca9532.h>
14 #include <dt-bindings/mfd/st,stpmic1.h>
[all …]

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