| /linux/drivers/mmc/host/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
30 This selects the ARM(R) AMBA(R) PrimeCell Multimedia Card
41 This selects the Qualcomm Data Mover lite/local on SD Card controller.
52 This selects the STMicroelectronics STM32 SDMMC host controller.
61 This selects the Intel(R) PXA(R) Multimedia card Interface.
71 This selects the generic Secure Digital Host Controller Interface.
94 implements a hardware byte swapper using a 32-bit datum.
106 support UHS2-capable devices.
118 This selects the PCI Secure Digital Host Controller Interface.
133 disabled, it will steal the MMC cards away - rendering them
[all …]
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| /linux/drivers/ufs/host/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0+
5 # Copyright (C) 2011-2013 Samsung India Software Operations
15 This selects the PCI UFS Host Controller Interface. Select this if
23 tristate "DesignWare pci support using a G210 Test Chip"
26 Synopsys Test Chip is a PHY for prototyping purposes.
34 This selects the UFS host controller support. Select this if
45 This selects the Cadence-specific additions to UFSHCD platform driver.
50 tristate "DesignWare platform support using a G210 Test Chip"
53 Synopsys Test Chip is a PHY for prototyping purposes.
64 This selects the QCOM specific additions to UFSHCD platform driver.
[all …]
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| /linux/Documentation/devicetree/bindings/bus/ |
| H A D | qcom,ebi2.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 external memory (such as NAND or other memory-mapped peripherals) whereas
17 NOR flash memories), WE (write enable). This on top of 6 different chip selects
25 Also CS1 and CS2 has -A and -B signals. Why they have that is unclear to me.
27 The chip selects have the following memory range assignments. This region of
28 memory is referred to as "Chip Peripheral SS FPB0" and is 168MB big.
30 Chip Select Physical address base
31 CS0 GPIO134 0x1a800000-0x1b000000 (8MB)
[all …]
|
| H A D | socionext,uniphier-system-bus.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/bus/socionext,uniphier-system-bus.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 The UniPhier System Bus is an external bus that connects on-board devices to
11 the UniPhier SoC. It is a simple (semi-)parallel bus with address, data, and
12 some control signals. It supports up to 8 banks (chip selects).
16 within each bank to the CPU-viewed address. The needed setup includes the
21 - Masahiro Yamada <yamada.masahiro@socionext.com>
25 const: socionext,uniphier-system-bus
[all …]
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| /linux/Documentation/devicetree/bindings/spi/ |
| H A D | renesas,sh-msiof.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/spi/renesas,sh-msiof.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Geert Uytterhoeven <geert+renesas@glider.be>
13 - $ref: spi-controller.yaml#
18 - items:
19 - const: renesas,msiof-sh73a0 # SH-Mobile AG5
20 - const: renesas,sh-mobile-msiof # generic SH-Mobile compatible
22 - items:
[all …]
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| H A D | nuvoton,npcm-fiu.txt | 6 FIU0 and FIUx supports two chip selects,
7 FIU3 support four chip select.
10 FIU0 and FIUx supports two chip selects,
11 FIU1 and FIU3 supports four chip selects.
14 - compatible : "nuvoton,npcm750-fiu" for Poleg NPCM7XX BMC
15 "nuvoton,npcm845-fiu" for Arbel NPCM8XX BMC
16 - #address-cells : should be 1.
17 - #size-cells : should be 0.
18 - reg : the first contains the register location and length,
20 - reg-names: Should contain the reg names "control" and "memory"
[all …]
|
| H A D | renesas,rspi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Geert Uytterhoeven <geert+renesas@glider.be>
15 - items:
16 - enum:
17 - renesas,rspi-sh7757 # SH7757
18 - const: renesas,rspi # Legacy SH
20 - items:
21 - enum:
[all …]
|
| H A D | spi-davinci.txt | 4 Keystone 2 - https://www.ti.com/lit/ug/sprugp2a/sprugp2a.pdf
5 dm644x - https://www.ti.com/lit/ug/sprue32a/sprue32a.pdf
6 OMAP-L138/da830 - http://www.ti.com/lit/ug/spruh77a/spruh77a.pdf
9 - #address-cells: number of cells required to define a chip select
11 - #size-cells: should be zero.
12 - compatible:
13 - "ti,dm6441-spi" for SPI used similar to that on DM644x SoC family
14 - "ti,da830-spi" for SPI used similar to that on DA8xx SoC family
15 - "ti,keystone-spi" for SPI used similar to that on Keystone2 SoC
17 - reg: Offset and length of SPI controller register space
[all …]
|
| H A D | spi-cadence.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/spi-cadence.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Michal Simek <michal.simek@amd.com>
13 - $ref: spi-controller.yaml#
18 - cdns,spi-r1p6
19 - xlnx,zynq-spi-r1p6
27 clock-names:
29 - const: ref_clk
[all …]
|
| /linux/Documentation/userspace-api/media/v4l/ |
| H A D | vidioc-dbg-g-chip-info.rst | 1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
13 VIDIOC_DBG_G_CHIP_INFO - Identify the chips on a TV card
41 applications must not use it. When you found a chip specific bug, please
42 contact the linux-media mailing list
53 the driver stores information about the selected chip in the ``name``
57 selects the nth bridge 'chip' on the TV card. You can enumerate all
60 zero always selects the bridge chip itself, e. g. the chip connected to
61 the PCI or USB bus. Non-zero numbers identify specific parts of the
62 bridge chip such as an AC97 register block.
65 selects the nth sub-device. This allows you to enumerate over all
[all …]
|
| H A D | vidioc-dbg-g-register.rst | 1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
13 VIDIOC_DBG_G_REGISTER - VIDIOC_DBG_S_REGISTER - Read or write hardware registers
55 ``match.type`` and ``match.addr`` or ``match.name`` fields select a chip
66 selects the nth non-sub-device chip on the TV card. The number zero
67 always selects the host chip, e. g. the chip connected to the PCI or USB
72 selects the nth sub-device.
83 We recommended the v4l2-dbg utility over calling these ioctls directly.
84 It is available from the LinuxTV v4l-dvb repository; see
92 .. flat-table:: struct v4l2_dbg_match
93 :header-rows: 0
[all …]
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| /linux/arch/m68k/include/asm/ |
| H A D | mcfqspi.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
12 * struct mcfqspi_cs_control - chip select control for the coldfire qspi driver
18 * The QSPI module has 4 hardware chip selects. We don't use them. Instead
31 * struct mcfqspi_platform_data - platform data for the coldfire qspi driver
33 * @num_chipselects: number of chip selects supported by this qspi driver.
34 * @cs_control: platform dependent chip select control.
|
| /linux/drivers/gpu/drm/rockchip/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
31 This selects support for the VOP driver. You should enable it
37 This selects support for the VOP2 driver. The VOP2 hardware is
46 This selects support for Rockchip SoC specific extensions
56 This selects support for Rockchip SoC specific extensions
64 This selects support for Rockchip SoC specific extensions
73 This selects support for Rockchip SoC specific extensions
81 This selects support for Rockchip SoC specific extensions
90 This selects support for Rockchip SoC specific extensions
101 This selects support for Rockchip SoC specific extensions
[all …]
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| /linux/drivers/spi/ |
| H A D | spi-mux.c | 1 // SPDX-License-Identifier: GPL-2.0
12 #define SPI_MUX_NO_CS ((unsigned int)-1)
18 * more chip selects than the hardware peripherals support, or than are
22 * mux will be handled as 'chip selects' on this controller.
26 * struct spi_mux_priv - the basic spi_mux structure
29 * @current_cs: The current chip select set in the mux
35 * @mux: mux_control structure used to provide chip selects for
51 struct spi_mux_priv *priv = spi_controller_get_devdata(spi->controller); in spi_mux_select()
54 ret = mux_control_select(priv->mux, spi_get_chipselect(spi, 0)); in spi_mux_select()
58 if (priv->current_cs == spi_get_chipselect(spi, 0)) in spi_mux_select()
[all …]
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| /linux/Documentation/devicetree/bindings/hwmon/ |
| H A D | adi,ltc4282.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Nuno Sa <nuno.sa@analog.com>
15 https://www.analog.com/media/en/technical-documentation/data-sheets/ltc4282.pdf
20 - adi,ltc4282
25 vdd-supply: true
30 '#clock-cells':
33 adi,rsense-nano-ohms:
36 adi,vin-mode-microvolt:
[all …]
|
| /linux/arch/alpha/include/asm/ |
| H A D | core_irongate.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
9 * IRONGATE is the internal name for the AMD-751 K7 core logic chipset
10 * which provides memory controller and PCI access for NAUTILUS-based
21 * The 21264 supports, and internally recognizes, a 44-bit physical
30 * through the routines given is 32-bit.
38 igcsr32 dev_vendor; /* 0x00 - device ID, vendor ID */
39 igcsr32 stat_cmd; /* 0x04 - status, command */
40 igcsr32 class; /* 0x08 - class code, rev ID */
41 igcsr32 latency; /* 0x0C - header type, PCI latency */
42 igcsr32 bar0; /* 0x10 - BAR0 - AGP */
[all …]
|
| /linux/arch/powerpc/platforms/85xx/ |
| H A D | p1023_rdb.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 2010-2011, 2013 Freescale Semiconductor, Inc.
5 * Author: Roy Zang <tie-fei.zang@freescale.com>
23 #include <asm/pci-bridge.h>
64 * The i2c controller selects initially ID EEPROM in the u-boot; in p1023_rdb_setup_arch()
65 * but if menu configuration selects RTC support in the kernel, in p1023_rdb_setup_arch()
66 * the i2c controller switches to select RTC chip in the kernel. in p1023_rdb_setup_arch()
69 /* Enable RTC chip on the segment #2 of i2c */ in p1023_rdb_setup_arch()
|
| /linux/arch/arm/mach-sa1100/include/mach/ |
| H A D | h3xxx.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
14 /* Physical memory regions corresponding to chip selects */
19 /* Virtual memory regions corresponding to chip selects 2 & 4 (used on sleeves) */
39 /* machine-specific gpios */
74 #define H3600_EGPIO_IR_FSEL (H3XXX_EGPIO_BASE + 13) /* IR speed select: 1->fast, 0->slow */
76 #define H3600_EGPIO_LVDD_ON (H3XXX_EGPIO_BASE + 15) /* enable 9V and -6.5V to LCD. */
|
| /linux/sound/usb/ |
| H A D | mixer_s1810c.c | 1 // SPDX-License-Identifier: GPL-2.0
17 #include <linux/usb/audio-v2.h>
38 * It seems like a selects between
42 * * b selects an input channel (see below).
43 * * c selects an output channel pair (see below).
44 * * d selects left (0) or right (1) of that pair.
45 * * e 0-> disconnect, 0x01000000-> connect,
46 * 0x0109-> used for stereo-linking channels,
54 * 0 - 7 Mic/Inst/Line (Analog inputs)
55 * 8 - 9 S/PDIF
[all …]
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| /linux/drivers/irqchip/ |
| H A D | irq-ftintc010.c | 1 // SPDX-License-Identifier: GPL-2.0
6 * Based on arch/arm/mach-gemini/irq.c
7 * Copyright (C) 2001-2006 Storlink, Corp.
8 * Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@gmail.com>
29 /* Selects level- or edge-triggered */
31 /* Selects active low/high or falling/rising edge */
42 * struct ft010_irq_data - irq data container for the Faraday IRQ controller
44 * @chip: chip container for this instance
49 struct irq_chip chip; member
58 mask = readl(FT010_IRQ_MASK(f->base)); in ft010_irq_mask()
[all …]
|
| /linux/Documentation/driver-api/ |
| H A D | edac.rst | 5 ----------------------------------------
8 *sockets, *socket sets*, *banks*, *rows*, *chip-select rows*, *channels*,
43 It is typically the highest hierarchy on a Fully-Buffered DIMM memory
52 * Single-channel
55 only. E. g. if the data is 64 bits-wide, the data flows to the CPU using
57 memories. FB-DIMM and RAMBUS use a different concept for channel, so
60 * Double-channel
63 dimms, accessed at the same time. E. g. if the DIMM is 64 bits-wide (72
67 * Chip-select row
70 accessed. Common chip-select rows for single channel are 64 bits, for
[all …]
|
| /linux/Documentation/devicetree/bindings/mfd/ |
| H A D | tps6105x.txt | 3 The TP61050/TPS61052 is a high-power "white LED driver". The
7 - compatible: "ti,tps61050" or "ti,tps61052"
8 - reg: Specifies the I2C slave address
10 Optional sub-node:
12 This subnode selects the chip's operational mode.
15 - regulator: presence of this sub-node puts the chip in regulator mode.
18 - led: presence of this sub-node puts the chip in led mode.
20 - function : see ../leds/common.txt
21 - color : see ../leds/common.txt
22 - label : see ../leds/common.txt
[all …]
|
| /linux/drivers/gpio/ |
| H A D | gpiolib-swnode.c | 1 // SPDX-License-Identifier: GPL-2.0+
23 #include "gpiolib-swnode.h"
25 #define GPIOLIB_SWNODE_UNDEFINED_NAME "swnode-gpio-undefined"
33 if (!gdev_node || !gdev_node->name) in swnode_get_gpio_device()
34 return ERR_PTR(-EINVAL); in swnode_get_gpio_device()
38 * primarily used as a key for internal chip selects in SPI bindings. in swnode_get_gpio_device()
41 !strcmp(gdev_node->name, GPIOLIB_SWNODE_UNDEFINED_NAME)) in swnode_get_gpio_device()
42 return ERR_PTR(-ENOENT); in swnode_get_gpio_device()
44 gdev = gpio_device_find_by_label(gdev_node->name); in swnode_get_gpio_device()
45 return gdev ?: ERR_PTR(-EPROBE_DEFER); in swnode_get_gpio_device()
[all …]
|
| /linux/drivers/memory/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
29 This selects the ARM PrimeCell PL172 MultiPort Memory Controller.
42 Used to configure the EBI (external bus interface) when the device-
68 bool "Baikal-T1 CM2 L2-RAM Cache Control Block"
72 Baikal-T1 CPU is based on the MIPS P5600 Warrior IP-core. The CPU
73 resides Coherency Manager v2 with embedded 1MB L2-cache. It's
75 tags and way-select latencies of RAM access. This driver provides a
76 dt properties-based and sysfs interface for it.
85 is intended to provide a glue-less interface to a variety of
88 time via four chip selects with 64M byte access per chip select.
[all …]
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| /linux/Documentation/misc-devices/ |
| H A D | apds990x.rst | 1 .. SPDX-License-Identifier: GPL-2.0
17 -----------
35 selects suitable gain step. After each measurement, reliability of the results
44 Driver controls chip operational state using pm_runtime framework.
45 Voltage regulators are controlled based on chip operational state.
48 -----
52 RO - shows detected chip type and version
55 RW - enable / disable chip. Uses counting logic
57 1 enables the chip
58 0 disables the chip
[all …]
|