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/linux/drivers/gpu/drm/i915/display/
H A Dintel_cdclk.c58 * DOC: CDCLK / RAWCLK
63 * are the core display clock (CDCLK) and RAWCLK.
65 * CDCLK clocks most of the display pipe logic, and thus its frequency
70 * On several platforms the CDCLK frequency can be changed dynamically
72 * Typically changes to the CDCLK frequency require all the display pipes
75 * On SKL+ the DMC will toggle the CDCLK off/on during DC5/6 entry/exit.
76 * DMC will not change the active CDCLK frequency however, so that part
79 * There are multiple components involved in the generation of the CDCLK
82 * - We have the CDCLK PLL, which generates an output clock based on a
91 * As such, the resulting CDCLK frequency can be calculated with the
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H A Dintel_vdsc.c1113 * cannot be higher than the VDSC clock (cdclk) in intel_vdsc_min_cdclk()
1115 * VDSC clock(cdclk) * 2 and so on. in intel_vdsc_min_cdclk()
1124 * compressed_bpp <= PPC * CDCLK * Big joiner Interface bits / Pixel clock in intel_vdsc_min_cdclk()
1126 * We have already computed compressed_bpp, so now compute the min CDCLK that in intel_vdsc_min_cdclk()
1129 * => CDCLK >= compressed_bpp * Pixel clock / (PPC * Bigjoiner Interface bits) in intel_vdsc_min_cdclk()
1132 * => CDCLK >= compressed_bpp * Pixel clock / 2 * Bigjoiner Interface bits in intel_vdsc_min_cdclk()
H A Dintel_dsi.c68 int max_dotclk = display->cdclk.max_dotclk_freq; in intel_dsi_mode_valid()
H A Dintel_dvo.c228 int max_dotclk = display->cdclk.max_dotclk_freq; in intel_dvo_mode_valid()
H A Dintel_pmdemand.c373 * Active_PLLs starts with 1 because of CDCLK PLL. in intel_pmdemand_atomic_check()
H A Dintel_tv.c964 int max_dotclk = display->cdclk.max_dotclk_freq; in intel_tv_mode_valid()
1300 * oversample clock on gen3, cdclk on gen4). Once the pipe in intel_tv_compute_config()
1329 * num = cdclk * (tv_mode->oversample >> !tv_mode->progressive); in intel_tv_compute_config()
H A Dintel_fbc.c1731 if (_intel_fbc_min_cdclk(crtc_state) > display->cdclk.max_cdclk_freq) { in intel_fbc_check_plane()
1754 * Do not ask for more than the max CDCLK frequency, in intel_fbc_min_cdclk()
1757 if (min_cdclk > display->cdclk.max_cdclk_freq) in intel_fbc_min_cdclk()
H A Dintel_plane.c1747 * the planes' minimum cdclk calculation. Add such planes in intel_plane_atomic_check()
1748 * to the state before we compute the minimum cdclk. in intel_plane_atomic_check()
H A Dskl_watermark.c1218 * but rather ratio between pixel_rate and cdclk with additional in icl_compute_dbuf_slices()
3035 dbuf_state->mdclk_cdclk_ratio = intel_mdclk_cdclk_ratio(display, &display->cdclk.hw); in skl_wm_get_hw_state()
3530 /* cdclk/mdclk will be changed later by intel_set_cdclk_post_plane_update() */ in intel_dbuf_mdclk_min_tracker_update()
3533 /* cdclk/mdclk already changed by intel_set_cdclk_pre_plane_update() */ in intel_dbuf_mdclk_min_tracker_update()
H A Dintel_display.c2383 int clock_limit = display->cdclk.max_dotclk_freq; in intel_crtc_compute_pipe_mode()
2399 clock_limit = display->cdclk.max_cdclk_freq * 9 / 10; in intel_crtc_compute_pipe_mode()
2407 clock_limit = display->cdclk.max_dotclk_freq; in intel_crtc_compute_pipe_mode()
7483 * plls, cdclk frequency, QGV point selection parameter etc. Voltage in intel_atomic_commit_tail()
7484 * index, cdclk/ddiclk frequencies are supposed to be configured before in intel_atomic_commit_tail()
7485 * the cdclk config is set. in intel_atomic_commit_tail()
8005 int max_dotclock = display->cdclk.max_dotclk_freq; in max_dotclock()
H A Dintel_lvds.c400 int max_pixclk = display->cdclk.max_dotclk_freq; in intel_lvds_mode_valid()
H A Dintel_crt.c357 int max_dotclk = display->cdclk.max_dotclk_freq; in intel_crt_mode_valid()
H A Dintel_dp.c912 max_bpp = display->cdclk.max_cdclk_freq * ppc * bigjoiner_interface_bits(display) / in bigjoiner_bw_max_bpp()
1011 * slice and VDSC engine, whenever we approach close enough to max CDCLK in intel_dp_dsc_get_slice_count()
1013 if (mode_clock >= ((display->cdclk.max_cdclk_freq * 85) / 100)) in intel_dp_dsc_get_slice_count()
1354 return clock > num_joined_pipes * display->cdclk.max_dotclk_freq || in intel_dp_needs_joiner()
1409 int max_dotclk = display->cdclk.max_dotclk_freq; in intel_dp_mode_valid()
H A Dintel_dsb.c667 * (and the speed also depends on CDCLK and memory clock)...
H A Dintel_hdcp.c361 * cdclk. Without active crtc we won't land here. So we are assuming that in hdcp_key_loadable()
362 * cdclk is already on. in hdcp_key_loadable()
H A Dintel_display_power_well.c1040 intel_cdclk_clock_changed(&display->cdclk.hw, in gen9_disable_dc_states()
H A Dintel_dp_mst.c1423 int max_dotclk = display->cdclk.max_dotclk_freq; in mst_connector_mode_valid_ctx()
/linux/drivers/clk/samsung/
H A Dclk-s5pv210-audss.c75 struct clk *hclk, *pll_ref, *pll_in, *cdclk, *sclk_audio; in s5pv210_audss_clk_probe() local
110 cdclk = devm_clk_get(&pdev->dev, "iiscdclk0"); in s5pv210_audss_clk_probe()
124 if (!IS_ERR(cdclk)) in s5pv210_audss_clk_probe()
125 mout_i2s_p[1] = __clk_get_name(cdclk); in s5pv210_audss_clk_probe()
/linux/Documentation/devicetree/bindings/clock/
H A Dsamsung,exynos-audss-clock.yaml52 - const: cdclk
79 clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in", "cdclk";
/linux/sound/hda/core/
H A Di915.c26 * are used to convert CDClk (Core Display Clock) to 24MHz BCLK:
27 * BCLK = CDCLK * M / N
54 default: /* default CDCLK 450MHz */ in snd_hdac_i915_set_bclk()
/linux/include/dt-bindings/sound/
H A Dsamsung-i2s.h5 #define CLK_I2S_CDCLK 0 /* the CDCLK (CODECLKO) gate clock */
/linux/arch/arm/boot/dts/samsung/
H A Ds3c64xx-pinctrl.dtsi334 i2s0_cdclk: i2s0-cdclk-pins {
346 i2s1_cdclk: i2s1-cdclk-pins {
360 i2s2_cdclk: i2s2-cdclk-pins {
/linux/Documentation/devicetree/bindings/sound/
H A Dsamsung-i2s.yaml115 description: Names of the CDCLK I2S output clocks.
/linux/sound/soc/samsung/
H A Di2s.c1090 /* Gate CDCLK by default */ in samsung_i2s_dai_probe()
1277 const char * const i2s_clk_desc[] = { "cdclk", "rclk_src", "prescaler" }; in i2s_register_clock_provider()
/linux/sound/hda/codecs/hdmi/
H A Dintelhdmi.c635 * to the audio vs. CDCLK workaround. in probe_i915_glk_hdmi()

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