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/linux/drivers/gpu/drm/i915/display/
H A Dintel_cdclk.c53 * DOC: CDCLK / RAWCLK
58 * are the core display clock (CDCLK) and RAWCLK.
60 * CDCLK clocks most of the display pipe logic, and thus its frequency
65 * On several platforms the CDCLK frequency can be changed dynamically
67 * Typically changes to the CDCLK frequency require all the display pipes
70 * On SKL+ the DMC will toggle the CDCLK off/on during DC5/6 entry/exit.
71 * DMC will not change the active CDCLK frequency however, so that part
74 * There are multiple components involved in the generation of the CDCLK
77 * - We have the CDCLK PLL, which generates an output clock based on a
86 * As such, the resulting CDCLK frequency can be calculated with the
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H A Dintel_audio.c441 unsigned int fec_coeff, cdclk, vdsc_bppx16; in calc_hblank_early_prog() local
449 cdclk = i915->display.cdclk.hw.cdclk; in calc_hblank_early_prog()
456 "h_active = %u link_clk = %u : lanes = %u vdsc_bpp = " FXP_Q4_FMT " cdclk = %u\n", in calc_hblank_early_prog()
457 h_active, link_clk, lanes, FXP_Q4_ARGS(vdsc_bppx16), cdclk); in calc_hblank_early_prog()
459 if (WARN_ON(!link_clk || !pixel_clk || !lanes || !vdsc_bppx16 || !cdclk)) in calc_hblank_early_prog()
468 hblank_delta = DIV64_U64_ROUND_UP(mul_u32_u32(5 * (link_clk + cdclk), pixel_clk), in calc_hblank_early_prog()
469 mul_u32_u32(link_clk, cdclk)); in calc_hblank_early_prog()
906 static void get_aud_ts_cdclk_m_n(int refclk, int cdclk, struct aud_ts_cdclk_m_n *aud_ts) in get_aud_ts_cdclk_m_n() argument
909 aud_ts->n = cdclk * aud_ts->m / 24000; in get_aud_ts_cdclk_m_n()
917 get_aud_ts_cdclk_m_n(i915->display.cdclk.hw.ref, i915->display.cdclk.hw.cdclk, &aud_ts); in intel_audio_cdclk_change_post()
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H A Dhsw_ips.c211 * the increased cdclk requirement into account when in hsw_crtc_state_ips_capable()
212 * calculating the new cdclk. in hsw_crtc_state_ips_capable()
214 * Should measure whether using a lower cdclk w/o IPS in hsw_crtc_state_ips_capable()
217 crtc_state->pixel_rate > display->cdclk.max_cdclk_freq * 95 / 100) in hsw_crtc_state_ips_capable()
233 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ in hsw_ips_min_cdclk()
269 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ in hsw_ips_compute_config()
270 if (crtc_state->pixel_rate > cdclk_state->logical.cdclk * 95 / 100) in hsw_ips_compute_config()
H A Dintel_display_core.h121 * dpll and cdclk state is protected by connection_mutex dpll.lock serializes
295 /* Display CDCLK functions */
296 const struct intel_cdclk_funcs *cdclk; member
344 /* The current hardware cdclk configuration */
347 /* cdclk, divider, and ratio table from bspec */
355 } cdclk; member
H A Dintel_atomic_plane.c274 * No need to check against the cdclk state if in intel_plane_calc_min_cdclk()
275 * the min cdclk for the plane doesn't increase. in intel_plane_calc_min_cdclk()
277 * Ie. we only ever increase the cdclk due to plane in intel_plane_calc_min_cdclk()
279 * display blinking due to constant cdclk changes. in intel_plane_calc_min_cdclk()
290 * No need to recalculate the cdclk state if in intel_plane_calc_min_cdclk()
291 * the min cdclk for the pipe doesn't increase. in intel_plane_calc_min_cdclk()
293 * Ie. we only ever increase the cdclk due to plane in intel_plane_calc_min_cdclk()
295 * display blinking due to constant cdclk changes. in intel_plane_calc_min_cdclk()
302 "[PLANE:%d:%s] min cdclk (%d kHz) > [CRTC:%d:%s] min cdclk (%d kHz)\n", in intel_plane_calc_min_cdclk()
H A Dintel_bw.c1305 * No need to check against the cdclk state if in intel_bw_calc_min_cdclk()
1306 * the min cdclk doesn't increase. in intel_bw_calc_min_cdclk()
1308 * Ie. we only ever increase the cdclk due to bandwidth in intel_bw_calc_min_cdclk()
1310 * display blinking due to constant cdclk changes. in intel_bw_calc_min_cdclk()
1320 * No need to recalculate the cdclk state if in intel_bw_calc_min_cdclk()
1321 * the min cdclk doesn't increase. in intel_bw_calc_min_cdclk()
1323 * Ie. we only ever increase the cdclk due to bandwidth in intel_bw_calc_min_cdclk()
1325 * display blinking due to constant cdclk changes. in intel_bw_calc_min_cdclk()
1331 "new bandwidth min cdclk (%d kHz) > old min cdclk (%d kHz)\n", in intel_bw_calc_min_cdclk()
H A Dintel_display_driver.c91 cdclk_state = to_intel_cdclk_state(display->cdclk.obj.state); in intel_display_driver_init_hw()
94 intel_cdclk_dump_config(display, &display->cdclk.hw, "Current CDCLK"); in intel_display_driver_init_hw()
95 cdclk_state->logical = cdclk_state->actual = display->cdclk.hw; in intel_display_driver_init_hw()
458 if (display->cdclk.max_cdclk_freq == 0) in intel_display_driver_probe_nogem()
H A Dintel_pmdemand.c325 (new_cdclk_state->actual.cdclk != in intel_pmdemand_needs_update()
326 old_cdclk_state->actual.cdclk || in intel_pmdemand_needs_update()
386 DIV_ROUND_UP(new_cdclk_state->actual.cdclk, 1000); in intel_pmdemand_atomic_check()
393 * Active_PLLs starts with 1 because of CDCLK PLL. in intel_pmdemand_atomic_check()
H A Dintel_dp_aux.c100 * The clock divider is based off the cdclk or PCH rawclk, and would in ilk_get_aux_clock_divider()
101 * like to run at 2MHz. So, take the cdclk or PCH rawclk value and in ilk_get_aux_clock_divider()
105 freq = display->cdclk.hw.cdclk; in ilk_get_aux_clock_divider()
133 * derive the clock from CDCLK automatically). We still implement the in skl_get_aux_clock_divider()
H A Dintel_vdsc.c1033 * cannot be higher than the VDSC clock (cdclk) in intel_vdsc_min_cdclk()
1035 * VDSC clock(cdclk) * 2 and so on. in intel_vdsc_min_cdclk()
1044 * compressed_bpp <= PPC * CDCLK * Big joiner Interface bits / Pixel clock in intel_vdsc_min_cdclk()
1046 * We have already computed compressed_bpp, so now compute the min CDCLK that in intel_vdsc_min_cdclk()
1049 * => CDCLK >= compressed_bpp * Pixel clock / (PPC * Bigjoiner Interface bits) in intel_vdsc_min_cdclk()
1052 * => CDCLK >= compressed_bpp * Pixel clock / 2 * Bigjoiner Interface bits in intel_vdsc_min_cdclk()
H A Dintel_backlight.c1098 clock = KHz(i915->display.cdclk.hw.cdclk); in i9xx_hz_to_pwm()
1116 clock = KHz(i915->display.cdclk.hw.cdclk); in i965_hz_to_pwm()
H A Dintel_modeset_setup.c161 to_intel_cdclk_state(i915->display.cdclk.obj.state); in intel_crtc_disable_noatomic_complete()
707 to_intel_cdclk_state(i915->display.cdclk.obj.state); in intel_modeset_readout_hw_state()
H A Dintel_display_power.c1178 drm_err(display->drm, "CDCLK source is not LCPLL\n"); in hsw_assert_cdclk()
1360 intel_cdclk_dump_config(display, &display->cdclk.hw, "Current CDCLK"); in hsw_restore_lcpll()
1681 /* 4. Enable CDCLK. */ in icl_display_core_init()
H A Di9xx_plane.c382 * of cdclk when the sprite plane is enabled on the in i9xx_plane_ratio()
384 * never allowed to exceed 80% of cdclk. Let's just go in i9xx_plane_ratio()
H A Dintel_dvo.c227 int max_dotclk = to_i915(connector->base.dev)->display.cdclk.max_dotclk_freq; in intel_dvo_mode_valid()
H A Dintel_dpll_mgr.c1480 /* DPLL0 is always enabled since it drives CDCLK */ in skl_ddi_dpll0_get_hw_state()
1981 i915->display.dpll.ref_clks.nssc = i915->display.cdclk.hw.ref; in skl_update_dpll_ref_clks()
3968 * DVFS pre sequence would be here, but in our driver the cdclk code in combo_pll_enable()
3991 * DVFS pre sequence would be here, but in our driver the cdclk code in tbt_pll_enable()
4016 * DVFS pre sequence would be here, but in our driver the cdclk code in mg_pll_enable()
4033 * DVFS pre sequence would be here, but in our driver the cdclk code in icl_pll_disable()
4082 i915->display.dpll.ref_clks.nssc = i915->display.cdclk.hw.ref; in icl_update_dpll_ref_clks()
H A Dintel_tv.c965 int max_dotclk = display->cdclk.max_dotclk_freq; in intel_tv_mode_valid()
1301 * oversample clock on gen3, cdclk on gen4). Once the pipe in intel_tv_compute_config()
1330 * num = cdclk * (tv_mode->oversample >> !tv_mode->progressive); in intel_tv_compute_config()
H A Dintel_display.c2572 int clock_limit = i915->display.cdclk.max_dotclk_freq; in intel_crtc_compute_pipe_mode()
2588 clock_limit = i915->display.cdclk.max_cdclk_freq * 9 / 10; in intel_crtc_compute_pipe_mode()
2596 clock_limit = i915->display.cdclk.max_dotclk_freq; in intel_crtc_compute_pipe_mode()
4499 cdclk_state->logical.cdclk); in hsw_ips_linetime_wm()
6181 * the planes' minimum cdclk calculation. Add such planes in intel_atomic_check_planes()
6182 * to the state before we compute the minimum cdclk. in intel_atomic_check_planes()
7788 * plls, cdclk frequency, QGV point selection parameter etc. Voltage in intel_atomic_commit_tail()
7789 * index, cdclk/ddiclk frequencies are supposed to be configured before in intel_atomic_commit_tail()
7790 * the cdclk config is set. in intel_atomic_commit_tail()
8320 int max_dotclock = display->cdclk.max_dotclk_freq; in max_dotclock()
/linux/drivers/clk/samsung/
H A Dclk-exynos-audss.c128 struct clk *pll_ref, *pll_in, *cdclk, *sclk_audio, *sclk_pcm_in; in exynos_audss_clk_probe() local
188 cdclk = devm_clk_get(dev, "cdclk"); in exynos_audss_clk_probe()
190 if (!IS_ERR(cdclk)) in exynos_audss_clk_probe()
191 mout_i2s_p[1] = __clk_get_name(cdclk); in exynos_audss_clk_probe()
H A Dclk-s5pv210-audss.c70 struct clk *hclk, *pll_ref, *pll_in, *cdclk, *sclk_audio; in s5pv210_audss_clk_probe() local
105 cdclk = devm_clk_get(&pdev->dev, "iiscdclk0"); in s5pv210_audss_clk_probe()
119 if (!IS_ERR(cdclk)) in s5pv210_audss_clk_probe()
120 mout_i2s_p[1] = __clk_get_name(cdclk); in s5pv210_audss_clk_probe()
/linux/Documentation/devicetree/bindings/clock/
H A Dsamsung,exynos-audss-clock.yaml52 - const: cdclk
79 clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in", "cdclk";
/linux/sound/hda/
H A Dhdac_i915.c26 * are used to convert CDClk (Core Display Clock) to 24MHz BCLK:
27 * BCLK = CDCLK * M / N
54 default: /* default CDCLK 450MHz */ in snd_hdac_i915_set_bclk()
/linux/include/dt-bindings/sound/
H A Dsamsung-i2s.h5 #define CLK_I2S_CDCLK 0 /* the CDCLK (CODECLKO) gate clock */
/linux/arch/arm/boot/dts/samsung/
H A Ds3c64xx-pinctrl.dtsi334 i2s0_cdclk: i2s0-cdclk-pins {
346 i2s1_cdclk: i2s1-cdclk-pins {
360 i2s2_cdclk: i2s2-cdclk-pins {
/linux/Documentation/devicetree/bindings/sound/
H A Dsamsung-i2s.yaml115 description: Names of the CDCLK I2S output clocks.

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