Lines Matching full:cdclk
53 * DOC: CDCLK / RAWCLK
58 * are the core display clock (CDCLK) and RAWCLK.
60 * CDCLK clocks most of the display pipe logic, and thus its frequency
65 * On several platforms the CDCLK frequency can be changed dynamically
67 * Typically changes to the CDCLK frequency require all the display pipes
70 * On SKL+ the DMC will toggle the CDCLK off/on during DC5/6 entry/exit.
71 * DMC will not change the active CDCLK frequency however, so that part
74 * There are multiple components involved in the generation of the CDCLK
77 * - We have the CDCLK PLL, which generates an output clock based on a
86 * As such, the resulting CDCLK frequency can be calculated with the
89 * cdclk = vco / cd2x_div / (sq_len / sq_div) / 2
100 * Several methods exist to change the CDCLK frequency, which ones are
123 u8 (*calc_voltage_level)(int cdclk);
129 display->funcs.cdclk->get_cdclk(display, cdclk_config); in intel_cdclk_get_cdclk()
136 display->funcs.cdclk->set_cdclk(display, cdclk_config, pipe); in intel_cdclk_set_cdclk()
143 return display->funcs.cdclk->modeset_calc_cdclk(state); in intel_cdclk_modeset_calc_cdclk()
147 int cdclk) in intel_cdclk_calc_voltage_level() argument
149 return display->funcs.cdclk->calc_voltage_level(cdclk); in intel_cdclk_calc_voltage_level()
155 cdclk_config->cdclk = 133333; in fixed_133mhz_get_cdclk()
161 cdclk_config->cdclk = 200000; in fixed_200mhz_get_cdclk()
167 cdclk_config->cdclk = 266667; in fixed_266mhz_get_cdclk()
173 cdclk_config->cdclk = 333333; in fixed_333mhz_get_cdclk()
179 cdclk_config->cdclk = 400000; in fixed_400mhz_get_cdclk()
185 cdclk_config->cdclk = 450000; in fixed_450mhz_get_cdclk()
200 cdclk_config->cdclk = 133333; in i85x_get_cdclk()
214 cdclk_config->cdclk = 200000; in i85x_get_cdclk()
217 cdclk_config->cdclk = 250000; in i85x_get_cdclk()
220 cdclk_config->cdclk = 133333; in i85x_get_cdclk()
225 cdclk_config->cdclk = 266667; in i85x_get_cdclk()
239 cdclk_config->cdclk = 133333; in i915gm_get_cdclk()
245 cdclk_config->cdclk = 333333; in i915gm_get_cdclk()
249 cdclk_config->cdclk = 190000; in i915gm_get_cdclk()
263 cdclk_config->cdclk = 133333; in i945gm_get_cdclk()
269 cdclk_config->cdclk = 320000; in i945gm_get_cdclk()
273 cdclk_config->cdclk = 200000; in i945gm_get_cdclk()
387 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco, in g33_get_cdclk()
393 "Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", in g33_get_cdclk()
395 cdclk_config->cdclk = 190476; in g33_get_cdclk()
408 cdclk_config->cdclk = 266667; in pnv_get_cdclk()
411 cdclk_config->cdclk = 333333; in pnv_get_cdclk()
414 cdclk_config->cdclk = 444444; in pnv_get_cdclk()
417 cdclk_config->cdclk = 200000; in pnv_get_cdclk()
424 cdclk_config->cdclk = 133333; in pnv_get_cdclk()
427 cdclk_config->cdclk = 166667; in pnv_get_cdclk()
466 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco, in i965gm_get_cdclk()
472 "Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", in i965gm_get_cdclk()
474 cdclk_config->cdclk = 200000; in i965gm_get_cdclk()
494 cdclk_config->cdclk = cdclk_sel ? 333333 : 222222; in gm45_get_cdclk()
497 cdclk_config->cdclk = cdclk_sel ? 320000 : 228571; in gm45_get_cdclk()
501 "Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", in gm45_get_cdclk()
503 cdclk_config->cdclk = 222222; in gm45_get_cdclk()
516 cdclk_config->cdclk = 800000; in hsw_get_cdclk()
518 cdclk_config->cdclk = 450000; in hsw_get_cdclk()
520 cdclk_config->cdclk = 450000; in hsw_get_cdclk()
522 cdclk_config->cdclk = 337500; in hsw_get_cdclk()
524 cdclk_config->cdclk = 540000; in hsw_get_cdclk()
548 static u8 vlv_calc_voltage_level(struct intel_display *display, int cdclk) in vlv_calc_voltage_level() argument
553 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */ in vlv_calc_voltage_level()
555 else if (cdclk >= 266667) in vlv_calc_voltage_level()
565 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; in vlv_calc_voltage_level()
579 cdclk_config->cdclk = vlv_get_cck_clock(dev_priv, "cdclk", in vlv_get_cdclk()
606 if (display->cdclk.hw.cdclk >= dev_priv->czclk_freq) { in vlv_program_pfi_credits()
639 int cdclk = cdclk_config->cdclk; in vlv_set_cdclk() local
643 switch (cdclk) { in vlv_set_cdclk()
651 MISSING_CASE(cdclk); in vlv_set_cdclk()
656 * off and a CDCLK frequency other than the minimum, like when in vlv_set_cdclk()
676 "timed out waiting for CDclk change\n"); in vlv_set_cdclk()
679 if (cdclk == 400000) { in vlv_set_cdclk()
683 cdclk) - 1; in vlv_set_cdclk()
685 /* adjust cdclk divider */ in vlv_set_cdclk()
695 "timed out waiting for CDclk change\n"); in vlv_set_cdclk()
706 if (cdclk == 400000) in vlv_set_cdclk()
729 int cdclk = cdclk_config->cdclk; in chv_set_cdclk() local
733 switch (cdclk) { in chv_set_cdclk()
740 MISSING_CASE(cdclk); in chv_set_cdclk()
745 * off and a CDCLK frequency other than the minimum, like when in chv_set_cdclk()
761 "timed out waiting for CDclk change\n"); in chv_set_cdclk()
785 static u8 bdw_calc_voltage_level(int cdclk) in bdw_calc_voltage_level() argument
787 switch (cdclk) { in bdw_calc_voltage_level()
807 cdclk_config->cdclk = 800000; in bdw_get_cdclk()
809 cdclk_config->cdclk = 450000; in bdw_get_cdclk()
811 cdclk_config->cdclk = 450000; in bdw_get_cdclk()
813 cdclk_config->cdclk = 540000; in bdw_get_cdclk()
815 cdclk_config->cdclk = 337500; in bdw_get_cdclk()
817 cdclk_config->cdclk = 675000; in bdw_get_cdclk()
821 * at least what the CDCLK frequency requires. in bdw_get_cdclk()
824 bdw_calc_voltage_level(cdclk_config->cdclk); in bdw_get_cdclk()
827 static u32 bdw_cdclk_freq_sel(int cdclk) in bdw_cdclk_freq_sel() argument
829 switch (cdclk) { in bdw_cdclk_freq_sel()
831 MISSING_CASE(cdclk); in bdw_cdclk_freq_sel()
849 int cdclk = cdclk_config->cdclk; in bdw_set_cdclk() local
858 "trying to change cdclk frequency with cdclk not enabled\n")) in bdw_set_cdclk()
864 "failed to inform pcode about cdclk change\n"); in bdw_set_cdclk()
880 LCPLL_CLK_FREQ_MASK, bdw_cdclk_freq_sel(cdclk)); in bdw_set_cdclk()
893 DIV_ROUND_CLOSEST(cdclk, 1000) - 1); in bdw_set_cdclk()
921 static u8 skl_calc_voltage_level(int cdclk) in skl_calc_voltage_level() argument
923 if (cdclk > 540000) in skl_calc_voltage_level()
925 else if (cdclk > 450000) in skl_calc_voltage_level()
927 else if (cdclk > 337500) in skl_calc_voltage_level()
981 cdclk_config->cdclk = cdclk_config->bypass = cdclk_config->ref; in skl_get_cdclk()
991 cdclk_config->cdclk = 432000; in skl_get_cdclk()
994 cdclk_config->cdclk = 308571; in skl_get_cdclk()
997 cdclk_config->cdclk = 540000; in skl_get_cdclk()
1000 cdclk_config->cdclk = 617143; in skl_get_cdclk()
1009 cdclk_config->cdclk = 450000; in skl_get_cdclk()
1012 cdclk_config->cdclk = 337500; in skl_get_cdclk()
1015 cdclk_config->cdclk = 540000; in skl_get_cdclk()
1018 cdclk_config->cdclk = 675000; in skl_get_cdclk()
1029 * at least what the CDCLK frequency requires. in skl_get_cdclk()
1032 skl_calc_voltage_level(cdclk_config->cdclk); in skl_get_cdclk()
1036 static int skl_cdclk_decimal(int cdclk) in skl_cdclk_decimal() argument
1038 return DIV_ROUND_CLOSEST(cdclk - 1000, 500); in skl_cdclk_decimal()
1043 bool changed = display->cdclk.skl_preferred_vco_freq != vco; in skl_set_preferred_cdclk_vco()
1045 display->cdclk.skl_preferred_vco_freq = vco; in skl_set_preferred_cdclk_vco()
1086 display->cdclk.hw.vco = vco; in skl_dpll0_enable()
1100 display->cdclk.hw.vco = 0; in skl_dpll0_disable()
1104 int cdclk, int vco) in skl_cdclk_freq_sel() argument
1106 switch (cdclk) { in skl_cdclk_freq_sel()
1109 cdclk != display->cdclk.hw.bypass); in skl_cdclk_freq_sel()
1131 int cdclk = cdclk_config->cdclk; in skl_set_cdclk() local
1137 * Based on WA#1183 CDCLK rates 308 and 617MHz CDCLK rates are in skl_set_cdclk()
1142 * minimum 308MHz CDCLK. in skl_set_cdclk()
1153 "Failed to inform PCU about cdclk change (%d)\n", ret); in skl_set_cdclk()
1157 freq_select = skl_cdclk_freq_sel(display, cdclk, vco); in skl_set_cdclk()
1159 if (display->cdclk.hw.vco != 0 && in skl_set_cdclk()
1160 display->cdclk.hw.vco != vco) in skl_set_cdclk()
1165 if (display->cdclk.hw.vco != vco) { in skl_set_cdclk()
1168 cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk); in skl_set_cdclk()
1177 if (display->cdclk.hw.vco != vco) in skl_set_cdclk()
1184 cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk); in skl_set_cdclk()
1212 intel_cdclk_dump_config(display, &display->cdclk.hw, "Current CDCLK"); in skl_sanitize_cdclk()
1215 if (display->cdclk.hw.vco == 0 || in skl_sanitize_cdclk()
1216 display->cdclk.hw.cdclk == display->cdclk.hw.bypass) in skl_sanitize_cdclk()
1227 skl_cdclk_decimal(display->cdclk.hw.cdclk); in skl_sanitize_cdclk()
1233 drm_dbg_kms(display->drm, "Sanitizing cdclk programmed by pre-os\n"); in skl_sanitize_cdclk()
1235 /* force cdclk programming */ in skl_sanitize_cdclk()
1236 display->cdclk.hw.cdclk = 0; in skl_sanitize_cdclk()
1238 display->cdclk.hw.vco = ~0; in skl_sanitize_cdclk()
1247 if (display->cdclk.hw.cdclk != 0 && in skl_cdclk_init_hw()
1248 display->cdclk.hw.vco != 0) { in skl_cdclk_init_hw()
1253 if (display->cdclk.skl_preferred_vco_freq == 0) in skl_cdclk_init_hw()
1255 display->cdclk.hw.vco); in skl_cdclk_init_hw()
1259 cdclk_config = display->cdclk.hw; in skl_cdclk_init_hw()
1261 cdclk_config.vco = display->cdclk.skl_preferred_vco_freq; in skl_cdclk_init_hw()
1264 cdclk_config.cdclk = skl_calc_cdclk(0, cdclk_config.vco); in skl_cdclk_init_hw()
1265 cdclk_config.voltage_level = skl_calc_voltage_level(cdclk_config.cdclk); in skl_cdclk_init_hw()
1272 struct intel_cdclk_config cdclk_config = display->cdclk.hw; in skl_cdclk_uninit_hw()
1274 cdclk_config.cdclk = cdclk_config.bypass; in skl_cdclk_uninit_hw()
1276 cdclk_config.voltage_level = skl_calc_voltage_level(cdclk_config.cdclk); in skl_cdclk_uninit_hw()
1282 u32 cdclk; member
1289 { .refclk = 19200, .cdclk = 144000, .ratio = 60 },
1290 { .refclk = 19200, .cdclk = 288000, .ratio = 60 },
1291 { .refclk = 19200, .cdclk = 384000, .ratio = 60 },
1292 { .refclk = 19200, .cdclk = 576000, .ratio = 60 },
1293 { .refclk = 19200, .cdclk = 624000, .ratio = 65 },
1298 { .refclk = 19200, .cdclk = 79200, .ratio = 33 },
1299 { .refclk = 19200, .cdclk = 158400, .ratio = 33 },
1300 { .refclk = 19200, .cdclk = 316800, .ratio = 33 },
1305 { .refclk = 19200, .cdclk = 172800, .ratio = 18 },
1306 { .refclk = 19200, .cdclk = 192000, .ratio = 20 },
1307 { .refclk = 19200, .cdclk = 307200, .ratio = 32 },
1308 { .refclk = 19200, .cdclk = 326400, .ratio = 68 },
1309 { .refclk = 19200, .cdclk = 556800, .ratio = 58 },
1310 { .refclk = 19200, .cdclk = 652800, .ratio = 68 },
1312 { .refclk = 24000, .cdclk = 180000, .ratio = 15 },
1313 { .refclk = 24000, .cdclk = 192000, .ratio = 16 },
1314 { .refclk = 24000, .cdclk = 312000, .ratio = 26 },
1315 { .refclk = 24000, .cdclk = 324000, .ratio = 54 },
1316 { .refclk = 24000, .cdclk = 552000, .ratio = 46 },
1317 { .refclk = 24000, .cdclk = 648000, .ratio = 54 },
1319 { .refclk = 38400, .cdclk = 172800, .ratio = 9 },
1320 { .refclk = 38400, .cdclk = 192000, .ratio = 10 },
1321 { .refclk = 38400, .cdclk = 307200, .ratio = 16 },
1322 { .refclk = 38400, .cdclk = 326400, .ratio = 34 },
1323 { .refclk = 38400, .cdclk = 556800, .ratio = 29 },
1324 { .refclk = 38400, .cdclk = 652800, .ratio = 34 },
1329 { .refclk = 19200, .cdclk = 172800, .ratio = 36 },
1330 { .refclk = 19200, .cdclk = 192000, .ratio = 40 },
1331 { .refclk = 19200, .cdclk = 307200, .ratio = 64 },
1332 { .refclk = 19200, .cdclk = 326400, .ratio = 136 },
1333 { .refclk = 19200, .cdclk = 556800, .ratio = 116 },
1334 { .refclk = 19200, .cdclk = 652800, .ratio = 136 },
1336 { .refclk = 24000, .cdclk = 180000, .ratio = 30 },
1337 { .refclk = 24000, .cdclk = 192000, .ratio = 32 },
1338 { .refclk = 24000, .cdclk = 312000, .ratio = 52 },
1339 { .refclk = 24000, .cdclk = 324000, .ratio = 108 },
1340 { .refclk = 24000, .cdclk = 552000, .ratio = 92 },
1341 { .refclk = 24000, .cdclk = 648000, .ratio = 108 },
1343 { .refclk = 38400, .cdclk = 172800, .ratio = 18 },
1344 { .refclk = 38400, .cdclk = 192000, .ratio = 20 },
1345 { .refclk = 38400, .cdclk = 307200, .ratio = 32 },
1346 { .refclk = 38400, .cdclk = 326400, .ratio = 68 },
1347 { .refclk = 38400, .cdclk = 556800, .ratio = 58 },
1348 { .refclk = 38400, .cdclk = 652800, .ratio = 68 },
1353 { .refclk = 19200, .cdclk = 307200, .ratio = 32 },
1354 { .refclk = 19200, .cdclk = 556800, .ratio = 58 },
1355 { .refclk = 19200, .cdclk = 652800, .ratio = 68 },
1357 { .refclk = 24000, .cdclk = 312000, .ratio = 26 },
1358 { .refclk = 24000, .cdclk = 552000, .ratio = 46 },
1359 { .refclk = 24400, .cdclk = 648000, .ratio = 54 },
1361 { .refclk = 38400, .cdclk = 307200, .ratio = 16 },
1362 { .refclk = 38400, .cdclk = 556800, .ratio = 29 },
1363 { .refclk = 38400, .cdclk = 652800, .ratio = 34 },
1368 { .refclk = 19200, .cdclk = 172800, .ratio = 27 },
1369 { .refclk = 19200, .cdclk = 192000, .ratio = 20 },
1370 { .refclk = 19200, .cdclk = 307200, .ratio = 32 },
1371 { .refclk = 19200, .cdclk = 556800, .ratio = 58 },
1372 { .refclk = 19200, .cdclk = 652800, .ratio = 68 },
1374 { .refclk = 24000, .cdclk = 176000, .ratio = 22 },
1375 { .refclk = 24000, .cdclk = 192000, .ratio = 16 },
1376 { .refclk = 24000, .cdclk = 312000, .ratio = 26 },
1377 { .refclk = 24000, .cdclk = 552000, .ratio = 46 },
1378 { .refclk = 24000, .cdclk = 648000, .ratio = 54 },
1380 { .refclk = 38400, .cdclk = 179200, .ratio = 14 },
1381 { .refclk = 38400, .cdclk = 192000, .ratio = 10 },
1382 { .refclk = 38400, .cdclk = 307200, .ratio = 16 },
1383 { .refclk = 38400, .cdclk = 556800, .ratio = 29 },
1384 { .refclk = 38400, .cdclk = 652800, .ratio = 34 },
1389 { .refclk = 19200, .cdclk = 172800, .ratio = 27 },
1390 { .refclk = 19200, .cdclk = 192000, .ratio = 20 },
1391 { .refclk = 19200, .cdclk = 307200, .ratio = 32 },
1392 { .refclk = 19200, .cdclk = 480000, .ratio = 50 },
1393 { .refclk = 19200, .cdclk = 556800, .ratio = 58 },
1394 { .refclk = 19200, .cdclk = 652800, .ratio = 68 },
1396 { .refclk = 24000, .cdclk = 176000, .ratio = 22 },
1397 { .refclk = 24000, .cdclk = 192000, .ratio = 16 },
1398 { .refclk = 24000, .cdclk = 312000, .ratio = 26 },
1399 { .refclk = 24000, .cdclk = 480000, .ratio = 40 },
1400 { .refclk = 24000, .cdclk = 552000, .ratio = 46 },
1401 { .refclk = 24000, .cdclk = 648000, .ratio = 54 },
1403 { .refclk = 38400, .cdclk = 179200, .ratio = 14 },
1404 { .refclk = 38400, .cdclk = 192000, .ratio = 10 },
1405 { .refclk = 38400, .cdclk = 307200, .ratio = 16 },
1406 { .refclk = 38400, .cdclk = 480000, .ratio = 25 },
1407 { .refclk = 38400, .cdclk = 556800, .ratio = 29 },
1408 { .refclk = 38400, .cdclk = 652800, .ratio = 34 },
1413 { .refclk = 38400, .cdclk = 163200, .ratio = 34, .waveform = 0x8888 },
1414 { .refclk = 38400, .cdclk = 204000, .ratio = 34, .waveform = 0x9248 },
1415 { .refclk = 38400, .cdclk = 244800, .ratio = 34, .waveform = 0xa4a4 },
1416 { .refclk = 38400, .cdclk = 285600, .ratio = 34, .waveform = 0xa54a },
1417 { .refclk = 38400, .cdclk = 326400, .ratio = 34, .waveform = 0xaaaa },
1418 { .refclk = 38400, .cdclk = 367200, .ratio = 34, .waveform = 0xad5a },
1419 { .refclk = 38400, .cdclk = 408000, .ratio = 34, .waveform = 0xb6b6 },
1420 { .refclk = 38400, .cdclk = 448800, .ratio = 34, .waveform = 0xdbb6 },
1421 { .refclk = 38400, .cdclk = 489600, .ratio = 34, .waveform = 0xeeee },
1422 { .refclk = 38400, .cdclk = 530400, .ratio = 34, .waveform = 0xf7de },
1423 { .refclk = 38400, .cdclk = 571200, .ratio = 34, .waveform = 0xfefe },
1424 { .refclk = 38400, .cdclk = 612000, .ratio = 34, .waveform = 0xfffe },
1425 { .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0xffff },
1430 { .refclk = 38400, .cdclk = 172800, .ratio = 16, .waveform = 0xad5a },
1431 { .refclk = 38400, .cdclk = 192000, .ratio = 16, .waveform = 0xb6b6 },
1432 { .refclk = 38400, .cdclk = 307200, .ratio = 16, .waveform = 0x0000 },
1433 { .refclk = 38400, .cdclk = 480000, .ratio = 25, .waveform = 0x0000 },
1434 { .refclk = 38400, .cdclk = 556800, .ratio = 29, .waveform = 0x0000 },
1435 { .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0x0000 },
1440 { .refclk = 38400, .cdclk = 153600, .ratio = 16, .waveform = 0xaaaa },
1441 { .refclk = 38400, .cdclk = 172800, .ratio = 16, .waveform = 0xad5a },
1442 { .refclk = 38400, .cdclk = 192000, .ratio = 16, .waveform = 0xb6b6 },
1443 { .refclk = 38400, .cdclk = 211200, .ratio = 16, .waveform = 0xdbb6 },
1444 { .refclk = 38400, .cdclk = 230400, .ratio = 16, .waveform = 0xeeee },
1445 { .refclk = 38400, .cdclk = 249600, .ratio = 16, .waveform = 0xf7de },
1446 { .refclk = 38400, .cdclk = 268800, .ratio = 16, .waveform = 0xfefe },
1447 { .refclk = 38400, .cdclk = 288000, .ratio = 16, .waveform = 0xfffe },
1448 { .refclk = 38400, .cdclk = 307200, .ratio = 16, .waveform = 0xffff },
1449 { .refclk = 38400, .cdclk = 330000, .ratio = 25, .waveform = 0xdbb6 },
1450 { .refclk = 38400, .cdclk = 360000, .ratio = 25, .waveform = 0xeeee },
1451 { .refclk = 38400, .cdclk = 390000, .ratio = 25, .waveform = 0xf7de },
1452 { .refclk = 38400, .cdclk = 420000, .ratio = 25, .waveform = 0xfefe },
1453 { .refclk = 38400, .cdclk = 450000, .ratio = 25, .waveform = 0xfffe },
1454 { .refclk = 38400, .cdclk = 480000, .ratio = 25, .waveform = 0xffff },
1455 { .refclk = 38400, .cdclk = 487200, .ratio = 29, .waveform = 0xfefe },
1456 { .refclk = 38400, .cdclk = 522000, .ratio = 29, .waveform = 0xfffe },
1457 { .refclk = 38400, .cdclk = 556800, .ratio = 29, .waveform = 0xffff },
1458 { .refclk = 38400, .cdclk = 571200, .ratio = 34, .waveform = 0xfefe },
1459 { .refclk = 38400, .cdclk = 612000, .ratio = 34, .waveform = 0xfffe },
1460 { .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0xffff },
1465 * Xe2_HPD always uses the minimal cdclk table from Wa_15015413771
1468 { .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0xffff },
1473 { .refclk = 38400, .cdclk = 153600, .ratio = 16, .waveform = 0xaaaa },
1474 { .refclk = 38400, .cdclk = 172800, .ratio = 16, .waveform = 0xad5a },
1475 { .refclk = 38400, .cdclk = 192000, .ratio = 16, .waveform = 0xb6b6 },
1476 { .refclk = 38400, .cdclk = 211200, .ratio = 16, .waveform = 0xdbb6 },
1477 { .refclk = 38400, .cdclk = 230400, .ratio = 16, .waveform = 0xeeee },
1478 { .refclk = 38400, .cdclk = 249600, .ratio = 16, .waveform = 0xf7de },
1479 { .refclk = 38400, .cdclk = 268800, .ratio = 16, .waveform = 0xfefe },
1480 { .refclk = 38400, .cdclk = 288000, .ratio = 16, .waveform = 0xfffe },
1481 { .refclk = 38400, .cdclk = 307200, .ratio = 16, .waveform = 0xffff },
1482 { .refclk = 38400, .cdclk = 326400, .ratio = 17, .waveform = 0xffff },
1483 { .refclk = 38400, .cdclk = 345600, .ratio = 18, .waveform = 0xffff },
1484 { .refclk = 38400, .cdclk = 364800, .ratio = 19, .waveform = 0xffff },
1485 { .refclk = 38400, .cdclk = 384000, .ratio = 20, .waveform = 0xffff },
1486 { .refclk = 38400, .cdclk = 403200, .ratio = 21, .waveform = 0xffff },
1487 { .refclk = 38400, .cdclk = 422400, .ratio = 22, .waveform = 0xffff },
1488 { .refclk = 38400, .cdclk = 441600, .ratio = 23, .waveform = 0xffff },
1489 { .refclk = 38400, .cdclk = 460800, .ratio = 24, .waveform = 0xffff },
1490 { .refclk = 38400, .cdclk = 480000, .ratio = 25, .waveform = 0xffff },
1491 { .refclk = 38400, .cdclk = 499200, .ratio = 26, .waveform = 0xffff },
1492 { .refclk = 38400, .cdclk = 518400, .ratio = 27, .waveform = 0xffff },
1493 { .refclk = 38400, .cdclk = 537600, .ratio = 28, .waveform = 0xffff },
1494 { .refclk = 38400, .cdclk = 556800, .ratio = 29, .waveform = 0xffff },
1495 { .refclk = 38400, .cdclk = 576000, .ratio = 30, .waveform = 0xffff },
1496 { .refclk = 38400, .cdclk = 595200, .ratio = 31, .waveform = 0xffff },
1497 { .refclk = 38400, .cdclk = 614400, .ratio = 32, .waveform = 0xffff },
1498 { .refclk = 38400, .cdclk = 633600, .ratio = 33, .waveform = 0xffff },
1499 { .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0xffff },
1500 { .refclk = 38400, .cdclk = 672000, .ratio = 35, .waveform = 0xffff },
1501 { .refclk = 38400, .cdclk = 691200, .ratio = 36, .waveform = 0xffff },
1512 static int cdclk_divider(int cdclk, int vco, u16 waveform) in cdclk_divider() argument
1516 cdclk * cdclk_squash_len); in cdclk_divider()
1521 const struct intel_cdclk_vals *table = display->cdclk.table; in bxt_calc_cdclk()
1525 if (table[i].refclk == display->cdclk.hw.ref && in bxt_calc_cdclk()
1526 table[i].cdclk >= min_cdclk) in bxt_calc_cdclk()
1527 return table[i].cdclk; in bxt_calc_cdclk()
1530 "Cannot satisfy minimum cdclk %d with refclk %u\n", in bxt_calc_cdclk()
1531 min_cdclk, display->cdclk.hw.ref); in bxt_calc_cdclk()
1535 static int bxt_calc_cdclk_pll_vco(struct intel_display *display, int cdclk) in bxt_calc_cdclk_pll_vco() argument
1537 const struct intel_cdclk_vals *table = display->cdclk.table; in bxt_calc_cdclk_pll_vco()
1540 if (cdclk == display->cdclk.hw.bypass) in bxt_calc_cdclk_pll_vco()
1544 if (table[i].refclk == display->cdclk.hw.ref && in bxt_calc_cdclk_pll_vco()
1545 table[i].cdclk == cdclk) in bxt_calc_cdclk_pll_vco()
1546 return display->cdclk.hw.ref * table[i].ratio; in bxt_calc_cdclk_pll_vco()
1548 drm_WARN(display->drm, 1, "cdclk %d not valid for refclk %u\n", in bxt_calc_cdclk_pll_vco()
1549 cdclk, display->cdclk.hw.ref); in bxt_calc_cdclk_pll_vco()
1553 static u8 bxt_calc_voltage_level(int cdclk) in bxt_calc_voltage_level() argument
1555 return DIV_ROUND_UP(cdclk, 25000); in bxt_calc_voltage_level()
1558 static u8 calc_voltage_level(int cdclk, int num_voltage_levels, in calc_voltage_level() argument
1564 if (cdclk <= voltage_level_max_cdclk[voltage_level]) in calc_voltage_level()
1568 MISSING_CASE(cdclk); in calc_voltage_level()
1572 static u8 icl_calc_voltage_level(int cdclk) in icl_calc_voltage_level() argument
1580 return calc_voltage_level(cdclk, in icl_calc_voltage_level()
1585 static u8 ehl_calc_voltage_level(int cdclk) in ehl_calc_voltage_level() argument
1598 return calc_voltage_level(cdclk, in ehl_calc_voltage_level()
1603 static u8 tgl_calc_voltage_level(int cdclk) in tgl_calc_voltage_level() argument
1612 return calc_voltage_level(cdclk, in tgl_calc_voltage_level()
1617 static u8 rplu_calc_voltage_level(int cdclk) in rplu_calc_voltage_level() argument
1626 return calc_voltage_level(cdclk, in rplu_calc_voltage_level()
1631 static u8 xe3lpd_calc_voltage_level(int cdclk) in xe3lpd_calc_voltage_level() argument
1679 * CDCLK PLL is disabled, the VCO/ratio doesn't matter, but in bxt_de_pll_readout()
1715 cdclk_config->cdclk = cdclk_config->bypass; in bxt_get_cdclk()
1749 cdclk_config->cdclk = DIV_ROUND_CLOSEST(hweight16(waveform) * in bxt_get_cdclk()
1752 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco, div); in bxt_get_cdclk()
1760 * at least what the CDCLK frequency requires. in bxt_get_cdclk()
1763 intel_cdclk_calc_voltage_level(display, cdclk_config->cdclk); in bxt_get_cdclk()
1775 display->cdclk.hw.vco = 0; in bxt_de_pll_disable()
1780 int ratio = DIV_ROUND_CLOSEST(vco, display->cdclk.hw.ref); in bxt_de_pll_enable()
1792 display->cdclk.hw.vco = vco; in bxt_de_pll_enable()
1802 drm_err(display->drm, "timeout waiting for CDCLK PLL unlock\n"); in icl_cdclk_pll_disable()
1804 display->cdclk.hw.vco = 0; in icl_cdclk_pll_disable()
1809 int ratio = DIV_ROUND_CLOSEST(vco, display->cdclk.hw.ref); in icl_cdclk_pll_enable()
1820 drm_err(display->drm, "timeout waiting for CDCLK PLL lock\n"); in icl_cdclk_pll_enable()
1822 display->cdclk.hw.vco = vco; in icl_cdclk_pll_enable()
1827 int ratio = DIV_ROUND_CLOSEST(vco, display->cdclk.hw.ref); in adlp_cdclk_pll_crawl()
1846 display->cdclk.hw.vco = vco; in adlp_cdclk_pll_crawl()
1870 int cdclk, int vco, u16 waveform) in bxt_cdclk_cd2x_div_sel() argument
1872 /* cdclk = vco / 2 / div{1,1.5,2,4} */ in bxt_cdclk_cd2x_div_sel()
1873 switch (cdclk_divider(cdclk, vco, waveform)) { in bxt_cdclk_cd2x_div_sel()
1876 cdclk != display->cdclk.hw.bypass); in bxt_cdclk_cd2x_div_sel()
1891 int cdclk) in cdclk_squash_waveform() argument
1893 const struct intel_cdclk_vals *table = display->cdclk.table; in cdclk_squash_waveform()
1896 if (cdclk == display->cdclk.hw.bypass) in cdclk_squash_waveform()
1900 if (table[i].refclk == display->cdclk.hw.ref && in cdclk_squash_waveform()
1901 table[i].cdclk == cdclk) in cdclk_squash_waveform()
1904 drm_WARN(display->drm, 1, "cdclk %d not valid for refclk %u\n", in cdclk_squash_waveform()
1905 cdclk, display->cdclk.hw.ref); in cdclk_squash_waveform()
1912 if (display->cdclk.hw.vco != 0 && in icl_cdclk_pll_update()
1913 display->cdclk.hw.vco != vco) in icl_cdclk_pll_update()
1916 if (display->cdclk.hw.vco != vco) in icl_cdclk_pll_update()
1922 if (display->cdclk.hw.vco != 0 && in bxt_cdclk_pll_update()
1923 display->cdclk.hw.vco != vco) in bxt_cdclk_pll_update()
1926 if (display->cdclk.hw.vco != vco) in bxt_cdclk_pll_update()
1969 return DIV_ROUND_UP(cdclk_config->vco, cdclk_config->cdclk); in intel_mdclk_cdclk_ratio()
2001 old_waveform = cdclk_squash_waveform(display, old_cdclk_config->cdclk); in cdclk_compute_crawl_and_squash_midpoint()
2002 new_waveform = cdclk_squash_waveform(display, new_cdclk_config->cdclk); in cdclk_compute_crawl_and_squash_midpoint()
2010 old_div = cdclk_divider(old_cdclk_config->cdclk, in cdclk_compute_crawl_and_squash_midpoint()
2012 new_div = cdclk_divider(new_cdclk_config->cdclk, in cdclk_compute_crawl_and_squash_midpoint()
2026 * - If moving to a higher cdclk, the desired action is squashing. in cdclk_compute_crawl_and_squash_midpoint()
2027 * The mid cdclk config should have the new (squash) waveform. in cdclk_compute_crawl_and_squash_midpoint()
2028 * - If moving to a lower cdclk, the desired action is crawling. in cdclk_compute_crawl_and_squash_midpoint()
2029 * The mid cdclk config should have the new vco. in cdclk_compute_crawl_and_squash_midpoint()
2042 mid_cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_squash_divider(mid_waveform) * in cdclk_compute_crawl_and_squash_midpoint()
2048 drm_WARN_ON(display->drm, mid_cdclk_config->cdclk < in cdclk_compute_crawl_and_squash_midpoint()
2049 min(old_cdclk_config->cdclk, new_cdclk_config->cdclk)); in cdclk_compute_crawl_and_squash_midpoint()
2050 drm_WARN_ON(display->drm, mid_cdclk_config->cdclk > in cdclk_compute_crawl_and_squash_midpoint()
2051 display->cdclk.max_cdclk_freq); in cdclk_compute_crawl_and_squash_midpoint()
2052 drm_WARN_ON(display->drm, cdclk_squash_waveform(display, mid_cdclk_config->cdclk) != in cdclk_compute_crawl_and_squash_midpoint()
2065 display->cdclk.hw.vco > 0; in pll_enable_wa_needed()
2073 int cdclk = cdclk_config->cdclk; in bxt_cdclk_ctl() local
2078 waveform = cdclk_squash_waveform(display, cdclk); in bxt_cdclk_ctl()
2080 val = bxt_cdclk_cd2x_div_sel(display, cdclk, vco, waveform) | in bxt_cdclk_ctl()
2088 cdclk >= 500000) in bxt_cdclk_ctl()
2094 val |= skl_cdclk_decimal(cdclk); in bxt_cdclk_ctl()
2103 int cdclk = cdclk_config->cdclk; in _bxt_set_cdclk() local
2106 if (HAS_CDCLK_CRAWL(display) && display->cdclk.hw.vco > 0 && vco > 0 && in _bxt_set_cdclk()
2107 !cdclk_pll_is_unknown(display->cdclk.hw.vco)) { in _bxt_set_cdclk()
2108 if (display->cdclk.hw.vco != vco) in _bxt_set_cdclk()
2121 u16 waveform = cdclk_squash_waveform(display, cdclk); in _bxt_set_cdclk()
2138 int cdclk = cdclk_config->cdclk; in bxt_set_cdclk() local
2165 "Failed to inform PCU about cdclk change (err %d, freq %d)\n", in bxt_set_cdclk()
2166 ret, cdclk); in bxt_set_cdclk()
2170 if (DISPLAY_VER(display) >= 20 && cdclk < display->cdclk.hw.cdclk) in bxt_set_cdclk()
2173 if (cdclk_compute_crawl_and_squash_midpoint(display, &display->cdclk.hw, in bxt_set_cdclk()
2181 if (DISPLAY_VER(display) >= 20 && cdclk > display->cdclk.hw.cdclk) in bxt_set_cdclk()
2206 "PCode CDCLK freq set failed, (err %d, freq %d)\n", in bxt_set_cdclk()
2207 ret, cdclk); in bxt_set_cdclk()
2218 display->cdclk.hw.voltage_level = cdclk_config->voltage_level; in bxt_set_cdclk()
2224 int cdclk, vco; in bxt_sanitize_cdclk() local
2227 intel_cdclk_dump_config(display, &display->cdclk.hw, "Current CDCLK"); in bxt_sanitize_cdclk()
2229 if (display->cdclk.hw.vco == 0 || in bxt_sanitize_cdclk()
2230 display->cdclk.hw.cdclk == display->cdclk.hw.bypass) in bxt_sanitize_cdclk()
2233 /* Make sure this is a legal cdclk value for the platform */ in bxt_sanitize_cdclk()
2234 cdclk = bxt_calc_cdclk(display, display->cdclk.hw.cdclk); in bxt_sanitize_cdclk()
2235 if (cdclk != display->cdclk.hw.cdclk) in bxt_sanitize_cdclk()
2238 /* Make sure the VCO is correct for the cdclk */ in bxt_sanitize_cdclk()
2239 vco = bxt_calc_cdclk_pll_vco(display, cdclk); in bxt_sanitize_cdclk()
2240 if (vco != display->cdclk.hw.vco) in bxt_sanitize_cdclk()
2249 expected = bxt_cdclk_ctl(display, &display->cdclk.hw, INVALID_PIPE); in bxt_sanitize_cdclk()
2264 drm_dbg_kms(display->drm, "Sanitizing cdclk programmed by pre-os\n"); in bxt_sanitize_cdclk()
2266 /* force cdclk programming */ in bxt_sanitize_cdclk()
2267 display->cdclk.hw.cdclk = 0; in bxt_sanitize_cdclk()
2270 display->cdclk.hw.vco = ~0; in bxt_sanitize_cdclk()
2279 if (display->cdclk.hw.cdclk != 0 && in bxt_cdclk_init_hw()
2280 display->cdclk.hw.vco != 0) in bxt_cdclk_init_hw()
2283 cdclk_config = display->cdclk.hw; in bxt_cdclk_init_hw()
2287 * - The initial CDCLK needs to be read from VBT. in bxt_cdclk_init_hw()
2290 cdclk_config.cdclk = bxt_calc_cdclk(display, 0); in bxt_cdclk_init_hw()
2291 cdclk_config.vco = bxt_calc_cdclk_pll_vco(display, cdclk_config.cdclk); in bxt_cdclk_init_hw()
2293 intel_cdclk_calc_voltage_level(display, cdclk_config.cdclk); in bxt_cdclk_init_hw()
2300 struct intel_cdclk_config cdclk_config = display->cdclk.hw; in bxt_cdclk_uninit_hw()
2302 cdclk_config.cdclk = cdclk_config.bypass; in bxt_cdclk_uninit_hw()
2305 intel_cdclk_calc_voltage_level(display, cdclk_config.cdclk); in bxt_cdclk_uninit_hw()
2311 * intel_cdclk_init_hw - Initialize CDCLK hardware
2314 * Initialize CDCLK. This consists mainly of initializing display->cdclk.hw and
2317 * take care of turning CDCLK off/on as needed.
2330 * intel_cdclk_uninit_hw - Uninitialize CDCLK hardware
2333 * Uninitialize CDCLK. This is done only during the display core
2361 old_waveform = cdclk_squash_waveform(display, a->cdclk); in intel_cdclk_can_crawl_and_squash()
2362 new_waveform = cdclk_squash_waveform(display, b->cdclk); in intel_cdclk_can_crawl_and_squash()
2381 a_div = DIV_ROUND_CLOSEST(a->vco, a->cdclk); in intel_cdclk_can_crawl()
2382 b_div = DIV_ROUND_CLOSEST(b->vco, b->cdclk); in intel_cdclk_can_crawl()
2403 return a->cdclk != b->cdclk && in intel_cdclk_can_squash()
2411 * @a: first CDCLK configuration
2412 * @b: second CDCLK configuration
2415 * True if CDCLK changed in a way that requires re-programming and
2421 return a->cdclk != b->cdclk || in intel_cdclk_clock_changed()
2427 * intel_cdclk_can_cd2x_update - Determine if changing between the two CDCLK
2430 * @a: first CDCLK configuration
2431 * @b: second CDCLK configuration
2434 * True if changing between the two CDCLK configurations
2456 return a->cdclk != b->cdclk && in intel_cdclk_can_cd2x_update()
2463 * intel_cdclk_changed - Determine if two CDCLK configurations are different
2464 * @a: first CDCLK configuration
2465 * @b: second CDCLK configuration
2468 * True if the CDCLK configurations don't match, false if they do.
2482 context, cdclk_config->cdclk, cdclk_config->vco, in intel_cdclk_dump_config()
2490 u16 cdclk, in intel_pcode_notify() argument
2501 update_mask = DISPLAY_TO_PCODE_UPDATE_MASK(cdclk, active_pipe_count, voltage_level); in intel_pcode_notify()
2527 if (!intel_cdclk_changed(&display->cdclk.hw, cdclk_config)) in intel_set_cdclk()
2530 if (drm_WARN_ON_ONCE(display->drm, !display->funcs.cdclk->set_cdclk)) in intel_set_cdclk()
2544 * Lock aux/gmbus while we change cdclk in case those in intel_set_cdclk()
2545 * functions use cdclk. Not all platforms/ports do, in intel_set_cdclk()
2574 intel_cdclk_changed(&display->cdclk.hw, cdclk_config), in intel_set_cdclk()
2575 "cdclk state doesn't match!\n")) { in intel_set_cdclk()
2576 intel_cdclk_dump_config(display, &display->cdclk.hw, "[hw state]"); in intel_set_cdclk()
2588 unsigned int cdclk = 0; u8 voltage_level, num_active_pipes = 0; in intel_cdclk_pcode_pre_notify() local
2600 change_cdclk = new_cdclk_state->actual.cdclk != old_cdclk_state->actual.cdclk; in intel_cdclk_pcode_pre_notify()
2606 * if CDCLK is increasing, set bits 25:16 to upcoming CDCLK, in intel_cdclk_pcode_pre_notify()
2607 * if CDCLK is decreasing or not changing, set bits 25:16 to current CDCLK, in intel_cdclk_pcode_pre_notify()
2608 * which basically means we choose the maximum of old and new CDCLK, if we know both in intel_cdclk_pcode_pre_notify()
2611 cdclk = max(new_cdclk_state->actual.cdclk, old_cdclk_state->actual.cdclk); in intel_cdclk_pcode_pre_notify()
2622 intel_pcode_notify(display, voltage_level, num_active_pipes, cdclk, in intel_cdclk_pcode_pre_notify()
2633 unsigned int cdclk = 0; u8 voltage_level, num_active_pipes = 0; in intel_cdclk_pcode_post_notify() local
2639 update_cdclk = new_cdclk_state->actual.cdclk != old_cdclk_state->actual.cdclk; in intel_cdclk_pcode_post_notify()
2645 * set bits 25:16 to current CDCLK in intel_cdclk_pcode_post_notify()
2648 cdclk = new_cdclk_state->actual.cdclk; in intel_cdclk_pcode_post_notify()
2659 intel_pcode_notify(display, voltage_level, num_active_pipes, cdclk, in intel_cdclk_pcode_post_notify()
2671 new_cdclk_state->actual.cdclk < old_cdclk_state->actual.cdclk; in intel_cdclk_is_decreasing_later()
2675 * intel_set_cdclk_pre_plane_update - Push the CDCLK state to the hardware
2679 * new CDCLK state, if necessary.
2704 if (new_cdclk_state->actual.cdclk >= old_cdclk_state->actual.cdclk) { in intel_set_cdclk_pre_plane_update()
2725 "Pre changing CDCLK to"); in intel_set_cdclk_pre_plane_update()
2729 * intel_set_cdclk_post_plane_update - Push the CDCLK state to the hardware
2733 * new CDCLK state, if necessary.
2754 new_cdclk_state->actual.cdclk < old_cdclk_state->actual.cdclk) in intel_set_cdclk_post_plane_update()
2762 "Post changing CDCLK to"); in intel_set_cdclk_post_plane_update()
2765 /* pixels per CDCLK */
2771 /* max pixel rate as % of CDCLK (not accounting for PPC) */
2877 * CDCLK frequency is always high enough for audio. With a in intel_compute_min_cdclk()
2878 * single active pipe we can always change CDCLK frequency in intel_compute_min_cdclk()
2886 if (min_cdclk > display->cdclk.max_cdclk_freq) { in intel_compute_min_cdclk()
2888 "required cdclk (%d kHz) exceeds max (%d kHz)\n", in intel_compute_min_cdclk()
2889 min_cdclk, display->cdclk.max_cdclk_freq); in intel_compute_min_cdclk()
2951 int min_cdclk, cdclk; in vlv_modeset_calc_cdclk() local
2957 cdclk = vlv_calc_cdclk(display, min_cdclk); in vlv_modeset_calc_cdclk()
2959 cdclk_state->logical.cdclk = cdclk; in vlv_modeset_calc_cdclk()
2961 vlv_calc_voltage_level(display, cdclk); in vlv_modeset_calc_cdclk()
2964 cdclk = vlv_calc_cdclk(display, cdclk_state->force_min_cdclk); in vlv_modeset_calc_cdclk()
2966 cdclk_state->actual.cdclk = cdclk; in vlv_modeset_calc_cdclk()
2968 vlv_calc_voltage_level(display, cdclk); in vlv_modeset_calc_cdclk()
2980 int min_cdclk, cdclk; in bdw_modeset_calc_cdclk() local
2986 cdclk = bdw_calc_cdclk(min_cdclk); in bdw_modeset_calc_cdclk()
2988 cdclk_state->logical.cdclk = cdclk; in bdw_modeset_calc_cdclk()
2990 bdw_calc_voltage_level(cdclk); in bdw_modeset_calc_cdclk()
2993 cdclk = bdw_calc_cdclk(cdclk_state->force_min_cdclk); in bdw_modeset_calc_cdclk()
2995 cdclk_state->actual.cdclk = cdclk; in bdw_modeset_calc_cdclk()
2997 bdw_calc_voltage_level(cdclk); in bdw_modeset_calc_cdclk()
3016 vco = display->cdclk.skl_preferred_vco_freq; in skl_dpll0_vco()
3027 * clock for eDP. This will affect cdclk as well. in skl_dpll0_vco()
3047 int min_cdclk, cdclk, vco; in skl_modeset_calc_cdclk() local
3055 cdclk = skl_calc_cdclk(min_cdclk, vco); in skl_modeset_calc_cdclk()
3058 cdclk_state->logical.cdclk = cdclk; in skl_modeset_calc_cdclk()
3060 skl_calc_voltage_level(cdclk); in skl_modeset_calc_cdclk()
3063 cdclk = skl_calc_cdclk(cdclk_state->force_min_cdclk, vco); in skl_modeset_calc_cdclk()
3066 cdclk_state->actual.cdclk = cdclk; in skl_modeset_calc_cdclk()
3068 skl_calc_voltage_level(cdclk); in skl_modeset_calc_cdclk()
3081 int min_cdclk, min_voltage_level, cdclk, vco; in bxt_modeset_calc_cdclk() local
3091 cdclk = bxt_calc_cdclk(display, min_cdclk); in bxt_modeset_calc_cdclk()
3092 vco = bxt_calc_cdclk_pll_vco(display, cdclk); in bxt_modeset_calc_cdclk()
3095 cdclk_state->logical.cdclk = cdclk; in bxt_modeset_calc_cdclk()
3098 intel_cdclk_calc_voltage_level(display, cdclk)); in bxt_modeset_calc_cdclk()
3101 cdclk = bxt_calc_cdclk(display, cdclk_state->force_min_cdclk); in bxt_modeset_calc_cdclk()
3102 vco = bxt_calc_cdclk_pll_vco(display, cdclk); in bxt_modeset_calc_cdclk()
3105 cdclk_state->actual.cdclk = cdclk; in bxt_modeset_calc_cdclk()
3107 intel_cdclk_calc_voltage_level(display, cdclk); in bxt_modeset_calc_cdclk()
3120 * We can't change the cdclk frequency, but we still want to in fixed_modeset_calc_cdclk()
3122 * the actual cdclk frequency. in fixed_modeset_calc_cdclk()
3162 cdclk_state = intel_atomic_get_global_obj_state(state, &display->cdclk.obj); in intel_atomic_get_cdclk_state()
3181 * planes are part of the state. We can now compute the minimum cdclk in intel_cdclk_atomic_check()
3226 intel_atomic_global_obj_init(display, &display->cdclk.obj, in intel_cdclk_init()
3310 "Can change cdclk via crawling and squashing\n"); in intel_modeset_calc_cdclk()
3315 "Can change cdclk via squashing\n"); in intel_modeset_calc_cdclk()
3320 "Can change cdclk via crawling\n"); in intel_modeset_calc_cdclk()
3325 "Can change cdclk cd2x divider with pipe %c active\n", in intel_modeset_calc_cdclk()
3329 /* All pipes must be switched off while we change the cdclk. */ in intel_modeset_calc_cdclk()
3330 ret = intel_modeset_all_pipes_late(state, "CDCLK change"); in intel_modeset_calc_cdclk()
3337 "Modeset required for cdclk change\n"); in intel_modeset_calc_cdclk()
3350 "New cdclk calculated to be logical %u kHz, actual %u kHz\n", in intel_modeset_calc_cdclk()
3351 new_cdclk_state->logical.cdclk, in intel_modeset_calc_cdclk()
3352 new_cdclk_state->actual.cdclk); in intel_modeset_calc_cdclk()
3365 int max_cdclk_freq = display->cdclk.max_cdclk_freq; in intel_compute_max_dotclk()
3371 * intel_update_max_cdclk - Determine the maximum support CDCLK frequency
3374 * Determine the maximum CDCLK frequency the platform supports, and also
3375 * derive the maximum dot clock frequency the maximum CDCLK frequency
3383 display->cdclk.max_cdclk_freq = 691200; in intel_update_max_cdclk()
3385 if (display->cdclk.hw.ref == 24000) in intel_update_max_cdclk()
3386 display->cdclk.max_cdclk_freq = 552000; in intel_update_max_cdclk()
3388 display->cdclk.max_cdclk_freq = 556800; in intel_update_max_cdclk()
3390 if (display->cdclk.hw.ref == 24000) in intel_update_max_cdclk()
3391 display->cdclk.max_cdclk_freq = 648000; in intel_update_max_cdclk()
3393 display->cdclk.max_cdclk_freq = 652800; in intel_update_max_cdclk()
3395 display->cdclk.max_cdclk_freq = 316800; in intel_update_max_cdclk()
3397 display->cdclk.max_cdclk_freq = 624000; in intel_update_max_cdclk()
3402 vco = display->cdclk.skl_preferred_vco_freq; in intel_update_max_cdclk()
3406 * Use the lower (vco 8640) cdclk values as a in intel_update_max_cdclk()
3419 display->cdclk.max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco); in intel_update_max_cdclk()
3428 display->cdclk.max_cdclk_freq = 450000; in intel_update_max_cdclk()
3430 display->cdclk.max_cdclk_freq = 450000; in intel_update_max_cdclk()
3432 display->cdclk.max_cdclk_freq = 540000; in intel_update_max_cdclk()
3434 display->cdclk.max_cdclk_freq = 675000; in intel_update_max_cdclk()
3436 display->cdclk.max_cdclk_freq = 320000; in intel_update_max_cdclk()
3438 display->cdclk.max_cdclk_freq = 400000; in intel_update_max_cdclk()
3440 /* otherwise assume cdclk is fixed */ in intel_update_max_cdclk()
3441 display->cdclk.max_cdclk_freq = display->cdclk.hw.cdclk; in intel_update_max_cdclk()
3444 display->cdclk.max_dotclk_freq = intel_compute_max_dotclk(display); in intel_update_max_cdclk()
3447 display->cdclk.max_cdclk_freq); in intel_update_max_cdclk()
3450 display->cdclk.max_dotclk_freq); in intel_update_max_cdclk()
3454 * intel_update_cdclk - Determine the current CDCLK frequency
3457 * Determine the current CDCLK frequency.
3463 intel_cdclk_get_cdclk(display, &display->cdclk.hw); in intel_update_cdclk()
3466 * 9:0 CMBUS [sic] CDCLK frequency (cdfreq): in intel_update_cdclk()
3468 * of cdclk that generates 4MHz reference clock freq which is used to in intel_update_cdclk()
3469 * generate GMBus clock. This will vary with the cdclk freq. in intel_update_cdclk()
3473 DIV_ROUND_UP(display->cdclk.hw.cdclk, 1000)); in intel_update_cdclk()
3580 seq_printf(m, "Current CD clock frequency: %d kHz\n", display->cdclk.hw.cdclk); in i915_cdclk_info_show()
3581 seq_printf(m, "Max CD clock frequency: %d kHz\n", display->cdclk.max_cdclk_freq); in i915_cdclk_info_show()
3582 seq_printf(m, "Max pixel clock frequency: %d kHz\n", display->cdclk.max_dotclk_freq); in i915_cdclk_info_show()
3741 * intel_init_cdclk_hooks - Initialize CDCLK related modesetting hooks
3749 display->funcs.cdclk = &xe3lpd_cdclk_funcs; in intel_init_cdclk_hooks()
3750 display->cdclk.table = xe3lpd_cdclk_table; in intel_init_cdclk_hooks()
3752 display->funcs.cdclk = &rplu_cdclk_funcs; in intel_init_cdclk_hooks()
3753 display->cdclk.table = xe2lpd_cdclk_table; in intel_init_cdclk_hooks()
3755 display->funcs.cdclk = &rplu_cdclk_funcs; in intel_init_cdclk_hooks()
3756 display->cdclk.table = xe2hpd_cdclk_table; in intel_init_cdclk_hooks()
3758 display->funcs.cdclk = &rplu_cdclk_funcs; in intel_init_cdclk_hooks()
3759 display->cdclk.table = mtl_cdclk_table; in intel_init_cdclk_hooks()
3761 display->funcs.cdclk = &tgl_cdclk_funcs; in intel_init_cdclk_hooks()
3762 display->cdclk.table = dg2_cdclk_table; in intel_init_cdclk_hooks()
3766 display->cdclk.table = adlp_a_step_cdclk_table; in intel_init_cdclk_hooks()
3767 display->funcs.cdclk = &tgl_cdclk_funcs; in intel_init_cdclk_hooks()
3769 display->cdclk.table = rplu_cdclk_table; in intel_init_cdclk_hooks()
3770 display->funcs.cdclk = &rplu_cdclk_funcs; in intel_init_cdclk_hooks()
3772 display->cdclk.table = adlp_cdclk_table; in intel_init_cdclk_hooks()
3773 display->funcs.cdclk = &tgl_cdclk_funcs; in intel_init_cdclk_hooks()
3776 display->funcs.cdclk = &tgl_cdclk_funcs; in intel_init_cdclk_hooks()
3777 display->cdclk.table = rkl_cdclk_table; in intel_init_cdclk_hooks()
3779 display->funcs.cdclk = &tgl_cdclk_funcs; in intel_init_cdclk_hooks()
3780 display->cdclk.table = icl_cdclk_table; in intel_init_cdclk_hooks()
3782 display->funcs.cdclk = &ehl_cdclk_funcs; in intel_init_cdclk_hooks()
3783 display->cdclk.table = icl_cdclk_table; in intel_init_cdclk_hooks()
3785 display->funcs.cdclk = &icl_cdclk_funcs; in intel_init_cdclk_hooks()
3786 display->cdclk.table = icl_cdclk_table; in intel_init_cdclk_hooks()
3788 display->funcs.cdclk = &bxt_cdclk_funcs; in intel_init_cdclk_hooks()
3790 display->cdclk.table = glk_cdclk_table; in intel_init_cdclk_hooks()
3792 display->cdclk.table = bxt_cdclk_table; in intel_init_cdclk_hooks()
3794 display->funcs.cdclk = &skl_cdclk_funcs; in intel_init_cdclk_hooks()
3796 display->funcs.cdclk = &bdw_cdclk_funcs; in intel_init_cdclk_hooks()
3798 display->funcs.cdclk = &hsw_cdclk_funcs; in intel_init_cdclk_hooks()
3800 display->funcs.cdclk = &chv_cdclk_funcs; in intel_init_cdclk_hooks()
3802 display->funcs.cdclk = &vlv_cdclk_funcs; in intel_init_cdclk_hooks()
3804 display->funcs.cdclk = &fixed_400mhz_cdclk_funcs; in intel_init_cdclk_hooks()
3806 display->funcs.cdclk = &ilk_cdclk_funcs; in intel_init_cdclk_hooks()
3808 display->funcs.cdclk = &gm45_cdclk_funcs; in intel_init_cdclk_hooks()
3810 display->funcs.cdclk = &g33_cdclk_funcs; in intel_init_cdclk_hooks()
3812 display->funcs.cdclk = &i965gm_cdclk_funcs; in intel_init_cdclk_hooks()
3814 display->funcs.cdclk = &fixed_400mhz_cdclk_funcs; in intel_init_cdclk_hooks()
3816 display->funcs.cdclk = &pnv_cdclk_funcs; in intel_init_cdclk_hooks()
3818 display->funcs.cdclk = &g33_cdclk_funcs; in intel_init_cdclk_hooks()
3820 display->funcs.cdclk = &i945gm_cdclk_funcs; in intel_init_cdclk_hooks()
3822 display->funcs.cdclk = &fixed_400mhz_cdclk_funcs; in intel_init_cdclk_hooks()
3824 display->funcs.cdclk = &i915gm_cdclk_funcs; in intel_init_cdclk_hooks()
3826 display->funcs.cdclk = &i915g_cdclk_funcs; in intel_init_cdclk_hooks()
3828 display->funcs.cdclk = &i865g_cdclk_funcs; in intel_init_cdclk_hooks()
3830 display->funcs.cdclk = &i85x_cdclk_funcs; in intel_init_cdclk_hooks()
3832 display->funcs.cdclk = &i845g_cdclk_funcs; in intel_init_cdclk_hooks()
3834 display->funcs.cdclk = &i830_cdclk_funcs; in intel_init_cdclk_hooks()
3837 if (drm_WARN(display->drm, !display->funcs.cdclk, in intel_init_cdclk_hooks()
3839 display->funcs.cdclk = &i830_cdclk_funcs; in intel_init_cdclk_hooks()