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/linux/tools/perf/pmu-events/arch/x86/emeraldrapids/
H A D	cache.json	7 …as found unmodified in the (FE) Forward or Exclusive State in this cores caches cache. A single s… 16 …m this core's caches, after the data is forwarded back to the requestor, and indicating the data w… 25 …n this core's caches without forwarded back to the requestor. The line was in Forward, Shared or E… 34 … to snoops indicating that the data was not found (IHitI) in this core's caches. A single snoop re… 649 … cache prefetches that hit in the L3 or were snooped from another core's caches on the same socket… 655 … cache prefetches that hit in the L3 or were snooped from another core's caches on the same socket… 660 …refetches that resulted in a snoop hit a modified line in another core's caches which forwarded th… 666 …refetches that resulted in a snoop hit a modified line in another core's caches which forwarded th… 671 …d line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket whe… 677 …d line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket whe… [all …]
H A D	memory.json	188 …1 instruction cache prefetches that were not supplied by the local socket's L1, L2, or L3 caches.", 194 …he prefetches that were not supplied by the local socket's L1, L2, or L3 caches. Available PDIST c… 232 …on": "Counts demand data reads that were not supplied by the local socket's L1, L2, or L3 caches.", 238 …nd data reads that were not supplied by the local socket's L1, L2, or L3 caches. Available PDIST c… 287 …xclusive ownership (PREFETCHW) that were not supplied by the local socket's L1, L2, or L3 caches.", 293 …p (PREFETCHW) that were not supplied by the local socket's L1, L2, or L3 caches. Available PDIST c… 320 … "Counts hardware prefetches to the L3 only that missed the local socket's L1, L2, and L3 caches.", 326 … prefetches to the L3 only that missed the local socket's L1, L2, and L3 caches. Available PDIST c… 331 …o the L3 only that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline … 337 …o the L3 only that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline … [all …]
/linux/tools/perf/pmu-events/arch/x86/sapphirerapids/
H A D	cache.json	7 …as found unmodified in the (FE) Forward or Exclusive State in this cores caches cache. A single s… 16 …m this core's caches, after the data is forwarded back to the requestor, and indicating the data w… 25 …n this core's caches without forwarded back to the requestor. The line was in Forward, Shared or E… 34 … to snoops indicating that the data was not found (IHitI) in this core's caches. A single snoop re… 541 …l(R) Optane(TM) DC persistent memory as the data source where the data request missed all caches.", 630 …l(R) Optane(TM) DC persistent memory as the data source where the data request missed all caches.", 668 … cache prefetches that hit in the L3 or were snooped from another core's caches on the same socket… 674 … cache prefetches that hit in the L3 or were snooped from another core's caches on the same socket… 679 …refetches that resulted in a snoop hit a modified line in another core's caches which forwarded th… 685 …refetches that resulted in a snoop hit a modified line in another core's caches which forwarded th… [all …]
H A D	memory.json	188 …1 instruction cache prefetches that were not supplied by the local socket's L1, L2, or L3 caches.", 194 …he prefetches that were not supplied by the local socket's L1, L2, or L3 caches. Available PDIST c… 232 …on": "Counts demand data reads that were not supplied by the local socket's L1, L2, or L3 caches.", 238 …nd data reads that were not supplied by the local socket's L1, L2, or L3 caches. Available PDIST c… 287 …xclusive ownership (PREFETCHW) that were not supplied by the local socket's L1, L2, or L3 caches.", 293 …p (PREFETCHW) that were not supplied by the local socket's L1, L2, or L3 caches. Available PDIST c… 320 … "Counts hardware prefetches to the L3 only that missed the local socket's L1, L2, and L3 caches.", 326 … prefetches to the L3 only that missed the local socket's L1, L2, and L3 caches. Available PDIST c… 331 …o the L3 only that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline … 337 …o the L3 only that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline … [all …]
/linux/tools/perf/pmu-events/arch/x86/graniterapids/
H A D	cache.json	504 …oad instructions with remote cxl mem as the data source where the data request missed all caches.", 638 …load instructions with local cxl mem as the data source where the data request missed all caches.", 676 … cache prefetches that hit in the L3 or were snooped from another core's caches on the same socket… 682 … cache prefetches that hit in the L3 or were snooped from another core's caches on the same socket… 687 …refetches that resulted in a snoop hit a modified line in another core's caches which forwarded th… 693 …refetches that resulted in a snoop hit a modified line in another core's caches which forwarded th… 720 …demand data reads that hit in the L3 or were snooped from another core's caches on the same socket… 726 …demand data reads that hit in the L3 or were snooped from another core's caches on the same socket… 731 …ata reads that resulted in a snoop hit a modified line in another core's caches which forwarded th… 737 …ata reads that resulted in a snoop hit a modified line in another core's caches which forwarded th… [all …]
H A D	memory.json	209 …1 instruction cache prefetches that were not supplied by the local socket's L1, L2, or L3 caches.", 215 …he prefetches that were not supplied by the local socket's L1, L2, or L3 caches. Available PDIST c… 242 …on": "Counts demand data reads that were not supplied by the local socket's L1, L2, or L3 caches.", 248 …nd data reads that were not supplied by the local socket's L1, L2, or L3 caches. Available PDIST c… 286 …xclusive ownership (PREFETCHW) that were not supplied by the local socket's L1, L2, or L3 caches.", 292 …p (PREFETCHW) that were not supplied by the local socket's L1, L2, or L3 caches. Available PDIST c… 308 … code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that we… 314 … code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that we… 319 …demands and prefetches to the core caches (L1 or L2) that were not supplied by the local socket's … 325 …demands and prefetches to the core caches (L1 or L2) that were not supplied by the local socket's … [all …]
/linux/tools/perf/pmu-events/arch/x86/icelakex/
H A D	cache.json	7 …as found unmodified in the (FE) Forward or Exclusive State in this cores caches cache. A single s… 16 …m this core's caches, after the data is forwarded back to the requestor, and indicating the data w… 25 …his core's caches without being forwarded back to the requestor. The line was in Forward, Shared o… 34 … to snoops indicating that the data was not found (IHitI) in this core's caches. A single snoop re… 473 …l(R) Optane(TM) DC persistent memory as the data source where the data request missed all caches.", 563 …l(R) Optane(TM) DC persistent memory as the data source where the data request missed all caches.", 583 … cache prefetches that hit in the L3 or were snooped from another core's caches on the same socket… 593 …refetches that resulted in a snoop hit a modified line in another core's caches which forwarded th… 603 …d line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket whe… 613 …d line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket whe… [all …]
H A D	memory.json	127 …1 instruction cache prefetches that were not supplied by the local socket's L1, L2, or L3 caches.", 137 …he prefetches that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline … 177 …on": "Counts demand data reads that were not supplied by the local socket's L1, L2, or L3 caches.", 187 …nd data reads that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline … 237 …xclusive ownership (PREFETCHW) that were not supplied by the local socket's L1, L2, or L3 caches.", 247 …p (PREFETCHW) that were not supplied by the local socket's L1, L2, or L3 caches and were supplied … 287 … prefetches (except PREFETCHW) that were not supplied by the local socket's L1, L2, or L3 caches.", 297 …pt PREFETCHW) that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline … 317 … "Counts hardware prefetches to the L3 only that missed the local socket's L1, L2, and L3 caches.", 327 …o the L3 only that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline … [all …]
/linux/tools/perf/pmu-events/arch/arm64/arm/neoverse-n1/
H A D	l2_cache.json	4 …ata and instruction accesses. Accesses are for misses in the first level caches or translation res… 8 …or data and instruction accesses. Accesses are for misses in the level 1 caches or translation res… 20 …or data and instruction accesses, accesses are for misses in the level 1 caches or translation res… 24 …or data and instruction accesses, accesses are for misses in the level 1 caches or translation res… 28 …or data and instruction accesses, accesses are for misses in the level 1 caches or translation res… 32 …or data and instruction accesses, accesses are for misses in the level 1 caches or translation res…
H A D	l1d_cache.json	`8 …om any load/store operations. Atomic operations that resolve in the CPUs caches (near atomic opera… 16 …from any load operation. Atomic load operations that resolve in the CPUs caches counts as both a w… 20 …al address) instruction. Near atomic operations that resolve in the CPUs caches count as a write a… 32 …: "Counts level 1 data cache refills where the cache line data came from caches inside the immedia…`
/linux/tools/perf/pmu-events/arch/arm64/arm/neoverse-v1/
H A D	l2_cache.json	4 …ata and instruction accesses. Accesses are for misses in the first level caches or translation res… 8 …or data and instruction accesses. Accesses are for misses in the level 1 caches or translation res… 20 …or data and instruction accesses, accesses are for misses in the level 1 caches or translation res… 24 …or data and instruction accesses, accesses are for misses in the level 1 caches or translation res… 28 …or data and instruction accesses, accesses are for misses in the level 1 caches or translation res… 32 …or data and instruction accesses, accesses are for misses in the level 1 caches or translation res…
H A D	l1d_cache.json	`8 …om any load/store operations. Atomic operations that resolve in the CPUs caches (near atomic opera… 20 …from any load operation. Atomic load operations that resolve in the CPUs caches counts as both a w… 24 …al address) instruction. Near atomic operations that resolve in the CPUs caches count as a write a… 36 …: "Counts level 1 data cache refills where the cache line data came from caches inside the immedia…`
/linux/drivers/media/pci/intel/ipu6/
H A D	ipu6.h	`146 * used to fill the L1 and L2 caches with the trash buffer translations. ZLW 148 * advance to the L1 and L2 caches without triggering any memory operations. 156 * As we need to clear the caches and 8MB being the biggest cache size, we need 177 * table caches. Both these L1 and L2 caches are divided into multiple sections 178 * called streams. There is maximum 16 streams for both caches. Each of these 181 * L1/L2 page table caches.`
/linux/Documentation/filesystems/
H A D	9p.rst	`136 cache=mode specifies a caching policy. By default, no caches are used. 142 0b00000000 all caches disabled, mmap disabled 143 0b00000001 file caches enabled 144 0b00000010 meta-data caches enabled 146 0b00001000 loose caches (no explicit consistency with server) 156 loose 0b00001111 (non-coherent file and meta-data caches) 164 IMPORTANT: loose caches (and by extension at the moment fscache) 240 /sys/fs/9p/caches. (applies only to cache=fscache)`
/linux/Documentation/filesystems/nfs/
H A D	rpc-cache.rst	`9 Caches subtitle 13 a wide variety of values to be caches. 15 There are a number of caches that are similar in structure though 17 of common code for managing these caches. 19 Examples of caches that are likely to be needed are: 105 includes it on a list of caches that will be regularly`
/linux/Documentation/block/
H A D	writeback_cache_control.rst	`9 write back caches. That means the devices signal I/O completion to the 52 For devices that do not support volatile write caches there is no driver 57 For devices with volatile write caches the driver needs to tell the block layer 58 that it supports flushing caches by setting the`
/linux/arch/mips/mm/
H A D	c-r4k.c	75 * separate caches). in r4k_op_needs_ipi() 387 * These caches are inclusive caches, that is, if something in local_r4k___flush_cache_all() 389 * in one of the primary caches. in local_r4k___flush_cache_all() 468 * whole caches when vma is executable. 508 * only flush the primary caches but R1x000 behave sane ... in local_r4k_flush_cache_mm() 510 * caches, so we can bail out early. in local_r4k_flush_cache_mm() 770 * Either no secondary cache or the available caches don't have the in r4k_dma_cache_wback_inv() 771 * subset property so we have to flush the primary caches in r4k_dma_cache_wback_inv() 874 * Aliases only affect the primary caches so don't bother with in local_r4k_flush_kernel_vmap_range_index() 875 * S-caches or T-caches. in local_r4k_flush_kernel_vmap_range_index() [all …]
/linux/tools/perf/pmu-events/arch/arm64/fujitsu/monaka/
H A D	l2_cache.json	`90 …cess in the Level 1 data and Level 2 caches, causing a coherence access to outside of the Level 1 … 118 …t misses in the Level 1 data and Level 2 caches, causing an access to outside of the Level 1 and L…`
/linux/arch/openrisc/
H A D	Kconfig	`90 bool "Have write through data caches" 93 Select this if your implementation features write through data caches. 95 caches at relevant times. Most OpenRISC implementations support write- 96 through data caches.`
/linux/include/linux/
H A D	kvm_types.h	`87 * Memory caches are used to preallocate memory ahead of various MMU flows, 90 * holding MMU locks. Note, these caches act more like prefetch buffers than 91 * classical caches, i.e. objects are not returned to the cache on being freed.`
/linux/arch/mips/kernel/
H A D	bmips_5xxx_init.S	`300 * Description: Enable I and D caches, initialize I and D-caches, also set 323 * Description: Enable I and D caches, and initialize I and D-caches 344 /* Enable Caches before Clearing. If the caches are disabled 715 * Description: Enable I and D caches, and initialize I and D-caches`
/linux/arch/arm64/kernel/
H A D	cacheinfo.c	`51 /* Separate instruction and data caches / in detect_cache_level() 86 some external caches not specified in CLIDR_EL1 in init_cache_level() 88 * only unified external caches are considered here in init_cache_level()`
/linux/tools/cgroup/
H A D	memcg_slabinfo.py	`183 caches = {} 202 caches[addr] = cache 214 for addr in caches: 216 cache_show(caches[addr], cfg, stats[addr])`
/linux/arch/powerpc/platforms/52xx/
H A D	lite5200_sleep.S	`74 /* flush caches [destroys r3, r4] / 95 / disable I and D caches / 231 / invalidate caches / 234 mtspr SPRN_HID0, r5 / invalidate caches / 239 / enable caches / 241 mtspr SPRN_HID0, r10 / restore (enable caches, DPM) */`
/linux/drivers/infiniband/hw/hfi1/
H A D	user_pages.c	`20 * This function should be used in the implementation of buffer caches. 24 * cache size. Use of this function is especially important for caches 52 * caches. This fraction is then equally distributed among all in hfi1_can_pin_pages()`

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