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/linux/tools/perf/pmu-events/arch/x86/emeraldrapids/
H A D	cache.json	7 "PublicDescription": "Counts responses to snoops indicating the line will now be (I)nvalidated: removed from this core's cache, after the data is forwarded back to the requestor and indicating the data was found unmodified in the (FE) Forward or Exclusive State in this cores caches cache. A single snoop response from the core counts on all hyperthreads of the core.", 16 "PublicDescription": "Counts responses to snoops indicating the line will now be (I)nvalidated: removed from this core's caches, after the data is forwarded back to the requestor, and indicating the data was found modified(M) in this cores caches cache (aka HitM response). A single snoop response from the core counts on all hyperthreads of the core.", 25 "PublicDescription": "Counts responses to snoops indicating the line will now be (I)nvalidated in this core's caches without forwarded back to the requestor. The line was in Forward, Shared or Exclusive (FSE) state in this cores caches. A single snoop response from the core counts on all hyperthreads of the core.", 34 "PublicDescription": "Counts responses to snoops indicating that the data was not found (IHitI) in this core's caches. A single snoop response from the core counts on all hyperthreads of the Core.", 676 "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit in the L3 or were snooped from another core's caches on the same socket.", 682 "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit in the L3 or were snooped from another core's caches on the same socket. Available PDIST counters: 0", 687 "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that resulted in a snoop hit a modified line in another core's caches which forwarded the data.", 693 "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that resulted in a snoop hit a modified line in another core's caches whic [all...]
H A D	memory.json	188 …1 instruction cache prefetches that were not supplied by the local socket's L1, L2, or L3 caches.", 194 …he prefetches that were not supplied by the local socket's L1, L2, or L3 caches. Available PDIST c… 232 …on": "Counts demand data reads that were not supplied by the local socket's L1, L2, or L3 caches.", 238 …nd data reads that were not supplied by the local socket's L1, L2, or L3 caches. Available PDIST c… 287 …xclusive ownership (PREFETCHW) that were not supplied by the local socket's L1, L2, or L3 caches.", 293 …p (PREFETCHW) that were not supplied by the local socket's L1, L2, or L3 caches. Available PDIST c… 320 … "Counts hardware prefetches to the L3 only that missed the local socket's L1, L2, and L3 caches.", 326 … prefetches to the L3 only that missed the local socket's L1, L2, and L3 caches. Available PDIST c… 331 …o the L3 only that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline … 337 …o the L3 only that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline … [all …]
/linux/tools/perf/pmu-events/arch/x86/sapphirerapids/
H A D	cache.json	7 "PublicDescription": "Counts responses to snoops indicating the line will now be (I)nvalidated: removed from this core's cache, after the data is forwarded back to the requestor and indicating the data was found unmodified in the (FE) Forward or Exclusive State in this cores caches cache. A single snoop response from the core counts on all hyperthreads of the core.", 16 "PublicDescription": "Counts responses to snoops indicating the line will now be (I)nvalidated: removed from this core's caches, after the data is forwarded back to the requestor, and indicating the data was found modified(M) in this cores caches cache (aka HitM response). A single snoop response from the core counts on all hyperthreads of the core.", 25 "PublicDescription": "Counts responses to snoops indicating the line will now be (I)nvalidated in this core's caches without forwarded back to the requestor. The line was in Forward, Shared or Exclusive (FSE) state in this cores caches. A single snoop response from the core counts on all hyperthreads of the core.", 34 "PublicDescription": "Counts responses to snoops indicating that the data was not found (IHitI) in this core's caches. A single snoop response from the core counts on all hyperthreads of the Core.", 568 "BriefDescription": "Retired load instructions with remote Intel(R) Optane(TM) DC persistent memory as the data source where the data request missed all caches.", 657 "BriefDescription": "Retired load instructions with local Intel(R) Optane(TM) DC persistent memory as the data source where the data request missed all caches.", 695 "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit in the L3 or were snooped from another core's caches on the same socket.", 701 "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit in the L3 or were snooped from another core's caches o [all...]
H A D	memory.json	188 …1 instruction cache prefetches that were not supplied by the local socket's L1, L2, or L3 caches.", 194 …he prefetches that were not supplied by the local socket's L1, L2, or L3 caches. Available PDIST c… 232 …on": "Counts demand data reads that were not supplied by the local socket's L1, L2, or L3 caches.", 238 …nd data reads that were not supplied by the local socket's L1, L2, or L3 caches. Available PDIST c… 287 …xclusive ownership (PREFETCHW) that were not supplied by the local socket's L1, L2, or L3 caches.", 293 …p (PREFETCHW) that were not supplied by the local socket's L1, L2, or L3 caches. Available PDIST c… 320 … "Counts hardware prefetches to the L3 only that missed the local socket's L1, L2, and L3 caches.", 326 … prefetches to the L3 only that missed the local socket's L1, L2, and L3 caches. Available PDIST c… 331 …o the L3 only that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline … 337 …o the L3 only that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline … [all …]
/linux/tools/perf/pmu-events/arch/x86/graniterapids/
H A D	cache.json	513 "BriefDescription": "Retired load instructions with remote cxl mem as the data source where the data request missed all caches.", 647 "BriefDescription": "Retired load instructions with local cxl mem as the data source where the data request missed all caches.", 685 "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit in the L3 or were snooped from another core's caches on the same socket.", 691 "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit in the L3 or were snooped from another core's caches on the same socket. Available PDIST counters: 0", 696 "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that resulted in a snoop hit a modified line in another core's caches which forwarded the data.", 702 "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that resulted in a snoop hit a modified line in another core's caches which forwarded the data. Available PDIST counters: 0", 729 "BriefDescription": "Counts demand data reads that hit in the L3 or were snooped from another core's caches on the same socket.", 735 "PublicDescription": "Counts demand data reads that hit in the L3 or were snooped from another core's caches on the same socket. Available PDIST counters: 0", 740 "BriefDescription": "Counts demand data reads that resulted in a snoop hit a modified line in another core's caches which forwarded the data.", 746 "PublicDescription": "Counts demand data reads that resulted in a snoop hit a modified line in another core's caches whic [all...]
H A D	memory.json	209 …1 instruction cache prefetches that were not supplied by the local socket's L1, L2, or L3 caches.", 215 …he prefetches that were not supplied by the local socket's L1, L2, or L3 caches. Available PDIST c… 242 …on": "Counts demand data reads that were not supplied by the local socket's L1, L2, or L3 caches.", 248 …nd data reads that were not supplied by the local socket's L1, L2, or L3 caches. Available PDIST c… 286 …xclusive ownership (PREFETCHW) that were not supplied by the local socket's L1, L2, or L3 caches.", 292 …p (PREFETCHW) that were not supplied by the local socket's L1, L2, or L3 caches. Available PDIST c… 308 … code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that we… 314 … code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that we… 319 …demands and prefetches to the core caches (L1 or L2) that were not supplied by the local socket's … 325 …demands and prefetches to the core caches (L1 or L2) that were not supplied by the local socket's … [all …]
/linux/tools/perf/pmu-events/arch/x86/icelakex/
H A D	cache.json	7 …as found unmodified in the (FE) Forward or Exclusive State in this cores caches cache. A single s… 16 …m this core's caches, after the data is forwarded back to the requestor, and indicating the data w… 25 …his core's caches without being forwarded back to the requestor. The line was in Forward, Shared o… 34 … to snoops indicating that the data was not found (IHitI) in this core's caches. A single snoop re… 473 …l(R) Optane(TM) DC persistent memory as the data source where the data request missed all caches.", 563 …l(R) Optane(TM) DC persistent memory as the data source where the data request missed all caches.", 583 … cache prefetches that hit in the L3 or were snooped from another core's caches on the same socket… 593 …refetches that resulted in a snoop hit a modified line in another core's caches which forwarded th… 603 …d line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket whe… 613 …d line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket whe… [all …]
H A D	memory.json	127 …1 instruction cache prefetches that were not supplied by the local socket's L1, L2, or L3 caches.", 137 …he prefetches that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline … 177 …on": "Counts demand data reads that were not supplied by the local socket's L1, L2, or L3 caches.", 187 …nd data reads that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline … 237 …xclusive ownership (PREFETCHW) that were not supplied by the local socket's L1, L2, or L3 caches.", 247 …p (PREFETCHW) that were not supplied by the local socket's L1, L2, or L3 caches and were supplied … 287 … prefetches (except PREFETCHW) that were not supplied by the local socket's L1, L2, or L3 caches.", 297 …pt PREFETCHW) that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline … 317 … "Counts hardware prefetches to the L3 only that missed the local socket's L1, L2, and L3 caches.", 327 …o the L3 only that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline … [all …]
/linux/tools/perf/pmu-events/arch/arm64/arm/neoverse-n1/
H A D	l2_cache.json	4 …ata and instruction accesses. Accesses are for misses in the first level caches or translation res… 8 …or data and instruction accesses. Accesses are for misses in the level 1 caches or translation res… 20 …or data and instruction accesses, accesses are for misses in the level 1 caches or translation res… 24 …or data and instruction accesses, accesses are for misses in the level 1 caches or translation res… 28 …or data and instruction accesses, accesses are for misses in the level 1 caches or translation res… 32 …or data and instruction accesses, accesses are for misses in the level 1 caches or translation res…
H A D	l1d_cache.json	`8 …om any load/store operations. Atomic operations that resolve in the CPUs caches (near atomic opera… 16 …from any load operation. Atomic load operations that resolve in the CPUs caches counts as both a w… 20 …al address) instruction. Near atomic operations that resolve in the CPUs caches count as a write a… 32 …: "Counts level 1 data cache refills where the cache line data came from caches inside the immedia…`
/linux/tools/perf/pmu-events/arch/arm64/arm/neoverse-v1/
H A D	l2_cache.json	4 …ata and instruction accesses. Accesses are for misses in the first level caches or translation res… 8 …or data and instruction accesses. Accesses are for misses in the level 1 caches or translation res… 20 …or data and instruction accesses, accesses are for misses in the level 1 caches or translation res… 24 …or data and instruction accesses, accesses are for misses in the level 1 caches or translation res… 28 …or data and instruction accesses, accesses are for misses in the level 1 caches or translation res… 32 …or data and instruction accesses, accesses are for misses in the level 1 caches or translation res…
H A D	l1d_cache.json	`8 …om any load/store operations. Atomic operations that resolve in the CPUs caches (near atomic opera… 20 …from any load operation. Atomic load operations that resolve in the CPUs caches counts as both a w… 24 …al address) instruction. Near atomic operations that resolve in the CPUs caches count as a write a… 36 …: "Counts level 1 data cache refills where the cache line data came from caches inside the immedia…`
/linux/drivers/media/pci/intel/ipu6/
H A D	ipu6.h	`146 * used to fill the L1 and L2 caches with the trash buffer translations. ZLW 148 * advance to the L1 and L2 caches without triggering any memory operations. 156 * As we need to clear the caches and 8MB being the biggest cache size, we need 177 * table caches. Both these L1 and L2 caches are divided into multiple sections 178 * called streams. There is maximum 16 streams for both caches. Each of these 181 * L1/L2 page table caches.`
/linux/Documentation/filesystems/nfs/
H A D	rpc-cache.rst	`9 Caches subtitle 13 a wide variety of values to be caches. 15 There are a number of caches that are similar in structure though 17 of common code for managing these caches. 19 Examples of caches that are likely to be needed are: 105 includes it on a list of caches that will be regularly`
/linux/Documentation/block/
H A D	writeback_cache_control.rst	`9 write back caches. That means the devices signal I/O completion to the 52 For devices that do not support volatile write caches there is no driver 57 For devices with volatile write caches the driver needs to tell the block layer 58 that it supports flushing caches by setting the`
/linux/tools/perf/pmu-events/arch/arm64/fujitsu/monaka/
H A D	l2_cache.json	`90 …cess in the Level 1 data and Level 2 caches, causing a coherence access to outside of the Level 1 … 118 …t misses in the Level 1 data and Level 2 caches, causing an access to outside of the Level 1 and L…`
/linux/arch/mips/kernel/
H A D	bmips_5xxx_init.S	`300 * Description: Enable I and D caches, initialize I and D-caches, also set 323 * Description: Enable I and D caches, and initialize I and D-caches 344 /* Enable Caches before Clearing. If the caches are disabled 715 * Description: Enable I and D caches, and initialize I and D-caches`
/linux/arch/arm64/kernel/
H A D	cacheinfo.c	`51 /* Separate instruction and data caches / in detect_cache_level() 86 some external caches not specified in CLIDR_EL1 in init_cache_level() 88 * only unified external caches are considered here in init_cache_level()`
/linux/tools/cgroup/
H A D	memcg_slabinfo.py	`183 caches = {} 202 caches[addr] = cache 214 for addr in caches: 216 cache_show(caches[addr], cfg, stats[addr])`
/linux/drivers/infiniband/hw/hfi1/
H A D	user_pages.c	`20 * This function should be used in the implementation of buffer caches. 24 * cache size. Use of this function is especially important for caches 52 * caches. This fraction is then equally distributed among all in hfi1_can_pin_pages()`
/linux/kernel/bpf/
H A D	memalloc.c	566 ma->caches = pcc; in bpf_mem_alloc_init() 578 ma->caches = pcc; in bpf_mem_alloc_percpu_init() 600 pcc = ma->caches; in bpf_mem_alloc_percpu_unit_init() 663 if (ma->caches) { in check_leaked_objs() 665 cc = per_cpu_ptr(ma->caches, cpu); in check_leaked_objs() 681 free_percpu(ma->caches); in free_mem_alloc_no_barrier() 683 ma->caches = NULL; in free_mem_alloc_no_barrier() 755 if (ma->caches) { in bpf_mem_alloc_destroy() 758 cc = per_cpu_ptr(ma->caches, cpu); in bpf_mem_alloc_destroy() 897 ret = unit_alloc(this_cpu_ptr(ma->caches)->cache + idx); in bpf_mem_alloc() [all …]
/linux/arch/powerpc/platforms/52xx/
H A D	lite5200_sleep.S	`74 /* flush caches [destroys r3, r4] / 95 / disable I and D caches / 231 / invalidate caches / 234 mtspr SPRN_HID0, r5 / invalidate caches / 239 / enable caches / 241 mtspr SPRN_HID0, r10 / restore (enable caches, DPM) */`
/linux/arch/arm/mm/
H A D	proc-sa1100.S	`52 * - Clean and turn off caches. 59 mcr p15, 0, r0, c1, c0, 0 @ disable caches 76 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 124 * Clean the specified entry of any caches such that the MMU 208 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4`
/linux/mm/
H A D	slab.h	261 struct list_head list; /* List of slab caches / 298 bootstrap_sheaf temporarily during init, or permanently for the boot caches 299 * and caches with debugging enabled, or all caches with CONFIG_SLUB_TINY. This 386 * have the problem that the structures used for managing slab caches are 387 * allocated from slab caches themselves. 392 UP, /* Slab caches usable but not all extras yet / 401 / The list of all slab caches on the system / 582 Return true if KMALLOC_NORMAL caches may need obj_exts arrays. 584 * Memory allocation profiling requires obj_exts for all caches. 585 * Memcg usually doesn't need them for normal kmalloc caches, but kmalloc types
/linux/arch/powerpc/boot/
H A D	gamecube-head.S	`14 * - if the data and instruction caches are enabled or not 17 * We enable the caches if not already enabled, enable the MMU with an 75 /* enable and invalidate the caches if not already enabled */`

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