xref: /linux/tools/perf/pmu-events/arch/arm64/fujitsu/monaka/l2_cache.json (revision f4f346c3465949ebba80c6cc52cd8d2eeaa545fd) 
1[
2    {
3        "ArchStdEvent": "L2D_CACHE",
4        "BriefDescription": "This event counts operations that cause a cache access to the L2 cache. See L2D_CACHE of ARMv9 Reference Manual for more information."
5    },
6    {
7        "ArchStdEvent": "L2D_CACHE_REFILL",
8        "BriefDescription": "This event counts operations that cause a refill of the L2 cache. See L2D_CACHE_REFILL of ARMv9 Reference Manual for more information."
9    },
10    {
11        "ArchStdEvent": "L2D_CACHE_WB",
12        "BriefDescription": "This event counts every write-back of data from the L2 cache caused by L2 replace, non-temporal-store and DC ZVA."
13    },
14    {
15        "ArchStdEvent": "L2I_TLB_REFILL",
16        "BriefDescription": "This event counts operations that cause a TLB refill of the L2I TLB. See L2I_TLB_REFILL of ARMv9 Reference Manual for more information."
17    },
18    {
19        "ArchStdEvent": "L2I_TLB",
20        "BriefDescription": "This event counts operations that cause a TLB access to the L2I TLB. See L2I_TLB of ARMv9 Reference Manual for more information."
21    },
22    {
23        "ArchStdEvent": "L2D_CACHE_RD",
24        "BriefDescription": "This event counts L2D_CACHE caused by read access."
25    },
26    {
27        "ArchStdEvent": "L2D_CACHE_WR",
28        "BriefDescription": "This event counts L2D_CACHE caused by write access."
29    },
30    {
31        "ArchStdEvent": "L2D_CACHE_REFILL_RD",
32        "BriefDescription": "This event counts L2D_CACHE_REFILL caused by read access."
33    },
34    {
35        "ArchStdEvent": "L2D_CACHE_REFILL_WR",
36        "BriefDescription": "This event counts L2D_CACHE_REFILL caused by write access."
37    },
38    {
39        "ArchStdEvent": "L2D_CACHE_WB_VICTIM",
40        "BriefDescription": "This event counts every write-back of data from the L2 cache caused by L2 replace."
41    },
42    {
43        "EventCode": "0x0300",
44        "EventName": "L2D_CACHE_DM",
45        "BriefDescription": "This event counts L2D_CACHE caused by demand access."
46    },
47    {
48        "EventCode": "0x0301",
49        "EventName": "L2D_CACHE_DM_RD",
50        "BriefDescription": "This event counts L2D_CACHE caused by demand read access."
51    },
52    {
53        "EventCode": "0x0302",
54        "EventName": "L2D_CACHE_DM_WR",
55        "BriefDescription": "This event counts L2D_CACHE caused by demand write access."
56    },
57    {
58        "EventCode": "0x0305",
59        "EventName": "L2D_CACHE_HWPRF_ADJACENT",
60        "BriefDescription": "This event counts L2D_CACHE caused by hardware adjacent prefetch."
61    },
62    {
63        "EventCode": "0x0308",
64        "EventName": "L2D_CACHE_REFILL_DM",
65        "BriefDescription": "This event counts L2D_CACHE_REFILL caused by demand access."
66    },
67    {
68        "EventCode": "0x0309",
69        "EventName": "L2D_CACHE_REFILL_DM_RD",
70        "BriefDescription": "This event counts L2D_CACHE_REFILL caused by demand read access."
71    },
72    {
73        "EventCode": "0x030A",
74        "EventName": "L2D_CACHE_REFILL_DM_WR",
75        "BriefDescription": "This event counts L2D_CACHE_REFILL caused by demand write access."
76    },
77    {
78        "EventCode": "0x030B",
79        "EventName": "L2D_CACHE_REFILL_DM_WR_EXCL",
80        "BriefDescription": "This event counts L2D_CACHE_REFILL caused by demand write exclusive access."
81    },
82    {
83        "EventCode": "0x030C",
84        "EventName": "L2D_CACHE_REFILL_DM_WR_ATOM",
85        "BriefDescription": "This event counts L2D_CACHE_REFILL caused by demand write atomic access."
86    },
87    {
88        "EventCode": "0x030D",
89        "EventName": "L2D_CACHE_BTC",
90        "BriefDescription": "This event counts demand access that hits cache line with shared status and requests exclusive access in the Level 1 data and Level 2 caches, causing a coherence access to outside of the Level 1 and Level 2 caches of this PE."
91    },
92    {
93        "EventCode": "0x03B0",
94        "EventName": "L2D_CACHE_WB_VICTIM_CLEAN",
95        "BriefDescription": "This event counts every write-back of data from the L2 cache caused by L2 replace where the data is clean. In this case, the data will usually be written to L3 cache."
96    },
97    {
98        "EventCode": "0x03B1",
99        "EventName": "L2D_CACHE_WB_NT",
100        "BriefDescription": "This event counts every write-back of data from the L2 cache caused by non-temporal-store."
101    },
102    {
103        "EventCode": "0x03B2",
104        "EventName": "L2D_CACHE_WB_DCZVA",
105        "BriefDescription": "This event counts every write-back of data from the L2 cache caused by DC ZVA."
106    },
107    {
108        "EventCode": "0x03B3",
109        "EventName": "L2D_CACHE_FB",
110        "BriefDescription": "This event counts every flush-back (drop) of data from the L2 cache."
111    },
112    {
113        "ArchStdEvent": "L2D_CACHE_LMISS_RD",
114        "BriefDescription": "This event counts operations that cause a refill of the L2 cache that incurs additional latency."
115    },
116    {
117        "ArchStdEvent": "L2D_CACHE_MISS",
118        "BriefDescription": "This event counts demand access that misses in the Level 1 data and Level 2 caches, causing an access to outside of the Level 1 and Level 2 caches of this PE."
119    },
120    {
121        "ArchStdEvent": "L2D_CACHE_HWPRF",
122        "BriefDescription": "This event counts L2D_CACHE caused by hardware prefetch."
123    },
124    {
125        "ArchStdEvent": "L2D_CACHE_REFILL_HWPRF",
126        "BriefDescription": "This event counts L2D_CACHE_REFILL caused by hardware prefetch."
127    },
128    {
129        "ArchStdEvent": "L2D_CACHE_HIT_RD",
130        "BriefDescription": "This event counts demand read counted by L2D_CACHE_RD that hits in the Level 2 cache."
131    },
132    {
133        "ArchStdEvent": "L2D_CACHE_HIT_WR",
134        "BriefDescription": "This event counts demand write counted by L2D_CACHE_WR that hits in the Level 2 cache."
135    },
136    {
137        "ArchStdEvent": "L2D_CACHE_HIT",
138        "BriefDescription": "This event counts access counted by L2D_CACHE that hits in the Level 2 cache."
139    },
140    {
141        "ArchStdEvent": "L2D_LFB_HIT_RD",
142        "BriefDescription": "This event counts demand access counted by L2D_CACHE_HIT_RD that hits a recently fetched line in the Level 2 cache."
143    },
144    {
145        "ArchStdEvent": "L2D_LFB_HIT_WR",
146        "BriefDescription": "This event counts demand access counted by L2D_CACHE_HIT_WR that hits a recently fetched line in the Level 2 cache."
147    },
148    {
149        "ArchStdEvent": "L2D_CACHE_PRF",
150        "BriefDescription": "This event counts L2D_CACHE caused by hardware prefetch or software prefetch."
151    },
152    {
153        "ArchStdEvent": "L2D_CACHE_REFILL_PRF",
154        "BriefDescription": "This event counts L2D_CACHE_REFILL caused by hardware prefetch or software prefetch."
155    },
156    {
157        "ArchStdEvent": "L2D_CACHE_REFILL_PERCYC",
158        "BriefDescription": "This counter counts by the number of cache refills counted by L2D_CACHE_REFILL in progress on each Processor cycle."
159    }
160]
161