| /freebsd/share/man/man4/ |
| H A D | ng_ppp.4 | 1 .\" Copyright (c) 1996-1999 Whistle Communications, Inc.
19 .\" MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
51 user-land daemon).
54 user-land implementations.
56 multi-link PPP, Van Jacobson compression, PPP compression, PPP
58 A single PPP node corresponds to one PPP multi-link bundle.
66 .Dv bypass
71 Typically this node is connected to a user-land daemon via a
84 .Dv bypass
94 These device-independent hooks transmit and receive full PPP
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| H A D | ix.4 | 1 .\" Copyright (c) 2001-2008, Intel Corporation
42 .Bd -ragged -offset indent
50 .Bd -literal -offset indent
79 .Bl -bullet -compact
87 Intel(R) Ethernet X540 Bypass
91 Intel(R) Ethernet X520 Bypass (82599)
101 .Bl -tag -width "hw.ix.allow_unsupported_sfp"
109 Enable Message Signalled Interrupts (MSI-X).
111 Allow unsupported small form-factor pluggable
116 Enable Flow Director.
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| /freebsd/sys/dev/mii/ |
| H A D | nsphyterreg.h | 3 /*-
4 * SPDX-License-Identifier: BSD-2-Clause
65 #define PHYSTS_MP_DESCRLK 0x0200 /* de-scrambler lock */
75 #define MIPSCR_INTEN 0x0002 /* interrupt enable */
85 #define MIPGSR_MSK_ANC 0x0800 /* mask auto-neg complete event */
96 #define PCSR_SINGLE_SD 0x8000 /* single-ended SD mode */
112 #define PCSR_MP_BYP_4B5B 0x1000 /* bypass encoder */
114 #define PCSR_MP_TQ_EN 0x0400 /* enable True Quiet mode */
117 #define PCSR_MP_NRZI_BYPASS 0x0004 /* NRZI bypass enabled */
120 #define MII_NSPHYTER_LBR 0x17 /* loopback and bypass */
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| H A D | ciphyreg.h | 1 /*-
2 * SPDX-License-Identifier: BSD-4-Clause
18 * 4. Neither the name of the author nor the names of any co-contributors
52 #define CIPHY_BMCR_CTEST 0x0080 /* Collision test enable */
137 #define CIPHY_1000CTL_MSE 0x1000 /* Master/Slave manual enable */
159 #define CIPHY_EXTSTS_X_FD_CAP 0x8000 /* 1000base-X FD capable */
160 #define CIPHY_EXTSTS_X_HD_CAP 0x4000 /* 1000base-X HD capable */
161 #define CIPHY_EXTSTS_T_FD_CAP 0x2000 /* 1000base-T FD capable */
162 #define CIPHY_EXTSTS_T_HD_CAP 0x1000 /* 1000base-T HD capable */
171 /* Vendor-specific PHY registers */
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| H A D | amphyreg.h | 1 /*-
2 * SPDX-License-Identifier: BSD-4-Clause
18 * 4. Neither the name of the author nor the names of any co-contributors
43 #define DSCR_BP4B5B 0x8000 /* Bypass 4B5B encoding */
44 #define DSCR_BPSCR 0x4000 /* Bypass scrambler */
45 #define DSCR_BPALIGN 0x2000 /* Bypass symbol alignment */
77 #define T10CSRSCR_LPEN 0x4000 /* Link pulse enable */
78 #define T10CSRSCR_HBE 0x2000 /* Heartbeat enable */
79 #define T10CSRSCR_JABEN 0x0800 /* Jabber enable */
80 #define T10CSRSCR_SER 0x0400 /* Serial mode enable */
|
| H A D | bmtphyreg.h | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
43 #define AUX_CTL_4B5B_BYPASS 0x0400 /* bypass 4b5b encoder */
44 #define AUX_CTL_SCR_BYPASS 0x0200 /* bypass scrambler */
45 #define AUX_CTL_NRZI_BYPASS 0x0100 /* bypass NRZI encoder */
46 #define AUX_CTL_RXALIGN_BYPASS 0x0080 /* bypass rx symbol alignment */
48 #define AUX_CTL_FEF_EN 0x0020 /* far-end fault enable */
51 #define AUX_STS_FX_MODE 0x0400 /* 100base-FX mode (strap pin) */
63 #define MII_BMTPHY_RXERROR_CTR 0x12 /* 100base-X Rx error counter */
66 #define MII_BMTPHY_FCS_CTR 0x13 /* 100base-X false carrier counter */
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| H A D | nsphyreg.h | 3 /*-
4 * SPDX-License-Identifier: BSD-2-Clause
50 #define MII_NSPHY_PCR 0x17 /* PCS sub-layer configuration */
69 * 0 Normal LED1 operation - 10baseTX and 100baseTX transmission
74 * 1 LED4 output configured to indicate full-duplex in both
78 * mode and full-duplex in 100baseTX mode.
81 #define MII_NSPHY_LBREMR 0x18 /* Loopback, bypass, error mask */
82 #define LBREMR_BADSSDEN 0x8000 /* enable bad SSD detection */
83 #define LBREMR_BP4B5B 0x4000 /* bypass 4b/5b encoding */
84 #define LBREMR_BPSCR 0x2000 /* bypass scrambler */
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| H A D | brgphyreg.h | 1 /*-
2 * SPDX-License-Identifier: BSD-4-Clause
18 * 4. Neither the name of the author nor the names of any co-contributors
51 #define BRGPHY_BMCR_CTEST 0x0080 /* Collision test enable */
97 #define BRGPHY_1000CTL_MSE 0x1000 /* Master/Slave enable */
113 #define BRGPHY_EXTSTS_X_FD_CAP 0x8000 /* 1000base-X FD capable */
114 #define BRGPHY_EXTSTS_X_HD_CAP 0x4000 /* 1000base-X HD capable */
115 #define BRGPHY_EXTSTS_T_FD_CAP 0x2000 /* 1000base-T FD capable */
116 #define BRGPHY_EXTSTS_T_HD_CAP 0x1000 /* 1000base-T HD capable */
119 #define BRGPHY_PHY_EXTCTL_MAC_PHY 0x8000 /* 10BIT/GMI-interface */
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| /freebsd/sys/contrib/device-tree/Bindings/regulator/ |
| H A D | ti-abb-regulator.txt | 4 - compatible: Should be one of:
5 - "ti,abb-v1" for older SoCs like OMAP3
6 - "ti,abb-v2" for newer SoCs like OMAP4, OMAP5
7 - "ti,abb-v3" for a generic definition where setup and control registers are
9 - reg: Address and length of the register set for the device. It contains
10 the information of registers in the same order as described by reg-names
11 - reg-names: Should contain the reg names
12 - "base-address" - contains base address of ABB module (ti,abb-v1,ti,abb-v2)
13 - "control-address" - contains control register address of ABB module (ti,abb-v3)
14 - "setup-address" - contains setup register address of ABB module (ti,abb-v3)
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| H A D | regulator.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Liam Girdwood <lgirdwood@gmail.com>
11 - Mark Brown <broonie@kernel.org>
14 regulator-nam
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| /freebsd/sys/dev/smartpqi/ |
| H A D | smartpqi_features.c | 1 /*-
2 * Copyright 2016-2023 Microchip Technology, Inc. and/or its subsidiaries.
41 if (byte_index >= firmware_features->num_elements) { in pqi_is_firmware_feature_supported()
47 return (firmware_features->features_supported[byte_index] & in pqi_is_firmware_feature_supported()
66 (firmware_features->num_elements * 2); in pqi_is_firmware_feature_enabled()
89 firmware_features->num_elements; in pqi_request_firmware_feature()
92 firmware_features->features_supported[byte_index] |= in pqi_request_firmware_feature()
110 request.header.iu_length = sizeof(request) - PQI_REQUEST_HEADER_LENGTH; in pqi_config_table_update()
138 features_requested = firmware_features->features_supported + in pqi_enable_firmware_features()
139 firmware_features->num_elements; in pqi_enable_firmware_features()
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| /freebsd/sys/contrib/alpine-hal/ |
| H A D | al_hal_nb_regs.h | 1 /*-
10 found at http://www.gnu.org/licenses/gpl-2.0.html
101 /* [0x6c] Read-only that reflects CPU Cluster Local GIC base high address */
103 /* [0x70] Read-only that reflects CPU Cluster Local GIC base low address */
105 /* [0x74] Read-only that reflects the device's IOGIC base high address. */
107 /* [0x78] Read-only that reflects IOGIC base low address */
454 /* Enable broadcast of inner shareable transactions from CPUs.
460 /* Enable broadcast of outer shareable transactions from CPUs.
474 0 Enable the GIC CPU interface logic.
480 /* Value read in the Cluster ID Affinity Level-1 field, bits[15:8], of the Multiprocessor Affinity
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| /freebsd/sys/contrib/device-tree/Bindings/power/supply/ |
| H A D | bq25980.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Andrew Davis <afd@ti.com>
15 for use in high-power density portable electronics. These inductorless
20 - $ref: power-supply.yaml#
25 - ti,bq25980
26 - ti,bq25975
27 - ti,bq25960
32 ti,watchdog-timeout-ms:
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| /freebsd/sys/dev/ixgbe/ |
| H A D | ixgbe_dcb_82599.h | 2 SPDX-License-Identifier: BSD-3-Clause
4 Copyright (c) 2001-2020, Intel Corporation
40 * 1 WSP - Weighted Strict Priority
43 * 1 WRR - Weighted Round Robin
46 #define IXGBE_RTTDCS_BDPM 0x00400000 /* Bypass Data Pipe - must clear! */
47 #define IXGBE_RTTDCS_BPBFSM 0x00800000 /* Bypass PB Free Space - must
60 #define IXGBE_RTRPT4C_GSP 0x40000000 /* GSP enable bit */
61 #define IXGBE_RTRPT4C_LSP 0x80000000 /* LSP enable bit */
64 * buffers enable
67 * (RSS) enable
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| /freebsd/sys/contrib/device-tree/Bindings/clock/ti/ |
| H A D | dpll.txt | 4 register-mapped DPLL with usually two selectable input clocks
5 (reference clock and bypass clock), with digital phase locked
9 sub-types, which effectively result in slightly different setup
12 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
15 - compatible : shall be one of:
16 "ti,omap3-dpll-clock",
17 "ti,omap3-dpll-core-clock",
18 "ti,omap3-dpll-per-clock",
19 "ti,omap3-dpll-per-j-type-clock",
20 "ti,omap4-dpll-clock",
[all …]
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| H A D | apll.txt | 4 register-mapped APLL with usually two selectable input clocks
5 (reference clock and bypass clock), with analog phase locked
11 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
15 - compatible : shall be "ti,dra7-apll-clock" or "ti,omap2-apll-clock"
16 - #clock-cells : from common clock binding; shall be set to 0.
17 - clocks : link phandles of parent clocks (clk-ref and clk-bypass)
18 - reg : address and length of the register set for controlling the APLL.
20 "control" - contains the control register offset
21 "idlest" - contains the idlest register offset
22 "autoidle" - contains the autoidle register offset (OMAP2 only)
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| /freebsd/sbin/mount_nullfs/ |
| H A D | mount_nullfs.8 | 38 .Nd "mount a loopback file system sub-tree; demonstrate the use of a null file system layer"
43 .Ar mount-point
49 layer, duplicating a sub-tree of the file system
79 .Do null-node Dc Ns s
81 all lower-layer vnodes, not just over directory vnodes.
84 .Bl -tag -width indent
93 .Bl -tag -width nocache
96 Some lower-laye
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86.td | 1 //===-- X86.td - Target definition file for the Intel X86 --*- tablegen -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
14 // Get the target-independent interfaces which we are implementing...
18 //===----------------------------------------------------------------------===//
22 def Is64Bit : SubtargetFeature<"64bit-mode", "Is64Bit", "true",
23 "64-bit mode (x86_64)">;
24 def Is32Bit : SubtargetFeature<"32bit-mode", "Is32Bit", "true",
25 "32-bit mode (80386)">;
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| /freebsd/sys/contrib/device-tree/Bindings/sound/ |
| H A D | adi,max98396.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ryan Lee <ryans.lee@analog.com>
13 The MAX98396 is a mono Class-DG speaker amplifier with I/V sense.
21 - adi,max98396
22 - adi,max98397
27 avdd-supply:
30 dvdd-supply:
33 dvddio-supply:
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| /freebsd/sys/contrib/device-tree/src/arm/st/ |
| H A D | st-pincfg.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
14 /* Output enable */
29 /* User-frendly defines for Pin Direction */
44 * Bypass retime with optional delay parameter
46 #define BYPASS (0) macro
49 * single-edge data non inverted clock, retime data with clk
54 * single-edge data inverted clock, retime data with clk
59 * double-edge data, retime data with clk
68 * CLK0, CLK1 modes with non-inverted clock
|
| /freebsd/sys/dev/rtwn/rtl8821a/ |
| H A D | r21a_chan.c | 1 /*-
73 struct r12a_softc *rs = sc->sc_priv; in r21a_set_band_2ghz()
75 /* Enable CCK / OFDM. */ in r21a_set_band_2ghz()
85 if (rs->ext_lna_2g) { in r21a_set_band_2ghz()
92 /* Bypass 2.4 GHz external LNA. */ in r21a_set_band_2ghz()
111 struct r12a_softc *rs = sc->sc_priv; in r21a_set_band_5ghz()
119 if (rs->ext_lna_2g) { in r21a_set_band_5ghz()
120 /* Bypass 2.4 GHz external LNA. */ in r21a_set_band_5ghz()
133 device_printf(sc->sc_dev, in r21a_set_band_5ghz()
138 /* Enable OFDM. */ in r21a_set_band_5ghz()
|
| /freebsd/sys/dev/vnic/ |
| H A D | nic.h | 73 /* Receive channel configuration in TNS bypass mode
74 * Below is configuration in TNS bypass mode
75 * BGX0-LMAC0-CHAN0 - VNIC CHAN0
76 * BGX0-LMAC1-CHAN0 - VNIC CHAN16
78 * BGX1-LMAC0-CHAN0 - VNIC CHAN128
80 * BGX1-LMAC3-CHAN0 - VNIC CHAN174
87 /* TNS bypass mode: 1-1 mapping between VNIC and BGX:LMAC */
102 /* TNS bypass mode */
132 /* MSI-X interrupts */
178 boolean_t enable; member
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| /freebsd/sys/contrib/alpine-hal/eth/ |
| H A D | al_hal_an_lt_wrapper_regs.h | 1 /*-
10 found at http://www.gnu.org/licenses/gpl-2.0.html
135 /* bypass the AN/LT block */
137 /* bypass the AN/LT block */
152 * Default Auto-Negotiation Enable. If ‘1’, the auto-negotiation process will
153 * start after reset de-assertion. The application can also start the
154 * auto-negotiation process by writing the KXAN_CONTROL.an_enable bit with ‘1’.
176 * 0 - Select input from the SerDes
177 * 1 - Select register value from phy_los_in_def
187 * 1 - Select register value from phy_los_out_def
[all …]
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| /freebsd/sys/arm/broadcom/bcm2835/ |
| H A D | bcm2835_rng.c | 61 #define RNG_JCLK_BYP_DIV_CNT 0x0000ff00 /* Jitter clk bypass divider
64 #define RNG_JCLK_BYP_SRC 0x00000020 /* Jitter clk bypass source */
65 #define RNG_JCLK_BYP_SEL 0x00000010 /* Jitter clk bypass select */
67 #define RNG_RBGEN_BIT 0x00000001 /* Enable RNG bit */
153 {"broadcom,bcm2835-rng", (uintptr_t)&bcm2835_rng_conf},
154 {"brcm,bcm2835-rng", (uintptr_t)&bcm2835_rng_conf},
156 {"brcm,bcm2711-rng200", (uintptr_t)&bcm2838_rng_conf},
157 {"brcm,bcm2838-rng", (uintptr_t)&bcm2838_rng_conf},
158 {"brcm,bcm2838-rng200", (uintptr_t)&bcm2838_rng_conf},
159 {"brcm,bcm7211-rng", (uintptr_t)&bcm2838_rng_conf},
[all …]
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| /freebsd/sys/contrib/device-tree/Bindings/mfd/ |
| H A D | richtek,rt4831.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - ChiYuan Huang <cy_huang@richtek.com>
23 https://www.richtek.com/assets/product_file/RT4831A/DS4831A-05.pdf
33 enable-gpios:
35 GPIO to enable/disable the chip. It is optional.
40 $ref: /schemas/regulator/richtek,rt4831-regulator.yaml
43 $ref: /schemas/leds/backlight/richtek,rt4831-backlight.yaml
46 - compatible
[all …]
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