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/linux/drivers/gpu/drm/bridge/
H A Dsil-sii8620.h1 /* SPDX-License-Identifier: GPL-2.0-only */
9 * Copyright (C) 2013-2014 Silicon Image, Inc.
15 /* Vendor ID Low byte, default value: 0x01 */
18 /* Vendor ID High byte, default value: 0x00 */
21 /* Device ID Low byte, default value: 0x60 */
24 /* Device ID High byte, default value: 0x86 */
27 /* Device Revision, default value: 0x10 */
30 /* OTP DBYTE510, default value: 0x00 */
33 /* System Control #1, default value: 0x00 */
35 #define BIT_SYS_CTRL1_OTPVMUTEOVR_SET BIT(7)
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/linux/arch/mips/include/asm/octeon/
H A Dcvmx-fau.h7 * Copyright (c) 2003-2008 Cavium Networks
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
57 * bit will be set. Otherwise the value of the register before
62 int64_t value:63; member
67 * bit will be set. Otherwise the value of the register before
72 int32_t value:31; member
77 * bit will be set. Otherwise the value of the register before
82 int16_t value:15; member
87 * bit will be set. Otherwise the value of the register before
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H A Dcvmx-scratch.h7 * Copyright (c) 2003-2008 Cavium Networks
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
31 * Scratch memory is byte addressable - all addresses are byte addresses.
40 * compile without warnings for both 32bit and 64bit.
42 #define CVMX_SCRATCH_BASE (-32768l) /* 0xffffffffffff8000 */
45 * Reads an 8 bit value from the processor local scratchpad memory.
49 * Returns value read
57 * Reads a 16 bit value from the processor local scratchpad memory.
61 * Returns value read
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/linux/sound/soc/ti/
H A Domap-mcbsp-priv.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * OMAP Multi-Channel Buffered Serial Port
12 #include <linux/platform_data/asoc-ti-mcbsp.h>
51 /* OMAP1-OMAP2420 registers */
73 /************************** McBSP SPCR1 bit definitions ***********************/
74 #define RRST BIT(0)
75 #define RRDY BIT(1)
76 #define RFULL BIT(2)
77 #define RSYNC_ERR BIT(3)
78 #define RINTM(value) (((value) & 0x3) << 4) /* bits 4:5 */ argument
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/linux/drivers/phy/tegra/
H A Dxusb-tegra186.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2016-2022, NVIDIA CORPORATION. All rights reserved.
21 #define HS_CURR_LEVEL_PADX_SHIFT(x) ((x) ? (11 + (x - 1) * 6) : 0)
50 #define USB2_PORT_WAKE_INTERRUPT_ENABLE(x) BIT(x)
51 #define USB2_PORT_WAKEUP_EVENT(x) BIT((x) + 7)
52 #define SS_PORT_WAKE_INTERRUPT_ENABLE(x) BIT((x) + 14)
53 #define SS_PORT_WAKEUP_EVENT(x) BIT((x) + 21)
54 #define USB2_HSIC_PORT_WAKE_INTERRUPT_ENABLE(x) BIT((x) + 28)
55 #define USB2_HSIC_PORT_WAKEUP_EVENT(x) BIT((x) + 30)
63 #define SSPX_ELPG_CLAMP_EN(x) BIT(0 + (x) * 3)
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H A Dxusb-tegra210.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2014-2020, NVIDIA CORPORATION. All rights reserved.
27 ((x) ? (11 + ((x) - 1) * 6) : 0)
58 #define USB2_PORT_WAKE_INTERRUPT_ENABLE(x) BIT((x))
59 #define USB2_PORT_WAKEUP_EVENT(x) BIT((x) + 7)
60 #define SS_PORT_WAKE_INTERRUPT_ENABLE(x) BIT((x) + 14)
61 #define SS_PORT_WAKEUP_EVENT(x) BIT((x) + 21)
62 #define USB2_HSIC_PORT_WAKE_INTERRUPT_ENABLE(x) BIT((x) + 28)
63 #define USB2_HSIC_PORT_WAKEUP_EVENT(x) BIT((x) + 30)
218 #define XUSB_PADCTL_UPHY_MISC_PAD_CTL1_AUX_RX_TERM_EN BIT(18)
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/linux/include/linux/
H A Dbitops.h1 /* SPDX-License-Identifier: GPL-2.0 */
24 * Defined here because those may be needed by architecture-specific static
28 #include <asm-generic/bitops/generic-non-atomic.h>
31 * Many architecture-specific non-atomic bitops contain inline asm code and due
32 * to that the compiler can't optimize them to compile-time expressions or
36 * equal to `unsigned long foo = BIT(BAR)`, pick the generic C alternative when
39 * The casts to `uintptr_t` are needed to mitigate `-Waddress` warnings when
40 * passing a bitmap from .bss or .data (-> `!!addr` is always true).
50 * The following macros are non-atomic versions of their non-underscored
91 return order; /* We could be slightly more clever with -1 here... */ in get_bitmask_order()
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/linux/drivers/net/wireless/realtek/rtw88/
H A Dfw.h1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 /* Copyright(c) 2018-2019 Realtek Corporation
32 #define RTW_DEFAULT_CQM_THOLD -70
99 #define RTW_C2H_RA_RPT_SGI BIT(7)
145 FW_FEATURE_SIG = BIT(0),
146 FW_FEATURE_LPS_C2H = BIT(1),
147 FW_FEATURE_LCLK = BIT(2),
148 FW_FEATURE_PG = BIT(3),
149 FW_FEATURE_TX_WAKE = BIT(4),
150 FW_FEATURE_BCN_FILTER = BIT(5),
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/linux/arch/arm/mach-sa1100/include/mach/
H A Dbitfield.h10 * Purpose Definition of macros to operate on bit fields.
29 * The macro "Fld" encodes a bit field, given its size and its shift value
30 * with respect to bit 0.
33 * A more intuitive way to encode bit fields would have been to use their
34 * mask. However, extracting size and shift value information from a bit
35 * field's mask is cumbersome and might break the assembler (255-character
36 * line-size limit).
39 * Size Size of the bit field, in number of bits.
40 * Shft Shift value of the bit field with respect to bit 0.
43 * Fld Encoded bit field.
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/linux/arch/mips/kernel/
H A Dunaligned.c18 * only the performance is affected. Much worse is that such code is non-
30 * option in your user programs - I discourage the use of the software
31 * emulation strongly - use the following code in your userland stuff:
92 #include <asm/unaligned-emul.h>
97 #include "access-helper.h"
115 unsigned long origpc, orig31, value; in emulate_load_store_insn() local
121 orig31 = regs->regs[31]; in emulate_load_store_insn()
133 * can assume therefore that the code is MIPS-aware and in emulate_load_store_insn()
173 LoadW(addr, value, res); in emulate_load_store_insn()
177 regs->regs[insn.mxu_lx_format.rd] = value; in emulate_load_store_insn()
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/linux/drivers/mmc/host/
H A Dsunplus-mmc.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Author: Li-hao Kuo <lhjeff911@gmail.com>
11 #include <linux/dma-mapping.h>
18 #include <linux/mmc/slot-gpio.h>
44 #define SPMMC_HW_DMA_RST BIT(9)
45 #define SPMMC_DMAIDLE BIT(10)
65 #define SPMMC_SDINT_SDCMPEN BIT(0)
66 #define SPMMC_SDINT_SDCMP BIT(1)
67 #define SPMMC_SDINT_SDCMPCLR BIT(2)
68 #define SPMMC_SDINT_SDIOEN BIT(3)
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H A Dsdhci-pci-gli.c1 // SPDX-License-Identifier: GPL-2.0+
7 * Version: v0.9.0 (2019-08-08)
18 #include "sdhci-cqhci.h"
19 #include "sdhci-pci.h"
21 #include "sdhci-uhs2.h"
25 #define SDHCI_GLI_9750_WT_EN BIT(0)
38 #define SDHCI_GLI_9750_SEL_1 BIT(29)
39 #define SDHCI_GLI_9750_SEL_2 BIT(31)
40 #define SDHCI_GLI_9750_ALL_RST (BIT(24)|BIT(25)|BIT(28)|BIT(30))
45 #define SDHCI_GLI_9750_PLL_DIR BIT(15)
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/linux/include/uapi/linux/
H A Dswab.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
72 __u32 l = val & ((1ULL << 32) - 1); in __fswab64()
98 * __swab16 - return a byteswapped 16-bit value
99 * @x: value to byteswap
111 * __swab32 - return a byteswapped 32-bit value
112 * @x: value to byteswap
124 * __swab64 - return a byteswapped 64-bit value
125 * @x: value to byteswap
146 * __swahw32 - return a word-swapped 32-bit value
147 * @x: value to wordswap
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/linux/sound/soc/bcm/
H A Dcygnus-ssp.c1 // SPDX-License-Identifier: GPL-2.0-only
2 // Copyright (C) 2014-2015 Broadcom Corporation
14 #include <sound/soc-dai.h>
16 #include "cygnus-ssp.h"
25 #define PLAYBACK_STREAM_MASK BIT(0)
26 #define CAPTURE_STREAM_MASK BIT(1)
241 return &cygaud->portinfo[dai->id]; in cygnus_dai_get_portinfo()
246 u32 value, fci_id; in audio_ssp_init_portregs() local
249 switch (aio->port_type) { in audio_ssp_init_portregs()
251 value = readl(aio->cygaud->audio + aio->regs.i2s_stream_cfg); in audio_ssp_init_portregs()
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/linux/drivers/phy/freescale/
H A Dphy-fsl-imx8mq-usb.c1 // SPDX-License-Identifier: GPL-2.0+
16 #define PHY_CTRL0_REF_SSP_EN BIT(2)
22 #define PHY_CTRL1_RESET BIT(0)
23 #define PHY_CTRL1_COMMONONN BIT(1)
24 #define PHY_CTRL1_ATERESET BIT(3)
25 #define PHY_CTRL1_VDATSRCENB0 BIT(19)
26 #define PHY_CTRL1_VDATDETENB0 BIT(20)
29 #define PHY_CTRL2_TXENABLEN0 BIT(8)
30 #define PHY_CTRL2_OTG_DISABLE BIT(9)
43 #define PHY_CTRL5_DMPWD_OVERRIDE_SEL BIT(23)
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/linux/drivers/iio/magnetometer/
H A Dst_magn_core.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright 2012-2013 STMicroelectronics Inc.
23 /* DEFAULT VALUE FOR SENSORS */
63 return &mdata->mount_matrix; in st_magn_get_mount_matrix()
73 BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE),
78 BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE),
83 BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE),
92 BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE),
97 BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE),
102 BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE),
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/linux/Documentation/devicetree/bindings/powerpc/
H A Dibm,powerpc-cpu-features.txt3 (skiboot/doc/device-tree/ibm,powerpc-cpu-features/binding.txt)
9 ibm,powerpc-cpu-features binding
19 /cpus/ibm,powerpc-cpu-features node binding
20 -------------------------------------------
22 Node: ibm,powerpc-cpu-features
26 The node name must be "ibm,powerpc-cpu-features".
35 - compatible
37 Value type: string
38 Definition: "ibm,powerpc-cpu-features"
45 - isa
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/linux/arch/xtensa/include/asm/
H A Dbitops.h2 * include/asm-xtensa/bitops.h
10 * Copyright (C) 2001 - 2007 Tensilica Inc.
24 #include <asm-generic/bitops/non-atomic.h>
37 * bit 0 is the LSB of addr; bit 32 is the LSB of (addr+1).
42 return 31 - __cntlz(~x & -~x); in ffz()
46 * __ffs: Find first bit set in word. Return 0 for bit 0
51 return 31 - __cntlz(x & -x); in __ffs()
55 * ffs: Find first bit set in word. This is defined the same way as
62 return 32 - __cntlz(x & -x); in ffs()
66 * fls: Find last (most-significant) bit set in word.
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/linux/Documentation/devicetree/bindings/regulator/
H A Danatop-regulator.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/regulator/anatop-regulator.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>
13 - $ref: regulator.yaml#
17 const: fsl,anatop-regulator
19 regulator-name: true
21 anatop-reg-offset:
23 description: u32 value representing the anatop MFD register offset.
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/linux/tools/testing/selftests/powerpc/vphn/
H A Dtest-vphn.c1 // SPDX-License-Identifier: GPL-2.0
41 "vphn: 1 x 16-bit value",
56 "vphn: 2 x 16-bit values",
72 "vphn: 3 x 16-bit value
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/linux/include/media/drv-intf/
H A Dsaa7146.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 #include <linux/delay.h> /* for delay-stuff */
7 #include <linux/pci.h> /* for pci-config-stuff, vendor ids etc. */
16 #include <media/v4l2-device.h>
17 #include <media/v4l2-ctrls.h>
22 #define saa7146_write(sxy,adr,dat) writel((dat),(sxy->mem+(adr)))
23 #define saa7146_read(sxy,adr) readl(sxy->mem+(adr))
107 u32 irq_mask; /* mask to indicate, which irq-events are handled by the extension */
129 u32 revision; /* chip revision; needed for bug-workarounds*/
131 /* pci-device & irq stuff*/
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/linux/drivers/net/ethernet/sfc/falcon/
H A Dio.h1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Copyright 2005-2006 Fen Systems Ltd.
5 * Copyright 2006-2013 Solarflare Communications Inc.
25 * the BIU collects the written value and does not write to the
27 * similar buffering scheme applies to host access to the NIC's 64-bit
30 * Writes to different CSRs and 64-bit SRAM words must be serialised,
34 * We also serialise reads from 128-bit CSRs and SRAM with the same
39 * 128-bit but are special-cased in the BIU to avoid the need for
42 * - They are write-only.
43 * - The semantics of writing to these registers are such that
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/linux/drivers/platform/x86/uniwill/
H A Duniwill-acpi.c1 // SPDX-License-Identifier: GPL-2.0-or-later
25 #include <linux/fixp-arith.h>
27 #include <linux/hwmon-sysfs.h>
30 #include <linux/input/sparse-keymap.h>
34 #include <linux/led-class-multicolor.h>
52 #include "uniwill-wmi.h"
71 #define BAT_DISCHARGING BIT(0)
100 #define WIFI_STATUS_ON BIT(7)
101 /* BIT(5) is also unset depending on the rfkill state (bluetooth?) */
112 #define ENABLE_MANUAL_CTRL BIT(0)
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/linux/drivers/net/ethernet/sfc/siena/
H A Dio.h1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Copyright 2005-2006 Fen Systems Ltd.
5 * Copyright 2006-2013 Solarflare Communications Inc.
25 * the BIU collects the written value and does not write to the
27 * similar buffering scheme applies to host access to the NIC's 64-bit
30 * Writes to different CSRs and 64-bit SRAM words must be serialised,
34 * We also serialise reads from 128-bit CSRs and SRAM with the same
39 * 128-bit but are special-cased in the BIU to avoid the need for
42 * - They are write-only.
43 * - The semantics of writing to these registers are such that
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dce112/
H A Ddce112_compressor.c2 * Copyright 2012-15 Advanced Micro Devices, Inc.
37 cp110->base.ctx->logger
39 (reg + cp110->offsets.dcp_offset)
41 (reg + cp110->offsets.dmif_offset)
45 .dcp_offset = (mmDCP0_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
48 - mmDMIF_PG0_DPG_PIPE_DPM_CONTROL),
51 .dcp_offset = (mmDCP1_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
54 - mmDMIF_PG0_DPG_PIPE_DPM_CONTROL),
57 .dcp_offset = (mmDCP2_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
60 - mmDMIF_PG0_DPG_PIPE_DPM_CONTROL),
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