1 /* SPDX-License-Identifier: GPL-2.0-only */
4  * Copyright 2005-2006 Fen Systems Ltd.
5  * Copyright 2006-2013 Solarflare Communications Inc.
25  * the BIU collects the written value and does not write to the
27  * similar buffering scheme applies to host access to the NIC's 64-bit
30  * Writes to different CSRs and 64-bit SRAM words must be serialised,
34  * We also serialise reads from 128-bit CSRs and SRAM with the same
39  * 128-bit but are special-cased in the BIU to avoid the need for
42  * - They are write-only.
43  * - The semantics of writing to these registers are such that
45  * - If the host writes to the last dword address of such a register
50  * - If the host writes to the address of any other part of such a
66 /* Hardware issue requires that only 64-bit naturally aligned writes
72 /* PIO is a win only if write-combining is possible */
80 	return efx->reg_base + reg;  in efx_reg()
84 static inline void _efx_writeq(struct efx_nic *efx, __le64 value,  in _efx_writeq()  argument
87 	__raw_writeq((__force u64)value, efx->membase + reg);  in _efx_writeq()
91 	return (__force __le64)__raw_readq(efx->membase + reg);  in _efx_readq()
95 static inline void _efx_writed(struct efx_nic *efx, __le32 value,  in _efx_writed()  argument
98 	__raw_writel((__force u32)value, efx->membase + reg);  in _efx_writed()
102 	return (__force __le32)__raw_readl(efx->membase + reg);  in _efx_readd()
105 /* Write a normal 128-bit CSR, locking as appropriate. */
106 static inline void efx_writeo(struct efx_nic *efx, const efx_oword_t *value,  in efx_writeo()  argument
111 	netif_vdbg(efx, hw, efx->net_dev,  in efx_writeo()
113 		   EFX_OWORD_VAL(*value));  in efx_writeo()
115 	spin_lock_irqsave(&efx->biu_lock, flags);  in efx_writeo()
117 	_efx_writeq(efx, value->u64[0], reg + 0);  in efx_writeo()
118 	_efx_writeq(efx, value->u64[1], reg + 8);  in efx_writeo()
120 	_efx_writed(efx, value->u32[0], reg + 0);  in efx_writeo()
121 	_efx_writed(efx, value->u32[1], reg + 4);  in efx_writeo()
122 	_efx_writed(efx, value->u32[2], reg + 8);  in efx_writeo()
123 	_efx_writed(efx, value->u32[3], reg + 12);  in efx_writeo()
125 	spin_unlock_irqrestore(&efx->biu_lock, flags);  in efx_writeo()
128 /* Write 64-bit SRAM through the supplied mapping, locking as appropriate. */
130 				   const efx_qword_t *value, unsigned int index)  in efx_sram_writeq()  argument
132 	unsigned int addr = index * sizeof(*value);  in efx_sram_writeq()
135 	netif_vdbg(efx, hw, efx->net_dev,  in efx_sram_writeq()
137 		   addr, EFX_QWORD_VAL(*value));  in efx_sram_writeq()
139 	spin_lock_irqsave(&efx->biu_lock, flags);  in efx_sram_writeq()
141 	__raw_writeq((__force u64)value->u64[0], membase + addr);  in efx_sram_writeq()
143 	__raw_writel((__force u32)value->u32[0], membase + addr);  in efx_sram_writeq()
144 	__raw_writel((__force u32)value->u32[1], membase + addr + 4);  in efx_sram_writeq()
146 	spin_unlock_irqrestore(&efx->biu_lock, flags);  in efx_sram_writeq()
149 /* Write a 32-bit CSR or the last dword of a special 128-bit CSR */
150 static inline void efx_writed(struct efx_nic *efx, const efx_dword_t *value,  in efx_writed()  argument
153 	netif_vdbg(efx, hw, efx->net_dev,  in efx_writed()
155 		   reg, EFX_DWORD_VAL(*value));  in efx_writed()
158 	_efx_writed(efx, value->u32[0], reg);  in efx_writed()
161 /* Read a 128-bit CSR, locking as appropriate. */
162 static inline void efx_reado(struct efx_nic *efx, efx_oword_t *value,  in efx_reado()  argument
167 	spin_lock_irqsave(&efx->biu_lock, flags);  in efx_reado()
168 	value->u32[0] = _efx_readd(efx, reg + 0);  in efx_reado()
169 	value->u32[1] = _efx_readd(efx, reg + 4);  in efx_reado()
170 	value->u32[2] = _efx_readd(efx, reg + 8);  in efx_reado()
171 	value->u32[3] = _efx_readd(efx, reg + 12);  in efx_reado()
172 	spin_unlock_irqrestore(&efx->biu_lock, flags);  in efx_reado()
174 	netif_vdbg(efx, hw, efx->net_dev,  in efx_reado()
176 		   EFX_OWORD_VAL(*value));  in efx_reado()
179 /* Read 64-bit SRAM through the supplied mapping, locking as appropriate. */
181 				  efx_qword_t *value, unsigned int index)  in efx_sram_readq()  argument
183 	unsigned int addr = index * sizeof(*value);  in efx_sram_readq()
186 	spin_lock_irqsave(&efx->biu_lock, flags);  in efx_sram_readq()
188 	value->u64[0] = (__force __le64)__raw_readq(membase + addr);  in efx_sram_readq()
190 	value->u32[0] = (__force __le32)__raw_readl(membase + addr);  in efx_sram_readq()
191 	value->u32[1] = (__force __le32)__raw_readl(membase + addr + 4);  in efx_sram_readq()
193 	spin_unlock_irqrestore(&efx->biu_lock, flags);  in efx_sram_readq()
195 	netif_vdbg(efx, hw, efx->net_dev,  in efx_sram_readq()
197 		   addr, EFX_QWORD_VAL(*value));  in efx_sram_readq()
200 /* Read a 32-bit CSR or SRAM */
201 static inline void efx_readd(struct efx_nic *efx, efx_dword_t *value,  in efx_readd()  argument
204 	value->u32[0] = _efx_readd(efx, reg);  in efx_readd()
205 	netif_vdbg(efx, hw, efx->net_dev,  in efx_readd()
207 		   reg, EFX_DWORD_VAL(*value));  in efx_readd()
210 /* Write a 128-bit CSR forming part of a table */
212 efx_writeo_table(struct efx_nic *efx, const efx_oword_t *value,  in efx_writeo_table()  argument
215 	efx_writeo(efx, value, reg + index * sizeof(efx_oword_t));  in efx_writeo_table()
218 /* Read a 128-bit CSR forming part of a table */
219 static inline void efx_reado_table(struct efx_nic *efx, efx_oword_t *value,  in efx_reado_table()  argument
222 	efx_reado(efx, value, reg + index * sizeof(efx_oword_t));  in efx_reado_table()
225 /* default VI stride (step between per-VI registers) is 8K on EF10 and
231 /* Calculate offset to page-mapped register */
235 	return page * efx->vi_stride + reg;  in efx_paged_reg()
239 static inline void _efx_writeo_page(struct efx_nic *efx, efx_oword_t *value,  in _efx_writeo_page()  argument
244 	netif_vdbg(efx, hw, efx->net_dev,  in _efx_writeo_page()
246 		   EFX_OWORD_VAL(*value));  in _efx_writeo_page()
249 	_efx_writeq(efx, value->u64[0], reg + 0);  in _efx_writeo_page()
250 	_efx_writeq(efx, value->u64[1], reg + 8);  in _efx_writeo_page()
252 	_efx_writed(efx, value->u32[0], reg + 0);  in _efx_writeo_page()
253 	_efx_writed(efx, value->u32[1], reg + 4);  in _efx_writeo_page()
254 	_efx_writed(efx, value->u32[2], reg + 8);  in _efx_writeo_page()
255 	_efx_writed(efx, value->u32[3], reg + 12);  in _efx_writeo_page()
258 #define efx_writeo_page(efx, value, reg, page)				\  argument
259 	_efx_writeo_page(efx, value,					\
264 /* Write a page-mapped 32-bit CSR (EVQ_RPTR, EVQ_TMR (EF10), or the
268 _efx_writed_page(struct efx_nic *efx, const efx_dword_t *value,  in _efx_writed_page()  argument
271 	efx_writed(efx, value, efx_paged_reg(efx, page, reg));  in _efx_writed_page()
273 #define efx_writed_page(efx, value, reg, page)				\  argument
274 	_efx_writed_page(efx, value,					\
286 /* Write TIMER_COMMAND.  This is a page-mapped 32-bit CSR, but a bug
291 					   const efx_dword_t *value,  in _efx_writed_page_locked()  argument
298 		spin_lock_irqsave(&efx->biu_lock, flags);  in _efx_writed_page_locked()
299 		efx_writed(efx, value, efx_paged_reg(efx, page, reg));  in _efx_writed_page_locked()
300 		spin_unlock_irqrestore(&efx->biu_lock, flags);  in _efx_writed_page_locked()
302 		efx_writed(efx, value, efx_paged_reg(efx, page, reg));  in _efx_writed_page_locked()
305 #define efx_writed_page_locked(efx, value, reg, page)			\  argument
306 	_efx_writed_page_locked(efx, value,				\