Lines Matching +full:bit +full:- +full:value
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 * Copyright (c) 2013-2015 Imagination Technologies
13 #include <linux/clk-provider.h>
18 * struct ingenic_cgu_pll_info - information about a PLL
21 * @m_shift: the number of bits to shift the multiplier value by (ie. the
22 * index of the lowest bit of the multiplier value in the PLL's
25 * @m_offset: the multiplier value which encodes to 0 in the PLL's control
27 * @n_shift: the number of bits to shift the divider value by (ie. the
28 * index of the lowest bit of the divider value in the PLL's
31 * @n_offset: the divider value which encodes to 0 in the PLL's control
33 * @od_shift: the number of bits to shift the post-VCO divider value by (ie.
34 * the index of the lowest bit of the post-VCO divider value in
36 * @od_bits: the size of the post-VCO divider field in bits, or 0 if no
38 * @od_max: the maximum post-VCO divider value
39 * @od_encoding: a pointer to an array mapping post-VCO divider values to
40 * their encoded values in the PLL control register, or -1 for
43 * @bypass_bit: the index of the bypass bit in the PLL control register, or
44 * -1 if there is no bypass bit
45 * @enable_bit: the index of the enable bit in the PLL control register, or
46 * -1 if there is no enable bit (ie, the PLL is always on)
47 * @stable_bit: the index of the stable bit in the PLL control register, or
48 * -1 if there is no stable bit
71 * struct ingenic_cgu_mux_info - information about a clock mux
73 * @shift: number of bits to shift the mux value by (ie. the index of
74 * the lowest bit of the mux value within its control register)
75 * @bits: the size of the mux value in bits
84 * struct ingenic_cgu_div_info - information about a divider
86 * @shift: number of bits to left shift the divide value by (ie. the index of
87 * the lowest bit of the divide value within its control register)
88 * @div: number to divide the divider value by (i.e. if the
89 * effective divider value is the value written to the register
91 * @bits: the size of the divide value in bits
92 * @ce_bit: the index of the change enable bit within reg, or -1 if there
94 * @busy_bit: the index of the busy bit within reg, or -1 if there isn't one
95 * @stop_bit: the index of the stop bit within reg, or -1 if there isn't one
97 * @div_table: optional table to map the value read from the register to the
98 * actual divider value
113 * struct ingenic_cgu_fixdiv_info - information about a fixed divider
121 * struct ingenic_cgu_gate_info - information about a clock gate
123 * @bit: offset of the bit in the register that controls the gate
124 * @clear_to_gate: if set, the clock is gated when the bit is cleared
129 u8 bit;
135 * struct ingenic_cgu_custom_info - information about a custom (SoC) clock
143 * struct ingenic_cgu_clk_info - information about a clock
148 * within the clock_info array of the CGU, or -1 in entries
162 CGU_CLK_EXT = BIT(0),
163 CGU_CLK_PLL = BIT(1),
164 CGU_CLK_GATE = BIT(2),
165 CGU_CLK_MUX = BIT(3),
166 CGU_CLK_MUX_GLITCHFREE = BIT(4),
167 CGU_CLK_DIV = BIT(5),
168 CGU_CLK_FIXDIV = BIT(6),
169 CGU_CLK_CUSTOM = BIT(7),
191 * struct ingenic_cgu - data about the CGU
209 * struct ingenic_clk - private data for a clock
210 * @hw: see Documentation/driver-api/clk.rst
212 * @idx: the index of this clock in cgu->clock_info
223 * ingenic_cgu_new() - create a new CGU instance
237 * ingenic_cgu_register_clocks() - Registers the clocks
242 * Return: 0 on success or -errno if unsuccessful.