Lines Matching +full:bit +full:- +full:value
1 /* SPDX-License-Identifier: GPL-2.0 */
3 * OMAP Multi-Channel Buffered Serial Port
12 #include <linux/platform_data/asoc-ti-mcbsp.h>
51 /* OMAP1-OMAP2420 registers */
73 /************************** McBSP SPCR1 bit definitions ***********************/
74 #define RRST BIT(0)
75 #define RRDY BIT(1)
76 #define RFULL BIT(2)
77 #define RSYNC_ERR BIT(3)
78 #define RINTM(value) (((value) & 0x3) << 4) /* bits 4:5 */ argument
79 #define ABIS BIT(6)
80 #define DXENA BIT(7)
81 #define CLKSTP(value) (((value) & 0x3) << 11) /* bits 11:12 */ argument
82 #define RJUST(value) (((value) & 0x3) << 13) /* bits 13:14 */ argument
83 #define ALB BIT(15)
84 #define DLB BIT(15)
86 /************************** McBSP SPCR2 bit definitions ***********************/
87 #define XRST BIT(0)
88 #define XRDY BIT(1)
89 #define XEMPTY BIT(2)
90 #define XSYNC_ERR BIT(3)
91 #define XINTM(value) (((value) & 0x3) << 4) /* bits 4:5 */ argument
92 #define GRST BIT(6)
93 #define FRST BIT(7)
94 #define SOFT BIT(8)
95 #define FREE BIT(9)
97 /************************** McBSP PCR bit definitions *************************/
98 #define CLKRP BIT(0)
99 #define CLKXP BIT(1)
100 #define FSRP BIT(2)
101 #define FSXP BIT(3)
102 #define DR_STAT BIT(4)
103 #define DX_STAT BIT(5)
104 #define CLKS_STAT BIT(6)
105 #define SCLKME BIT(7)
106 #define CLKRM BIT(8)
107 #define CLKXM BIT(9)
108 #define FSRM BIT(10)
109 #define FSXM BIT(11)
110 #define RIOEN BIT(12)
111 #define XIOEN BIT(13)
112 #define IDLE_EN BIT(14)
114 /************************** McBSP RCR1 bit definitions ************************/
115 #define RWDLEN1(value) (((value) & 0x7) << 5) /* Bits 5:7 */ argument
116 #define RFRLEN1(value) (((value) & 0x7f) << 8) /* Bits 8:14 */ argument
118 /************************** McBSP XCR1 bit definitions ************************/
119 #define XWDLEN1(value) (((value) & 0x7) << 5) /* Bits 5:7 */ argument
120 #define XFRLEN1(value) (((value) & 0x7f) << 8) /* Bits 8:14 */ argument
122 /*************************** McBSP RCR2 bit definitions ***********************/
123 #define RDATDLY(value) ((value) & 0x3) /* Bits 0:1 */ argument
124 #define RFIG BIT(2)
125 #define RCOMPAND(value) (((value) & 0x3) << 3) /* Bits 3:4 */ argument
126 #define RWDLEN2(value) (((value) & 0x7) << 5) /* Bits 5:7 */ argument
127 #define RFRLEN2(value) (((value) & 0x7f) << 8) /* Bits 8:14 */ argument
128 #define RPHASE BIT(15)
130 /*************************** McBSP XCR2 bit definitions ***********************/
131 #define XDATDLY(value) ((value) & 0x3) /* Bits 0:1 */ argument
132 #define XFIG BIT(2)
133 #define XCOMPAND(value) (((value) & 0x3) << 3) /* Bits 3:4 */ argument
134 #define XWDLEN2(value) (((value) & 0x7) << 5) /* Bits 5:7 */ argument
135 #define XFRLEN2(value) (((value) & 0x7f) << 8) /* Bits 8:14 */ argument
136 #define XPHASE BIT(15)
138 /************************* McBSP SRGR1 bit definitions ************************/
139 #define CLKGDV(value) ((value) & 0x7f) /* Bits 0:7 */ argument
140 #define FWID(value) (((value) & 0xff) << 8) /* Bits 8:15 */ argument
142 /************************* McBSP SRGR2 bit definitions ************************/
143 #define FPER(value) ((value) & 0x0fff) /* Bits 0:11 */ argument
144 #define FSGM BIT(12)
145 #define CLKSM BIT(13)
146 #define CLKSP BIT(14)
147 #define GSYNC BIT(15)
149 /************************* McBSP MCR1 bit definitions *************************/
150 #define RMCM BIT(0)
151 #define RCBLK(value) (((value) & 0x7) << 2) /* Bits 2:4 */ argument
152 #define RPABLK(value) (((value) & 0x3) << 5) /* Bits 5:6 */ argument
153 #define RPBBLK(value) (((value) & 0x3) << 7) /* Bits 7:8 */ argument
155 /************************* McBSP MCR2 bit definitions *************************/
156 #define XMCM(value) ((value) & 0x3) /* Bits 0:1 */ argument
157 #define XCBLK(value) (((value) & 0x7) << 2) /* Bits 2:4 */ argument
158 #define XPABLK(value) (((value) & 0x3) << 5) /* Bits 5:6 */ argument
159 #define XPBBLK(value) (((value) & 0x3) << 7) /* Bits 7:8 */ argument
161 /*********************** McBSP XCCR bit definitions *************************/
162 #define XDISABLE BIT(0)
163 #define XDMAEN BIT(3)
164 #define DILB BIT(5)
165 #define XFULL_CYCLE BIT(11)
166 #define DXENDLY(value) (((value) & 0x3) << 12) /* Bits 12:13 */ argument
167 #define PPCONNECT BIT(14)
168 #define EXTCLKGATE BIT(15)
170 /********************** McBSP RCCR bit definitions *************************/
171 #define RDISABLE BIT(0)
172 #define RDMAEN BIT(3)
173 #define RFULL_CYCLE BIT(11)
175 /********************** McBSP SYSCONFIG bit definitions ********************/
176 #define SOFTRST BIT(1)
177 #define ENAWAKEUP BIT(2)
178 #define SIDLEMODE(value) (((value) & 0x3) << 3) argument
179 #define CLOCKACTIVITY(value) (((value) & 0x3) << 8) argument
185 /********************** McBSP WAKEUPEN/IRQST/IRQEN bit definitions *********/
186 #define RSYNCERREN BIT(0)
187 #define RFSREN BIT(1)
188 #define REOFEN BIT(2)
189 #define RRDYEN BIT(3)
190 #define RUNDFLEN BIT(4)
191 #define ROVFLEN BIT(5)
192 #define XSYNCERREN BIT(7)
193 #define XFSXEN BIT(8)
194 #define XEOFEN BIT(9)
195 #define XRDYEN BIT(10)
196 #define XUNDFLEN BIT(11)
197 #define XOVFLEN BIT(12)
198 #define XEMPTYEOFEN BIT(14)
284 void __iomem *addr = mcbsp->io_base + reg * mcbsp->pdata->reg_step; in omap_mcbsp_write()
286 if (mcbsp->pdata->reg_size == 2) { in omap_mcbsp_write()
287 ((u16 *)mcbsp->reg_cache)[reg] = (u16)val; in omap_mcbsp_write()
290 ((u32 *)mcbsp->reg_cache)[reg] = val; in omap_mcbsp_write()
298 void __iomem *addr = mcbsp->io_base + reg * mcbsp->pdata->reg_step; in omap_mcbsp_read()
300 if (mcbsp->pdata->reg_size == 2) { in omap_mcbsp_read()
302 ((u16 *)mcbsp->reg_cache)[reg]; in omap_mcbsp_read()
305 ((u32 *)mcbsp->reg_cache)[reg]; in omap_mcbsp_read()