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/linux/arch/arm/boot/dts/ti/omap/
H A Dam43xx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
8 sys_clkin_ck: clock-sys-clkin-31@40 {
9 #clock-cells = <0>;
10 compatible = "ti,mux-clock";
11 clock-output-names = "sys_clkin_ck";
13 ti,bit-shift = <31>;
17 crystal_freq_sel_ck: clock-crystal-freq-sel-29@40 {
18 #clock-cells = <0>;
19 compatible = "ti,mux-clock";
20 clock-output-names = "crystal_freq_sel_ck";
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H A Dam33xx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
8 sys_clkin_ck: clock-sys-clkin-22@40 {
9 #clock-cells = <0>;
10 compatible = "ti,mux-clock";
11 clock-output-names = "sys_clkin_ck";
13 ti,bit-shift = <22>;
17 adc_tsc_fck: clock-adc-tsc-fck {
18 #clock-cells = <0>;
19 compatible = "fixed-factor-clock";
20 clock-output-names = "adc_tsc_fck";
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/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx7s.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
6 #include <dt-bindings/clock/imx7d-clock.h>
7 #include <dt-bindings/power/imx7-power.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/reset/imx7-reset.h>
12 #include "imx7d-pinfunc.h"
15 #address-cells = <1>;
16 #size-cells = <1>;
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/linux/sound/soc/sunxi/
H A Dsun8i-codec.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * (C) Copyright 2010-2016
9 * Mylène Josserand <mylene.josserand@free-electrons.com>
27 #include <sound/soc-dapm.h>
251 ret = clk_prepare_enable(scodec->clk_bus); in sun8i_codec_runtime_resume()
257 regcache_cache_only(scodec->regmap, false); in sun8i_codec_runtime_resume()
259 ret = regcache_sync(scodec->regmap); in sun8i_codec_runtime_resume()
272 regcache_cache_only(scodec->regmap, true); in sun8i_codec_runtime_suspend()
273 regcache_mark_dirty(scodec->regmap); in sun8i_codec_runtime_suspend()
275 clk_disable_unprepare(scodec->clk_bus); in sun8i_codec_runtime_suspend()
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/linux/sound/pci/ca0106/
H A Dca0106.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Copyright (c) 2004 James Courtier-Dutton <James@superbug.demon.co.uk>
4 * Driver CA0106 chips. e.g. Sound Blaster Audigy LS and Live 24bit
11 * Support interrupts per period.
48 * Added GPIO info for SB Live 24bit.
50 * Implement support for Line-in capture on SB Live 24bit.
52 * Add support for mute control on SB Live 24bit (cards w/ SPI DAC)
73 #define IPR_MIDI_RX_B 0x00020000 /* MIDI UART-B Receive buffer non-empty */
74 #define IPR_MIDI_TX_B 0x00010000 /* MIDI UART-B Transmit buffer empty */
87 #define IPR_MIDI_RX_A 0x00000004 /* MIDI UART-A Receive buffer non-empty */
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/linux/include/net/
H A Dkcm.h1 /* SPDX-License-Identifier: GPL-2.0-only */
60 struct kcm_mux *mux; member
75 /* Don't use bit fields here, these are set under different locks */
92 struct kcm_mux *mux; member
122 /* Per net MUX list */
132 /* Structure for a MUX */
138 struct list_head kcm_socks; /* All KCM sockets on MUX */
139 int kcm_socks_cnt; /* Total KCM socket count for MUX */
140 struct list_head psocks; /* List of all psocks on MUX */
154 spinlock_t lock ____cacheline_aligned_in_smp; /* TX and mux locking */
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/linux/arch/hexagon/include/asm/
H A Dbitops.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Bit operations for the Hexagon architecture
5 * Copyright (c) 2010-2011, The Linux Foundation. All rights reserved.
20 * (i.e. I get to shift by #5-2 (32 bits per long, 4 bytes per access),
23 * Typically, R10 is clobbered for address, R11 bit nr, and R12 is temp
27 * test_and_clear_bit - clear a bit and return its old value
28 * @nr: bit number to clear
41 " {if (!P1) jump 1b; %0 = mux(P0,#1,#0);}\n" in test_and_clear_bit()
51 * test_and_set_bit - set a bit and return its old value
52 * @nr: bit number to set
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/linux/sound/soc/codecs/
H A Dak4619.c1 // SPDX-License-Identifier: GPL-2.0
3 * ak4619.c -- Asahi Kasei ALSA SoC Audio driver
47 #define DAC_DEMP 0x13 /* DAC De-Emphasis Setting */
51 * Bit fields
55 #define PMAD2 BIT(5)
56 #define PMAD1 BIT(4)
57 #define PMDA2 BIT(2)
58 #define PMDA1 BIT(1)
59 #define RSTN BIT(0)
69 #define BCKP BIT(1)
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H A Dlpass-tx-macro.c1 // SPDX-License-Identifier: GPL-2.0-only
2 // Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
12 #include <sound/soc-dapm.h>
15 #include <linux/clk-provider.h>
17 #include "lpass-macro-common.h"
20 #define CDC_TX_MCLK_EN_MASK BIT(0)
21 #define CDC_TX_MCLK_ENABLE BIT(0)
23 #define CDC_TX_FS_CNT_EN_MASK BIT(0)
24 #define CDC_TX_FS_CNT_ENABLE BIT(0)
26 #define CDC_TX_SWR_RESET_MASK BIT(1)
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H A Dwcd934x.c1 // SPDX-License-Identifier: GPL-2.0
6 #include <linux/clk-provider.h>
21 #include <sound/soc-dapm.h>
23 #include "wcd-clsh-v2.h"
24 #include "wcd-common.h"
25 #include "wcd-mbhc-v
3301 slim_rx_mux_to_dai_id(int mux) slim_rx_mux_to_dai_id() argument
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H A Dwcd9335.c1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
3 // Copyright (c) 2017-2018, Linaro Limited
19 #include <sound/soc-dapm.h>
26 #include "wcd-clsh-v2.h"
28 #include <dt-bindings/sound/qcom,wcd9335.h>
99 #define WCD9335_CALCULATE_VOUT_D(req_mv) (((req_mv - 650) * 10) / 25)
126 {"RX INT" #id "_2 MUX", "RX0", "SLIM RX0"}, \
127 {"RX INT" #id "_2 MUX", "RX1", "SLIM RX1"}, \
128 {"RX INT" #id "_2 MUX", "RX2", "SLIM RX2"}, \
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H A Dwcd939x.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
4 * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved.
25 #include <sound/soc-dapm.h>
30 #include "wcd-clsh-v2.h"
31 #include "wcd-commo
3167 wcd939x_typec_mux_set(struct typec_mux_dev * mux,struct typec_mux_state * state) wcd939x_typec_mux_set() argument
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H A Dlpass-va-macro.c1 // SPDX-License-Identifier: GPL-2.0-only
2 // Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
5 #include <linux/clk-provider.h>
16 #include <sound/soc-dapm.h>
19 #include "lpass-macro-common.h"
23 #define CDC_VA_MCLK_CONTROL_EN BIT(
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/linux/drivers/pinctrl/nomadik/
H A Dpinctrl-ab8505.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) ST-Ericsson SA 2012
5 * Author: Patrice Chotard <patrice.chotard@stericsson.com> for ST-Ericsson.
13 #include "pinctrl-abx500.h"
98 * The groups are arranged as sets per altfunction column, so we can
99 * mux in one group at a time by selecting the same altfunction for them
241 * ALTERNATE_FUNCTIONS(GPIO_NUMBER, GPIOSEL bit, ALTERNATFUNC bit1,
247 * means that pin AB8505_PIN_D18 (pin 13) supports 4 mux (default/ALT_A,
249 * select the mux. ALTA, ALTB and ALTC val indicates values to write in
251 * designers didn't apply the same logic on how to select mux in the
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H A Dpinctrl-ab8500.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) ST-Ericsson SA 2012
5 * Author: Patrice Chotard <patrice.chotard@stericsson.com> for ST-Ericsson.
13 #include "pinctrl-abx500.h"
134 * The groups are arranged as sets per altfunction column, so we can
135 * mux in one group at a time by selecting the same altfunction for them
358 * ALTERNATE_FUNCTIONS(GPIO_NUMBER, GPIOSEL bit, ALTERNATFUNC bit1,
364 * means that pin AB8500_PIN_W17 (pin 13) supports 4 mux (default/ALT_A,
366 * select the mux. ALTA, ALTB and ALTC val indicates values to write in
368 * designers didn't apply the same logic on how to select mux in the
[all …]
/linux/Documentation/devicetree/bindings/pinctrl/
H A Dpinctrl-single.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/pinctrl-single.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Tony Lindgren <tony@atomide.com>
21 - enum:
22 - pinctrl-single
23 - pinconf-single
24 - items:
25 - enum:
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/linux/drivers/media/pci/dt3155/
H A Ddt3155.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Copyright (C) 2006-2010 by Marin Mitov *
15 #include <media/v4l2-device.h>
16 #include <media/v4l2-dev.h>
17 #include <media/videobuf2-v4l2.h>
69 /* CSR1 bit masks */
88 /* INT_CSR bit masks */
96 /* IIC_CSR1 bit masks */
99 /* IIC_CSR2 bit masks */
105 /* CSR2 bit masks */
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/linux/drivers/pinctrl/
H A Dpinctrl-at91.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
29 #include "pinctrl-at91.h"
46 * @ops: at91 pinctrl mux ops
114 * struct at91_pmx_func - describes AT91 pinmux functions
134 * struct at91_pmx_pin - describes an At91 pin mux
137 * @mux: the mux mode : gpio or periph_x of the pin i.e. alternate function.
143 enum at91_mux mux; member
148 * struct at91_pin_group - describes an At91 pin group
150 * @pins_conf: the mux mode for each pin in this group. The size of this
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H A Dpinctrl-st.c1 // SPDX-License-Identifier: GPL-2.0-only
65 * Each field in this register is 8 bit corresponding to 8 pins in the bank.
78 * each register is dedicated per pin.
84 #define RT_D_CFG_CLKNOTDATA_MASK BIT(2)
88 #define RT_D_CFG_DELAY_INNOTOUT_MASK BIT(7)
90 #define RT_D_CFG_DOUBLE_EDGE_MASK BIT(8)
92 #define RT_D_CFG_INVERTCLK_MASK BIT(9)
94 #define RT_D_CFG_RETIME_MASK BIT(10)
98 * Below is the bit allocation details for each possible configuration.
99 * All the bit fields can be encapsulated into four variables
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/linux/drivers/pinctrl/freescale/
H A Dpinctrl-imx1-core.c1 // SPDX-License-Identifier: GPL-2.0+
8 // Based on pinctrl-imx.c:
29 #include "pinctrl-imx1.h"
56 #define MX1_MUX_FUNCTION(val) (BIT(0) & val)
57 #define MX1_MUX_GPIO(val) ((BIT(1) & val) >> 1)
58 #define MX1_MUX_DIR(val) ((BIT(2) & val) >> 2)
59 #define MX1_MUX_OCONF(val) (((BIT(4) | BIT(5)) & val) >> 4)
60 #define MX1_MUX_ICONFA(val) (((BIT(8) | BIT(9)) & val) >> 8)
61 #define MX1_MUX_ICONFB(val) (((BIT(10) | BIT(11)) & val) >> 10)
69 * Those controls that are represented by 1 bit have a direct mapping between
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/linux/drivers/pinctrl/meson/
H A Dpinctrl-meson.h1 /* SPDX-License-Identifier: GPL-2.0-only */
20 * struct meson_pmx_group - a pinmux group
26 * @reg: register offset for the group in the domain mux registers
27 * @bit bit index enabling the group
38 * struct meson_pmx_func - a pinmux function
51 * struct meson_reg_desc - a register descriptor
54 * @bit: bit index in register
57 * pull-enable, direction, etc. for a single pin
61 unsigned int bit; member
65 * enum meson_reg_type - type of registers encoded in @meson_reg_desc
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/linux/drivers/media/i2c/
H A Dmax9286.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (C) 2017-2019 Jacopo Mondi
6 * Copyright (C) 2017-2019 Kieran Bingham
7 * Copyright (C) 2017-2019 Laurent Pinchart
8 * Copyright (C) 2017-2019 Niklas Söderlund
20 #include <linux/i2c-mux.h>
26 #include <media/v4l2-async.h>
27 #include <media/v4l2-ctrls.h>
28 #include <media/v4l2-device.h>
29 #include <media/v4l2-fwnode.h>
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/linux/arch/powerpc/platforms/512x/
H A Dclock-commonclk.c1 // SPDX-License-Identifier: GPL-2.0-or-later
12 #include <linux/clk-provider.h>
21 #include <dt-bindings/clock/mpc512x-clock.h>
61 /* intermediates for the mux+gate+div+mux MCLK generation */
89 * interpretation, no CFM, different fourth PSC/CAN mux0 input -- yet
285 /* helper to isolate a bit field from a register */
292 val &= (1 << len) - 1; in get_bit_field()
305 spmf = get_bit_field(&clkregs->spmr, 24, 4); in get_spmf_mult()
326 divcode = get_bit_field(&clkregs->scfr2, 26, 6); in get_sys_div_x2()
350 cpmf = get_bit_field(&clkregs->spmr, 16, 4); in get_cpmf_mult_x2()
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/linux/drivers/net/wwan/iosm/
H A Diosm_ipc_mux.h1 /* SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2020-21 Intel Corporation.
19 /* Size of the buffer for the IP MUX Lite data buffer. */
22 /* TD counts for IP MUX Lite */
26 /* open session request (AP->CP) */
29 /* response to open session request (CP->AP) */
32 /* close session request (AP->CP) */
35 /* response to close session request (CP->AP) */
38 /* Flow control command with mask of the flow per queue/flow. */
58 /* MUX for route link devices */
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/linux/drivers/gpu/drm/mcde/
H A Dmcde_display.c1 // SPDX-License-Identifier: GPL-2.0
5 * (C) ST-Ericsson SA 2013
9 #include <linux/dma-buf.h>
11 #include <linux/media-bus-format.h>
80 mispp = readl(mcde->regs + MCDE_MISPP); in mcde_display_irq()
81 misovl = readl(mcde->regs + MCDE_MISOVL); in mcde_display_irq()
82 mischnl = readl(mcde->regs + MCDE_MISCHNL); in mcde_display_irq()
92 if (!mcde->dpi_output && mcde_dsi_irq(mcde->mdsi)) { in mcde_display_irq()
101 if (mcde->flow_mode == MCDE_COMMAND_ONESHOT_FLOW) { in mcde_display_irq()
102 spin_lock(&mcde->flow_lock); in mcde_display_irq()
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