Lines Matching +full:bit +full:- +full:per +full:- +full:mux
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/atmel,at91rm9200-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Manikandan Muralidharan <manikandan.m@microchip.com>
22 - items:
23 - enum:
24 - atmel,at91rm9200-pinctrl
25 - atmel,at91sam9x5-pinctrl
26 - atmel,sama5d3-pinctrl
27 - microchip,sam9x60-pinctrl
28 - const: simple-mfd
29 - items:
30 - enum:
31 - microchip,sam9x7-pinctrl
32 - const: microchip,sam9x60-pinctrl
33 - const: simple-mfd
35 '#address-cells':
38 '#size-cells':
43 atmel,mux-mask:
44 $ref: /schemas/types.yaml#/definitions/uint32-matrix
46 Array of mask (periph per bank) to describe if a pin can be
67 configured in it by putting 1 to the pin bit (1 << pin)
70 From the datasheet Table 10-2.
106 - $ref: pinctrl.yaml#
109 - compatible
110 - ranges
111 - "#address-cells"
112 - "#size-cells"
113 - atmel,mux-mask
116 'gpio@[0-9a-f]+$':
117 $ref: /schemas/gpio/atmel,at91rm9200-gpio.yaml
128 $ref: /schemas/types.yaml#/definitions/uint32-matrix
131 mux and config setting.The format is
133 Supported pin number and mux varies for different SoCs, and
134 are defined in <include/dt-bindings/pinctrl/at91.h>.
137 - description:
139 - description:
141 - description:
143 - description:
147 - |
148 #include <dt-bindings/clock/at91.h>
149 #include <dt-bindings/interrupt-controller/irq.h>
150 #include <dt-bindings/pinctrl/at91.h>
153 #address-cells = <1>;
154 #size-cells = <1>;
155 compatible = "atmel,at91rm9200-pinctrl", "simple-mfd";
158 atmel,mux-mask = <
166 pinctrl_dbgu: dbgu-0 {
174 compatible = "atmel,at91rm9200-gpio";
177 #gpio-cells = <2>;
178 gpio-controller;
179 interrupt-controller;
180 #interrupt-cells = <2>;