Lines Matching +full:bit +full:- +full:per +full:- +full:mux
1 // SPDX-License-Identifier: GPL-2.0-only
2 // Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
12 #include <sound/soc-dapm.h>
15 #include <linux/clk-provider.h>
17 #include "lpass-macro-common.h"
20 #define CDC_TX_MCLK_EN_MASK BIT(0)
21 #define CDC_TX_MCLK_ENABLE BIT(0)
23 #define CDC_TX_FS_CNT_EN_MASK BIT(0)
24 #define CDC_TX_FS_CNT_ENABLE BIT(0)
26 #define CDC_TX_SWR_RESET_MASK BIT(1)
27 #define CDC_TX_SWR_RESET_ENABLE BIT(1)
28 #define CDC_TX_SWR_CLK_EN_MASK BIT(0)
29 #define CDC_TX_SWR_CLK_ENABLE BIT(0)
87 #define CDC_TXn_PGA_MUTE_MASK BIT(4)
88 #define CDC_TXn_CLK_EN_MASK BIT(5)
92 #define CDC_TXn_PH_EN_MASK BIT(0)
95 #define CDC_TXn_ADC_DMIC_SEL_MASK BIT(7)
102 #define CDC_TXn_HPF_F_CHANGE_MASK BIT(1)
103 #define CDC_TXn_HPF_ZERO_GATE_MASK BIT(0)
110 #define CDC_TX0_MBHC_CTL_EN_MASK BIT(6)
201 #define TX_ADC_TO_DMIC(n) ((n - TX_ADC_MAX)/2)
292 static const DECLARE_TLV_DB_SCALE(digital_gain, -8400, 100, -8400);
617 struct regmap *regmap = tx->regmap; in tx_macro_mclk_enable()
620 if (tx->tx_mclk_users == 0) { in tx_macro_mclk_enable()
632 tx->tx_mclk_users++; in tx_macro_mclk_enable()
634 if (tx->tx_mclk_users <= 0) { in tx_macro_mclk_enable()
635 dev_err(tx->dev, "clock already disabled\n"); in tx_macro_mclk_enable()
636 tx->tx_mclk_users = 0; in tx_macro_mclk_enable()
639 tx->tx_mclk_users--; in tx_macro_mclk_enable()
640 if (tx->tx_mclk_users == 0) { in tx_macro_mclk_enable()
659 if (tx->data->ver > LPASS_VER_9_0_0) in is_amic_enabled()
684 tx = hpf_work->tx; in tx_macro_tx_hpf_corner_freq_callback()
685 component = tx->component; in tx_macro_tx_hpf_corner_freq_callback()
686 hpf_cut_off_freq = hpf_work->hpf_cut_off_freq; in tx_macro_tx_hpf_corner_freq_callback()
688 dec_cfg_reg = CDC_TXn_TX_PATH_CFG0(hpf_work->decimator); in tx_macro_tx_hpf_corner_freq_callback()
689 hpf_gate_reg = CDC_TXn_TX_PATH_SEC2(hpf_work->decimator); in tx_macro_tx_hpf_corner_freq_callback()
691 if (is_amic_enabled(component, tx, hpf_work->decimator)) { in tx_macro_tx_hpf_corner_freq_callback()
710 /* Minimum 1 clk cycle delay is required as per HW spec */ in tx_macro_tx_hpf_corner_freq_callback()
727 tx = tx_mute_dwork->tx; in tx_macro_mute_update_callback()
728 component = tx->component; in tx_macro_mute_update_callback()
729 decimator = tx_mute_dwork->decimator; in tx_macro_mute_update_callback()
738 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in tx_macro_mclk_event()
785 if (widget->shift) { in tx_macro_update_smic_sel_v9_2()
805 struct snd_soc_component *component = snd_soc_dapm_to_component(widget->dapm); in tx_macro_put_dec_enum()
806 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; in tx_macro_put_dec_enum()
811 val = ucontrol->value.enumerated.item[0]; in tx_macro_put_dec_enum()
812 if (val >= e->items) in tx_macro_put_dec_enum()
813 return -EINVAL; in tx_macro_put_dec_enum()
815 switch (e->reg) { in tx_macro_put_dec_enum()
841 dev_err(component->dev, "Error in configuration!!\n"); in tx_macro_put_dec_enum()
842 return -EINVAL; in tx_macro_put_dec_enum()
846 if (widget->shift) /* MSM DMIC */ in tx_macro_put_dec_enum()
849 else if (tx->data->ver <= LPASS_VER_9_0_0) in tx_macro_put_dec_enum()
864 struct snd_soc_component *component = snd_soc_dapm_to_component(widget->dapm); in tx_macro_tx_mixer_get()
865 struct soc_mixer_control *mc = (struct soc_mixer_control *)kcontrol->private_value; in tx_macro_tx_mixer_get()
866 u32 dai_id = widget->shift; in tx_macro_tx_mixer_get()
867 u32 dec_id = mc->shift; in tx_macro_tx_mixer_get()
870 if (test_bit(dec_id, &tx->active_ch_mask[dai_id])) in tx_macro_tx_mixer_get()
871 ucontrol->value.integer.value[0] = 1; in tx_macro_tx_mixer_get()
873 ucontrol->value.integer.value[0] = 0; in tx_macro_tx_mixer_get()
882 struct snd_soc_component *component = snd_soc_dapm_to_component(widget->dapm); in tx_macro_tx_mixer_put()
884 struct soc_mixer_control *mc = (struct soc_mixer_control *)kcontrol->private_value; in tx_macro_tx_mixer_put()
885 u32 dai_id = widget->shift; in tx_macro_tx_mixer_put()
886 u32 dec_id = mc->shift; in tx_macro_tx_mixer_put()
887 u32 enable = ucontrol->value.integer.value[0]; in tx_macro_tx_mixer_put()
891 if (tx->active_decimator[dai_id] == dec_id) in tx_macro_tx_mixer_put()
894 set_bit(dec_id, &tx->active_ch_mask[dai_id]); in tx_macro_tx_mixer_put()
895 tx->active_ch_cnt[dai_id]++; in tx_macro_tx_mixer_put()
896 tx->active_decimator[dai_id] = dec_id; in tx_macro_tx_mixer_put()
898 if (tx->active_decimator[dai_id] == -1) in tx_macro_tx_mixer_put()
901 tx->active_ch_cnt[dai_id]--; in tx_macro_tx_mixer_put()
902 clear_bit(dec_id, &tx->active_ch_mask[dai_id]); in tx_macro_tx_mixer_put()
903 tx->active_decimator[dai_id] = -1; in tx_macro_tx_mixer_put()
905 snd_soc_dapm_mixer_update_power(widget->dapm, kcontrol, enable, update); in tx_macro_tx_mixer_put()
913 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in tx_macro_enable_dec()
923 decimator = w->shift; in tx_macro_enable_dec()
947 tx->dec_mode[decimator]); in tx_macro_enable_dec()
957 /* Minimum 1 clk cycle delay is required as per HW spec */ in tx_macro_enable_dec()
963 tx->tx_hpf_work[decimator].hpf_cut_off_freq = in tx_macro_enable_dec()
977 &tx->tx_mute_dwork[decimator].dwork, in tx_macro_enable_dec()
979 if (tx->tx_hpf_work[decimator].hpf_cut_off_freq != CF_MIN_3DB_150HZ) { in tx_macro_enable_dec()
981 &tx->tx_hpf_work[decimator].dwork, in tx_macro_enable_dec()
998 * 6ms delay is required as per HW spec in tx_macro_enable_dec()
1006 if (tx->bcs_enable) { in tx_macro_enable_dec()
1009 tx->bcs_clk_en = true; in tx_macro_enable_dec()
1014 tx->tx_hpf_work[decimator].hpf_cut_off_freq; in tx_macro_enable_dec()
1018 &tx->tx_hpf_work[decimator].dwork)) { in tx_macro_enable_dec()
1039 * as per HW spec in tx_macro_enable_dec()
1048 cancel_delayed_work_sync(&tx->tx_mute_dwork[decimator].dwork); in tx_macro_enable_dec()
1057 if (tx->bcs_enable) { in tx_macro_enable_dec()
1064 tx->bcs_clk_en = false; in tx_macro_enable_dec()
1076 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; in tx_macro_dec_mode_get()
1077 int path = e->shift_l; in tx_macro_dec_mode_get()
1079 ucontrol->value.integer.value[0] = tx->dec_mode[path]; in tx_macro_dec_mode_get()
1088 int value = ucontrol->value.integer.value[0]; in tx_macro_dec_mode_put()
1089 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; in tx_macro_dec_mode_put()
1090 int path = e->shift_l; in tx_macro_dec_mode_put()
1093 if (tx->dec_mode[path] == value) in tx_macro_dec_mode_put()
1096 tx->dec_mode[path] = value; in tx_macro_dec_mode_put()
1107 ucontrol->value.integer.value[0] = tx->bcs_enable; in tx_macro_get_bcs()
1116 int value = ucontrol->value.integer.value[0]; in tx_macro_set_bcs()
1119 tx->bcs_enable = value; in tx_macro_set_bcs()
1128 struct snd_soc_component *component = dai->component; in tx_macro_hw_params()
1158 dev_err(component->dev, "%s: Invalid TX sample rate: %d\n", in tx_macro_hw_params()
1160 return -EINVAL; in tx_macro_hw_params()
1163 for_each_set_bit(decimator, &tx->active_ch_mask[dai->id], TX_MACRO_DEC_MAX) in tx_macro_hw_params()
1174 struct snd_soc_component *component = dai->component; in tx_macro_get_channel_map()
1177 switch (dai->id) { in tx_macro_get_channel_map()
1181 *tx_slot = tx->active_ch_mask[dai->id]; in tx_macro_get_channel_map()
1182 *tx_num = tx->active_ch_cnt[dai->id]; in tx_macro_get_channel_map()
1192 struct snd_soc_component *component = dai->component; in tx_macro_digital_mute()
1197 if (tx->active_decimator[dai->id] == -1) in tx_macro_digital_mute()
1200 decimator = tx->active_decimator[dai->id]; in tx_macro_digital_mute()
1458 SND_SOC_DAPM_MUX_E("TX DEC0 MUX", SND_SOC_NOPM,
1464 SND_SOC_DAPM_MUX_E("TX DEC1 MUX", SND_SOC_NOPM,
1470 SND_SOC_DAPM_MUX_E("TX DEC2 MUX", SND_SOC_NOPM,
1476 SND_SOC_DAPM_MUX_E("TX DEC3 MUX", SND_SOC_NOPM,
1482 SND_SOC_DAPM_MUX_E("TX DEC4 MUX", SND_SOC_NOPM,
1488 SND_SOC_DAPM_MUX_E("TX DEC5 MUX", SND_SOC_NOPM,
1494 SND_SOC_DAPM_MUX_E("TX DEC6 MUX", SND_SOC_NOPM,
1500 SND_SOC_DAPM_MUX_E("TX DEC7 MUX", SND_SOC_NOPM,
1524 {"TX_AIF1_CAP Mixer", "DEC0", "TX DEC0 MUX"},
1525 {"TX_AIF1_CAP Mixer", "DEC1", "TX DEC1 MUX"},
1526 {"TX_AIF1_CAP Mixer", "DEC2", "TX DEC2 MUX"},
1527 {"TX_AIF1_CAP Mixer", "DEC3", "TX DEC3 MUX"},
1528 {"TX_AIF1_CAP Mixer", "DEC4", "TX DEC4 MUX"},
1529 {"TX_AIF1_CAP Mixer", "DEC5", "TX DEC5 MUX"},
1530 {"TX_AIF1_CAP Mixer", "DEC6", "TX DEC6 MUX"},
1531 {"TX_AIF1_CAP Mixer", "DEC7", "TX DEC7 MUX"},
1533 {"TX_AIF2_CAP Mixer", "DEC0", "TX DEC0 MUX"},
1534 {"TX_AIF2_CAP Mixer", "DEC1", "TX DEC1 MUX"},
1535 {"TX_AIF2_CAP Mixer", "DEC2", "TX DEC2 MUX"},
1536 {"TX_AIF2_CAP Mixer", "DEC3", "TX DEC3 MUX"},
1537 {"TX_AIF2_CAP Mixer", "DEC4", "TX DEC4 MUX"},
1538 {"TX_AIF2_CAP Mixer", "DEC5", "TX DEC5 MUX"},
1539 {"TX_AIF2_CAP Mixer", "DEC6", "TX DEC6 MUX"},
1540 {"TX_AIF2_CAP Mixer", "DEC7", "TX DEC7 MUX"},
1542 {"TX_AIF3_CAP Mixer", "DEC0", "TX DEC0 MUX"},
1543 {"TX_AIF3_CAP Mixer", "DEC1", "TX DEC1 MUX"},
1544 {"TX_AIF3_CAP Mixer", "DEC2", "TX DEC2 MUX"},
1545 {"TX_AIF3_CAP Mixer", "DEC3", "TX DEC3 MUX"},
1546 {"TX_AIF3_CAP Mixer", "DEC4", "TX DEC4 MUX"},
1547 {"TX_AIF3_CAP Mixer", "DEC5", "TX DEC5 MUX"},
1548 {"TX_AIF3_CAP Mixer", "DEC6", "TX DEC6 MUX"},
1549 {"TX_AIF3_CAP Mixer", "DEC7", "TX DEC7 MUX"},
1551 {"TX DEC0 MUX", NULL, "TX_MCLK"},
1552 {"TX DEC1 MUX", NULL, "TX_MCLK"},
1553 {"TX DEC2 MUX", NULL, "TX_MCLK"},
1554 {"TX DEC3 MUX", NULL, "TX_MCLK"},
1555 {"TX DEC4 MUX", NULL, "TX_MCLK"},
1556 {"TX DEC5 MUX", NULL, "TX_MCLK"},
1557 {"TX DEC6 MUX", NULL, "TX_MCLK"},
1558 {"TX DEC7 MUX", NULL, "TX_MCLK"},
1560 {"TX DEC0 MUX", "MSM_DMIC", "TX DMIC MUX0"},
1570 {"TX DEC1 MUX", "MSM_DMIC", "TX DMIC MUX1"},
1580 {"TX DEC2 MUX", "MSM_DMIC", "TX DMIC MUX2"},
1590 {"TX DEC3 MUX", "MSM_DMIC", "TX DMIC MUX3"},
1600 {"TX DEC4 MUX", "MSM_DMIC", "TX DMIC MUX4"},
1610 {"TX DEC5 MUX", "MSM_DMIC", "TX DMIC MUX5"},
1620 {"TX DEC6 MUX", "MSM_DMIC", "TX DMIC MUX6"},
1630 {"TX DEC7 MUX", "MSM_DMIC", "TX DMIC MUX7"},
1714 {"TX DEC0 MUX", "SWR_MIC", "TX SMIC MUX0"},
1729 {"TX DEC1 MUX", "SWR_MIC", "TX SMIC MUX1"},
1744 {"TX DEC2 MUX", "SWR_MIC", "TX SMIC MUX2"},
1759 {"TX DEC3 MUX", "SWR_MIC", "TX SMIC MUX3"},
1774 {"TX DEC4 MUX", "SWR_MIC", "TX SMIC MUX4"},
1789 {"TX DEC5 MUX", "SWR_MIC", "TX SMIC MUX5"},
1804 {"TX DEC6 MUX", "SWR_MIC", "TX SMIC MUX6"},
1819 {"TX DEC7 MUX", "SWR_MIC", "TX SMIC MUX7"},
1908 {"TX DEC0 MUX", "SWR_MIC", "TX SMIC MUX0"},
1923 {"TX DEC1 MUX", "SWR_MIC", "TX SMIC MUX1"},
1938 {"TX DEC2 MUX", "SWR_MIC", "TX SMIC MUX2"},
1953 {"TX DEC3 MUX", "SWR_MIC", "TX SMIC MUX3"},
1968 {"TX DEC4 MUX", "SWR_MIC", "TX SMIC MUX4"},
1983 {"TX DEC5 MUX", "SWR_MIC", "TX SMIC MUX5"},
1998 {"TX DEC6 MUX", "SWR_MIC", "TX SMIC MUX6"},
2013 {"TX DEC7 MUX", "SWR_MIC", "TX SMIC MUX7"},
2032 -84, 40, digital_gain),
2035 -84, 40, digital_gain),
2038 -84, 40, digital_gain),
2041 -84, 40, digital_gain),
2044 -84, 40, digital_gain),
2047 -84, 40, digital_gain),
2050 -84, 40, digital_gain),
2053 -84, 40, digital_gain),
2089 if (tx->data->extra_widgets_num) { in tx_macro_component_extend()
2090 ret = snd_soc_dapm_new_controls(dapm, tx->data->extra_widgets, in tx_macro_component_extend()
2091 tx->data->extra_widgets_num); in tx_macro_component_extend()
2093 dev_err(tx->dev, "failed to add extra widgets: %d\n", ret); in tx_macro_component_extend()
2098 if (tx->data->extra_routes_num) { in tx_macro_component_extend()
2099 ret = snd_soc_dapm_add_routes(dapm, tx->data->extra_routes, in tx_macro_component_extend()
2100 tx->data->extra_routes_num); in tx_macro_component_extend()
2102 dev_err(tx->dev, "failed to add extra routes: %d\n", ret); in tx_macro_component_extend()
2119 snd_soc_component_init_regmap(comp, tx->regmap); in tx_macro_component_probe()
2122 tx->tx_hpf_work[i].tx = tx; in tx_macro_component_probe()
2123 tx->tx_hpf_work[i].decimator = i; in tx_macro_component_probe()
2124 INIT_DELAYED_WORK(&tx->tx_hpf_work[i].dwork, in tx_macro_component_probe()
2129 tx->tx_mute_dwork[i].tx = tx; in tx_macro_component_probe()
2130 tx->tx_mute_dwork[i].decimator = i; in tx_macro_component_probe()
2131 INIT_DELAYED_WORK(&tx->tx_mute_dwork[i].dwork, in tx_macro_component_probe()
2134 tx->component = comp; in tx_macro_component_probe()
2150 struct regmap *regmap = tx->regmap; in swclk_gate_enable()
2153 ret = clk_prepare_enable(tx->mclk); in swclk_gate_enable()
2155 dev_err(tx->dev, "failed to enable mclk\n"); in swclk_gate_enable()
2170 struct regmap *regmap = tx->regmap; in swclk_gate_disable()
2176 clk_disable_unprepare(tx->mclk); in swclk_gate_disable()
2184 regmap_read(tx->regmap, CDC_TX_CLK_RST_CTRL_SWR_CONTROL, &val); in swclk_gate_is_enabled()
2185 ret = val & BIT(0); in swclk_gate_is_enabled()
2206 struct device *dev = tx->dev; in tx_macro_register_mclk_output()
2208 const char *clk_name = "lpass-tx-mclk"; in tx_macro_register_mclk_output()
2213 if (tx->npl) in tx_macro_register_mclk_output()
2214 parent_clk_name = __clk_get_name(tx->npl); in tx_macro_register_mclk_output()
2216 parent_clk_name = __clk_get_name(tx->mclk); in tx_macro_register_mclk_output()
2223 tx->hw.init = &init; in tx_macro_register_mclk_output()
2224 hw = &tx->hw; in tx_macro_register_mclk_output()
2233 .name = "RX-MACRO",
2245 struct device *dev = &pdev->dev; in tx_macro_probe()
2246 struct device_node *np = dev->of_node; in tx_macro_probe()
2253 return -ENOMEM; in tx_macro_probe()
2255 tx->data = device_get_match_data(dev); in tx_macro_probe()
2257 tx->macro = devm_clk_get_optional(dev, "macro"); in tx_macro_probe()
2258 if (IS_ERR(tx->macro)) in tx_macro_probe()
2259 return dev_err_probe(dev, PTR_ERR(tx->macro), "unable to get macro clock\n"); in tx_macro_probe()
2261 tx->dcodec = devm_clk_get_optional(dev, "dcodec"); in tx_macro_probe()
2262 if (IS_ERR(tx->dcodec)) in tx_macro_probe()
2263 return dev_err_probe(dev, PTR_ERR(tx->dcodec), "unable to get dcodec clock\n"); in tx_macro_probe()
2265 tx->mclk = devm_clk_get(dev, "mclk"); in tx_macro_probe()
2266 if (IS_ERR(tx->mclk)) in tx_macro_probe()
2267 return dev_err_probe(dev, PTR_ERR(tx->mclk), "unable to get mclk clock\n"); in tx_macro_probe()
2269 if (tx->data->flags & LPASS_MACRO_FLAG_HAS_NPL_CLOCK) { in tx_macro_probe()
2270 tx->npl = devm_clk_get(dev, "npl"); in tx_macro_probe()
2271 if (IS_ERR(tx->npl)) in tx_macro_probe()
2272 return dev_err_probe(dev, PTR_ERR(tx->npl), "unable to get npl clock\n"); in tx_macro_probe()
2275 tx->fsgen = devm_clk_get(dev, "fsgen"); in tx_macro_probe()
2276 if (IS_ERR(tx->fsgen)) in tx_macro_probe()
2277 return dev_err_probe(dev, PTR_ERR(tx->fsgen), "unable to get fsgen clock\n"); in tx_macro_probe()
2279 tx->pds = lpass_macro_pds_init(dev); in tx_macro_probe()
2280 if (IS_ERR(tx->pds)) in tx_macro_probe()
2281 return PTR_ERR(tx->pds); in tx_macro_probe()
2290 if (of_device_is_compatible(np, "qcom,sc7280-lpass-tx-macro")) { in tx_macro_probe()
2303 tx->regmap = devm_regmap_init_mmio(dev, base, &tx_regmap_config); in tx_macro_probe()
2304 if (IS_ERR(tx->regmap)) { in tx_macro_probe()
2305 ret = PTR_ERR(tx->regmap); in tx_macro_probe()
2311 tx->dev = dev; in tx_macro_probe()
2314 tx->active_decimator[TX_MACRO_AIF1_CAP] = -1; in tx_macro_probe()
2315 tx->active_decimator[TX_MACRO_AIF2_CAP] = -1; in tx_macro_probe()
2316 tx->active_decimator[TX_MACRO_AIF3_CAP] = -1; in tx_macro_probe()
2319 clk_set_rate(tx->mclk, MCLK_FREQ); in tx_macro_probe()
2320 clk_set_rate(tx->npl, MCLK_FREQ); in tx_macro_probe()
2322 ret = clk_prepare_enable(tx->macro); in tx_macro_probe()
2326 ret = clk_prepare_enable(tx->dcodec); in tx_macro_probe()
2330 ret = clk_prepare_enable(tx->mclk); in tx_macro_probe()
2334 ret = clk_prepare_enable(tx->npl); in tx_macro_probe()
2338 ret = clk_prepare_enable(tx->fsgen); in tx_macro_probe()
2344 if (tx->data->flags & LPASS_MACRO_FLAG_RESET_SWR) in tx_macro_probe()
2345 regmap_update_bits(tx->regmap, CDC_TX_CLK_RST_CTRL_SWR_CONTROL, in tx_macro_probe()
2348 regmap_update_bits(tx->regmap, CDC_TX_CLK_RST_CTRL_SWR_CONTROL, in tx_macro_probe()
2352 if (tx->data->flags & LPASS_MACRO_FLAG_RESET_SWR) in tx_macro_probe()
2353 regmap_update_bits(tx->regmap, CDC_TX_CLK_RST_CTRL_SWR_CONTROL, in tx_macro_probe()
2375 clk_disable_unprepare(tx->fsgen); in tx_macro_probe()
2377 clk_disable_unprepare(tx->npl); in tx_macro_probe()
2379 clk_disable_unprepare(tx->mclk); in tx_macro_probe()
2381 clk_disable_unprepare(tx->dcodec); in tx_macro_probe()
2383 clk_disable_unprepare(tx->macro); in tx_macro_probe()
2385 lpass_macro_pds_exit(tx->pds); in tx_macro_probe()
2392 struct tx_macro *tx = dev_get_drvdata(&pdev->dev); in tx_macro_remove()
2394 clk_disable_unprepare(tx->macro); in tx_macro_remove()
2395 clk_disable_unprepare(tx->dcodec); in tx_macro_remove()
2396 clk_disable_unprepare(tx->mclk); in tx_macro_remove()
2397 clk_disable_unprepare(tx->npl); in tx_macro_remove()
2398 clk_disable_unprepare(tx->fsgen); in tx_macro_remove()
2400 lpass_macro_pds_exit(tx->pds); in tx_macro_remove()
2407 regcache_cache_only(tx->regmap, true); in tx_macro_runtime_suspend()
2408 regcache_mark_dirty(tx->regmap); in tx_macro_runtime_suspend()
2410 clk_disable_unprepare(tx->fsgen); in tx_macro_runtime_suspend()
2411 clk_disable_unprepare(tx->npl); in tx_macro_runtime_suspend()
2412 clk_disable_unprepare(tx->mclk); in tx_macro_runtime_suspend()
2422 ret = clk_prepare_enable(tx->mclk); in tx_macro_runtime_resume()
2428 ret = clk_prepare_enable(tx->npl); in tx_macro_runtime_resume()
2434 ret = clk_prepare_enable(tx->fsgen); in tx_macro_runtime_resume()
2440 regcache_cache_only(tx->regmap, false); in tx_macro_runtime_resume()
2441 regcache_sync(tx->regmap); in tx_macro_runtime_resume()
2445 clk_disable_unprepare(tx->npl); in tx_macro_runtime_resume()
2447 clk_disable_unprepare(tx->mclk); in tx_macro_runtime_resume()
2502 .compatible = "qcom,sc7280-lpass-tx-macro",
2505 .compatible = "qcom,sm6115-lpass-tx-macro",
2508 .compatible = "qcom,sm8250-lpass-tx-macro",
2511 .compatible = "qcom,sm8450-lpass-tx-macro",
2514 .compatible = "qcom,sm8550-lpass-tx-macro",
2517 .compatible = "qcom,sc8280xp-lpass-tx-macro",