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/freebsd/sys/contrib/device-tree/Bindings/pinctrl/
H A Dpinctrl-st.txt3 Each multi-function pin is controlled, driven and routed through the
5 and multiple alternate functions(ALT1 - ALTx) that directly connect
14 GPIO bank can have one of the two possible types of interrupt-wirings.
17 reduces number of overall interrupts numbers required. All these banks belong to
20 | |----> [gpio-bank (n) ]
21 | |----> [gpio-bank (n + 1)]
22 [irqN]-- | irq-mux |----> [gpio-bank (n + 2)]
23 | |----> [gpio-bank (... )]
24 |_________|----> [gpio-bank (n + 7)]
26 Second type has a dedicated interrupt per gpio bank.
[all …]
H A Dmicrochip,sparx5-sgpio.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/microchip,sparx5-sgpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lars Povlsen <lars.povlsen@microchip.com>
14 the number of available GPIOs with a minimum number of additional
21 pattern: "^gpio@[0-9a-f]+$"
25 - microchip,sparx5-sgpio
26 - mscc,ocelot-sgpio
27 - mscc,luton-sgpio
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H A Dsamsung-pinctrl.txt6 on-chip controllers onto these pads.
9 - compatible: should be one of the following.
10 - "samsung,s3c2412-pinctrl": for S3C2412-compatible pin-controller,
11 - "samsung,s3c2416-pinctrl": for S3C2416-compatible pin-controller,
12 - "samsung,s3c2440-pinctrl": for S3C2440-compatible pin-controller,
13 - "samsung,s3c2450-pinctrl": for S3C2450-compatible pin-controller,
14 - "samsung,s3c64xx-pinctrl": for S3C64xx-compatible pin-controller,
15 - "samsung,s5pv210-pinctrl": for S5PV210-compatible pin-controller,
16 - "samsung,exynos3250-pinctrl": for Exynos3250 compatible pin-controller.
17 - "samsung,exynos4210-pinctrl": for Exynos4210 compatible pin-controller.
[all …]
H A Dallwinner,sun4i-a10-pinctrl.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/allwinner,sun4i-a10-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Che
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H A Dst,stm32-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/pinctrl/st,stm32-pinctrl.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Alexandre TORGUE <alexandre.torgue@foss.st.com>
17 on-chip controllers onto these pads.
22 - st,stm32f429-pinctrl
23 - st,stm32f469-pinctrl
24 - st,stm32f746-pinctrl
25 - st,stm32f769-pinctrl
[all …]
H A Dsamsung,pinctrl-gpio-bank.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/samsung,pinctrl-gpio-bank.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung S3C/S5P/Exynos SoC pin controller - gpio bank
10 - Krzysztof Kozlowski <krzk@kernel.org>
11 - Sylwester Nawrocki <s.nawrocki@samsung.com>
12 - Tomasz Figa <tomasz.figa@gmail.com>
18 GPIO bank description for Samsung S3C/S5P/Exynos SoC pin controller.
24 '#gpio-cells':
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/freebsd/sys/dts/
H A Dbindings-localbus.txt11 Value type: <prop-encoded-array> encoded as arbitrary number of localbus
18 a) child node address-cells:
19 - first cell: number of bank (chip select)
20 - second cell: (Marvell devices) Target ID for decoding
24 - address offset: used with parent's node base address to
27 c) child node size-cells:
28 - size: defines amount of memory that should be reserved for
31 1.2 bank-count
33 Property: bank-count
37 Description: The bank_count property defines maximum number of banks on
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/freebsd/sys/contrib/device-tree/Bindings/gpio/
H A Dbrcm,brcmstb-gpio.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/brcm,brcmstb-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 The controller's registers are organized as sets of eight 32-bit
11 registers with each set controlling a bank of up to 32 pins. A single
15 - Doug Berger <opendmb@gmail.com>
16 - Florian Fainelli <f.fainelli@gmail.com>
21 - enum:
22 - brcm,bcm7445-gpio
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H A Dbrcm,brcmstb-gpio.txt3 The controller's registers are organized as sets of eight 32-bit
4 registers with each set controlling a bank of up to 32 pins. A single
9 - compatible:
10 Must be "brcm,brcmstb-gpio"
12 - reg:
16 - #gpio-cells:
17 Should be <2>. The first cell is the pin number (within the controller's
19 bit[0]: polarity (0 for active-high, 1 for active-low)
21 - gpio-controller:
24 - brcm,gpio-bank-widths:
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H A Dbrcm,kona-gpio.txt8 support up to 8 banks of 32 GPIOs where each bank has its own IRQ. The
12 -------------------
14 - compatible: "brcm,bcm11351-gpio", "brcm,kona-gpio"
15 - reg: Physical base address and length of the controller's registers.
16 - interrupts: The interrupt outputs from the controller. There is one GPIO
17 interrupt per GPIO bank. The number of interrupts listed depends on the
18 number of GPIO banks on the SoC. The interrupts must be ordered by bank,
19 starting with bank 0. There is always a 1:1 mapping between banks and
21 - #gpio-cells: Should be <2>. The first cell is the pin number, the second
23 - bit 0 specifies polarity (0 for normal, 1 for inverted)
[all …]
H A Dgpio.txt5 -----------------
7 GPIO properties should be named "[<name>-]gpios", with <name> being the purpose
8 of this GPIO for the device. While a non-existent <name> is considered valid
10 for new bindings. Also, GPIO properties named "[<name>-]gpio" are valid and old
24 and bit-banged data signals:
27 gpio-controller;
28 #gpio-cells = <2>;
32 data-gpios = <&gpio1 12 0>,
44 recommended to use the two-cell approach.
48 include/dt-bindings/gpio/gpio.h whenever possible:
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/freebsd/sys/dev/qat/qat_common/
H A Dadf_transport.c1 /* SPDX-License-Identifier: BSD-3-Clause */
2 /* Copyright(c) 2007-2022 Intel Corporation */
28 return data - mult; in adf_modulo()
34 if (((size - 1) & addr) != 0) in adf_check_ring_alignment()
52 adf_reserve_ring(struct adf_etr_bank_data *bank, u32 ring) in adf_reserve_ring() argument
54 mtx_lock(&bank->lock); in adf_reserve_ring()
55 if (bank->ring_mask & (1 << ring)) { in adf_reserve_ring()
56 mtx_unlock(&bank->lock); in adf_reserve_ring()
59 bank->ring_mask |= (1 << ring); in adf_reserve_ring()
60 mtx_unlock(&bank->lock); in adf_reserve_ring()
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H A Dadf_freebsd_uio_cleanup.c1 /* SPDX-License-Identifier: BSD-3-Clause */
2 /* Copyright(c) 2007-2022 Intel Corporation */
45 int bank; member
51 * if orphan->tx_mask does not match with orphan->rx_mask
60 int tx_rx_gap = hw_data->tx_rx_gap; in check_orphan_ring()
61 u8 num_rings_per_bank = hw_data->num_rings_per_bank; in check_orphan_ring()
62 struct resource *csr_base = orphan->csr_base; in check_orphan_ring()
63 int bank = orphan->bank; in check_orphan_ring() local
66 if (test_bit(i, &orphan->tx_mask)) { in check_orphan_ring()
69 if (!test_bit(rx_ring, &orphan->rx_mask)) { in check_orphan_ring()
[all …]
/freebsd/sys/contrib/device-tree/Bindings/firmware/
H A Dcznic,turris-omnia-mcu.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/firmware/cznic,turris-omnia-mcu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marek Behún <kabel@kernel.org>
18 const: cznic,turris-omnia-mcu
27 interrupt-controller: true
29 '#interrupt-cells':
32 The first cell specifies the interrupt number (0 to 63), the second cell
37 IRQ number GPIO bank GPIO pin within bank
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/freebsd/sys/contrib/device-tree/Bindings/soc/fsl/cpm_qe/
H A Dgpio.txt1 Every GPIO controller node must have #gpio-cells property defined,
2 this information will be used to translate gpio-specifiers.
10 - compatible : "fsl,cpm1-pario-bank-a", "fsl,cpm1-pario-bank-b",
11 "fsl,cpm1-pario-bank-c", "fsl,cpm1-pario-bank-d",
12 "fsl,cpm1-pario-bank-e", "fsl,cpm2-pario-bank"
13 - #gpio-cells : Should be two. The first cell is the pin number and the
15 - gpio-controller : Marks the port as GPIO controller.
17 - fsl,cpm1-gpio-irq-mask : For banks having interrupt capability (like port C
20 - interrupts : This property provides the list of interrupt for each GPIO having
21 one as described by the fsl,cpm1-gpio-irq-mask property. There should be as
[all …]
/freebsd/sys/dev/smc/
H A Dif_smcreg.h1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
31 /* All Banks, Offset 0xe: Bank Select Register */
33 #define BSR_BANK_MASK 0x0007 /* Which bank is currently selected */
37 /* Bank 0, Offset 0x0: Transmit Control Register */
50 /* Bank 0, Offset 0x2: EPH Status Register */
67 /* Bank 0, Offset 0x4: Receive Control Register */
78 /* Bank 0, Offset 0x6: Counter Register */
89 /* Bank 0, Offset 0x8: Memory Information Register */
97 /* Bank 0, Offset 0xa: Receive/PHY Control Reigster */
[all …]
/freebsd/sys/contrib/device-tree/Bindings/mtd/
H A Dfsmc-nand.txt5 - compatible : "st,spear600-fsmc-nand", "stericsson,fsmc-nand"
6 - reg : Address range of the mtd chip
7 - reg-names: Should contain the reg names "fsmc_regs", "nand_data", "nand_addr" and "nand_cmd"
10 - bank-width : Width (in bytes) of the device. If not present, the width
12 - nand-skip-bbtscan: Indicates the BBT scanning should be skipped
13 - timings: array of 6 bytes for NAND timings. The meanings of these bytes
15 byte 0 TCLR : CLE to RE delay in number of AHB clock cycles, only 4 bits
19 byte 2 THIZ : number of HCLK clock cycles during which the data bus is
20 kept in Hi-Z (tristate) after the start of a write access.
23 byte 3 THOLD : number of HCLK clock cycles to hold the address (and data
[all …]
H A Dingenic,nand.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Paul Cercueil <paul@crapouillou.net>
13 - $ref: nand-controller.yaml#
14 - $ref: /schemas/memory-controllers/ingenic,nemc-peripherals.yaml#
19 - ingenic,jz4740-nand
20 - ingenic,jz4725b-nand
21 - ingenic,jz4780-nand
25 - description: Bank number, offset and size of first attached NAND chip
[all …]
/freebsd/sys/dev/ice/
H A Dice_nvm.c1 /* SPDX-License-Identifier: BSD-3-Clause */
67 cmd->cmd_flags |= ICE_AQC_NVM_FLASH_ONLY; in ice_aq_read_nvm()
71 cmd->cmd_flags |= ICE_AQC_NVM_LAST_CMD; in ice_aq_read_nvm()
72 cmd->module_typeid = CPU_TO_LE16(module_typeid); in ice_aq_read_nvm()
73 cmd->offset_low = CPU_TO_LE16(offset & 0xFFFF); in ice_aq_read_nvm()
74 cmd->offset_high = (offset >> 16) & 0xFF; in ice_aq_read_nvm()
75 cmd->lengt in ice_aq_read_nvm()
463 ice_get_flash_bank_offset(struct ice_hw * hw,enum ice_bank_select bank,u16 module) ice_get_flash_bank_offset() argument
537 ice_read_flash_module(struct ice_hw * hw,enum ice_bank_select bank,u16 module,u32 offset,u8 * data,u32 length) ice_read_flash_module() argument
574 ice_read_nvm_module(struct ice_hw * hw,enum ice_bank_select bank,u32 offset,u16 * data) ice_read_nvm_module() argument
597 ice_get_nvm_css_hdr_len(struct ice_hw * hw,enum ice_bank_select bank,u32 * hdr_len) ice_get_nvm_css_hdr_len() argument
634 ice_read_nvm_sr_copy(struct ice_hw * hw,enum ice_bank_select bank,u32 offset,u16 * data) ice_read_nvm_sr_copy() argument
660 ice_read_orom_module(struct ice_hw * hw,enum ice_bank_select bank,u32 offset,u16 * data) ice_read_orom_module() argument
683 ice_read_netlist_module(struct ice_hw * hw,enum ice_bank_select bank,u32 offset,u16 * data) ice_read_netlist_module() argument
851 ice_get_nvm_srev(struct ice_hw * hw,enum ice_bank_select bank,u32 * srev) ice_get_nvm_srev() argument
879 ice_get_nvm_ver_info(struct ice_hw * hw,enum ice_bank_select bank,struct ice_nvm_info * nvm) ice_get_nvm_ver_info() argument
936 ice_get_orom_srev(struct ice_hw * hw,enum ice_bank_select bank,u32 * srev) ice_get_orom_srev() argument
981 ice_get_orom_civd_data(struct ice_hw * hw,enum ice_bank_select bank,struct ice_orom_civd_info * civd) ice_get_orom_civd_data() argument
1058 ice_get_orom_ver_info(struct ice_hw * hw,enum ice_bank_select bank,struct ice_orom_info * orom) ice_get_orom_ver_info() argument
1110 ice_get_netlist_info(struct ice_hw * hw,enum ice_bank_select bank,struct ice_netlist_info * netlist) ice_get_netlist_info() argument
[all...]
/freebsd/sys/contrib/device-tree/Bindings/memory-controllers/
H A Dexynos-srom.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/exynos-srom.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzk@kernel.org>
19 - const: samsung,exynos4210-srom
24 "#address-cells":
27 "#size-cells":
34 Reflects the memory layout with four integer values per bank. Format:
35 <bank-number> 0 <parent address of bank> <size>
[all …]
/freebsd/sys/powerpc/powermac/
H A Dhrowpicvar.h1 /*-
2 * SPDX-License-Identifier: BSD-3-Clause
36 #define HROWPIC_IRQ_MASK ((HROWPIC_IRQMAX-1) >> 1) /* irq bit pos in word */
39 * Register offsets within bank. There are two identical banks,
40 * separated by 16 bytes. Interrupts 0->31 are processed in the
41 * second bank, and 32->63 in the first bank.
48 #define HPIC_PRIMARY 1 /* primary register bank */
49 #define HPIC_SECONDARY 0 /* secondary register bank */
52 * Convert an interrupt into a prim/sec bank number
58 * Convert an interrupt into the bit number within a bank register
[all …]
/freebsd/sys/contrib/device-tree/Bindings/interrupt-controller/
H A Dbrcm,bcm2835-armctrl-ic.txt1 BCM2835 Top-Level ("ARMCTRL") Interrupt Controller
3 The BCM2835 contains a custom top-level interrupt controller, which supports
4 72 interrupt sources using a 2-level register scheme. The interrupt
9 interrupts, but the per-CPU interrupt controller is the root, and an
14 - compatible : should be "brcm,bcm2835-armctrl-ic" or
15 "brcm,bcm2836-armctrl-ic"
16 - re
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/freebsd/sys/dev/qat_c2xxx/
H A Dqatvar.h1 /* SPDX-License-Identifier: BSD-2-Clause AND BSD-3-Clause */
31 * Copyright(c) 2007-2019 Intel Corporation. All rights reserved.
146 #define QAT_SIZE_TO_RING_SIZE_IN_BYTES(SIZE) ((1 << (SIZE - 1)) << 7)
147 #define QAT_RING_SIZE_IN_BYTES_TO_SIZE(SIZE) ((1 << (SIZE - 1)) >> 7)
158 ((((1 << (RING_SIZE - 1)) << 3) >> QAT_SIZE_TO_POW(MSG_SIZE)) - 1)
175 uint32_t qr_ring; /* ring number in bank */
176 uint32_t qr_bank; /* bank number in device */
195 uint32_t qb_bank; /* bank index */
234 ((sc)->sc_ae[ae])
238 u_int qae_ustore_size; /* free micro-store address */
[all …]
/freebsd/sys/dev/qat/qat_api/qat_kernel/src/
H A Dqat_transport.c1 /* SPDX-License-Identifier: BSD-3-Clause */
2 /* Copyright(c) 2007-2022 Intel Corporation */
23 return data - mult; in adf_modulo()
51 error = adf_create_ring(adf->accel_dev, in icp_adf_transCreateHandle()
115 * get ring number from a transport handle
124 *ringNum = (uint32_t)(ring->ring_number); in icp_adf_transGetRingNum()
166 * XXX: The qat_direct version of this routine returns max - 1, not in icp_adf_getInflightRequests()
169 *numInflightRequests = (*(uint32_t *)ring->inflights); in icp_adf_getInflightRequests()
171 ADF_MAX_INFLIGHTS(ring->ring_size, ring->msg_size); in icp_adf_getInflightRequests()
191 * ring number to be polled is supplied by the user via the
[all …]
/freebsd/sys/dev/qat/include/common/
H A Dadf_transport_access_macros.h1 /* SPDX-License-Identifier: BSD-3-Clause */
2 /* Copyright(c) 2007-2022 Intel Corporation */
54 #define ADF_SIZE_TO_RING_SIZE_IN_BYTES(SIZE) ((1 << (SIZE - 1)) << 7)
55 #define ADF_RING_SIZE_IN_BYTES_TO_SIZE(SIZE) ((1 << (SIZE - 1)) >> 7)
57 /* Set the response quota to a high number */
70 ((((1 << (RING_SIZE - 1)) << 3) >> ADF_SIZE_TO_POW(MSG_SIZE)) - 1)
79 #define READ_CSR_RING_HEAD(csr_base_addr, bank, ring) \ argument
81 (ADF_RING_BUNDLE_SIZE * bank) + ADF_RING_CSR_RING_HEAD + \
83 #define READ_CSR_RING_TAIL(csr_base_addr, bank, ring) \ argument
85 (ADF_RING_BUNDLE_SIZE * bank) + ADF_RING_CSR_RING_TAIL + \
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